9 INSTRUCTION OPCODES
     Figure 9-0.
     Table 9-0.
     Listing 9-0.



     This chapter lists and describes the opcodes that defines each of the
     instructions in the ADSP-219x’s instruction set. This information is use-
     ful for debugging programs.
     This chapter covers the following topics:
        • “Opcode Mnemonics” on page 9-1
        • “Opcode Definitions” on page 9-20


Opcode Mnemonics
     This section lists, describes, and gives the numeric value for each opcode
     mnemonic.

     Table 9-1. Opcode mnemonics

Mnemonic       Description                                              Details

AMF            Specifies an ALU or multiplier operation.                page 9-8

AS             Specifies whether ALU saturation mode is                 page 9-40
                  0 = disabled
                  1 = enabled

B              Specifies whether branch is                              page 9-32
                                                                        page 9-41
                  0 = immediate
                                                                        page 9-42
                  1 = delayed




                                      ADSP-219x Instruction Set Reference     9-1
Instruction Opcodes




      Table 9-1. Opcode mnemonics (Cont’d)

Mnemonic      Description                                                                 Details

BIT           Specifies which interrupt to enable or disable (0–15).                      page 9-60

BO            Specifies whether the supplied 4-bit constant in a type 9 instruction is    page 9-12
                                                                                          page 9-27
               01 = as is
               11 = negated

BR            Specifies whether bit-reverse addressing on DAG1 is                         page 9-40
               0 = disabled
               1 = enabled

BSR           Specifies whether the secondary DAG address registers are                   page 9-40
               0 = disabled
               1 = enabled

C             Specifies whether a software interrupt is                                   page 9-60
               0 = set
               1 = cleared

CC            Specifies the two LSBs of a 4-bit constant value in a type 9 instruction.   page 9-12
                                                                                          page 9-27

CF            Specifies whether to flush the instruction cache                            page 9-50
               0 = No flush
               1 = flush

COND          Specifies one of the condition codes on which to base execution of the      page 9-11
              instruction.




9-2       ADSP-219x Instruction Set Reference
    Table 9-1. Opcode mnemonics (Cont’d)

Mnemonic    Description                                                                   Details

D           Specifies the direction of a data move.                                       page 9-22
                                                                                          page 9-35
             0 = read
                                                                                          page 9-51
             1 = write                                                                    page 9-54
                                                                                          page 9-57
                                                                                          page 9-58

DD          Specifies a destination data register for a DM bus transfer.                  page 9-21
             00 = AX0
             01 = AX1
             10 = MX0
             11 = MX1

DDREG       Specifies a destination register for a register-to-register move operation.   page 9-13

DREG        Specifies an unrestricted data register (REG0 only).                          page 9-13

DMI         Specifies a DAG index address register (I0–I3) for a DM bus transfer.         page 9-18
                                                                                          page 9-21

DMM         Specifies a DAG modify address register (M0–M3) for a DM bus trans-           page 9-18
            fer.                                                                          page 9-21

DRGP        Specifies a destination register group.                                       page 9-39
             00 = REG0
             01 = REG1
             10 = REG2
             11 = REG3

DRL         Specifies two MSBs of DREG data register address.                             page 9-13

DRU         Specifies two LSBs of DREG data register address.                             page 9-13

Exponent    Specifies an 8-bit, two’s-complement shift value.                             page 9-37




                                    ADSP-219x Instruction Set Reference                         9-3
Instruction Opcodes




      Table 9-1. Opcode mnemonics (Cont’d)

Mnemonic         Description                                                       Details

G                Specifies a DAG register group.                                   page 9-17
                 0 = DAG1
                 1 = DAG2

IREG/MREG        Specifies DAG index and modify registers (I0–I7, M0–M7).          page 9-18

I                Specifies DAG index register (I0–I7).                             page 9-17

Idle Value       Specifies a 4-bit value that defines an internal clock divisor.   page 9-53

INT              Specifies whether interrupts are globally                         page 9-40
                 0 = disabled
                 1 = enabled

LPP              Specifies push/pop of the loop stacks.                            page 9-50
                 0 = disabled
                 1 = enabled

M                Specifies a DAG modify register.                                  page 9-17

MM               Specifies whether MAC integer mode is                             page 9-40
                 0 = disabled
                 1 = enabled

MOD DATA         Specifies an 8-bit, two’s-complement immediate data value.        page 9-44
                                                                                   page 9-51

MS               Specifies memory bus for a memory data transfer                   page 9-54
                 0 = 16-bit DM bus
                 1 = 24-bit PM bus




9-4          ADSP-219x Instruction Set Reference
     Table 9-1. Opcode mnemonics (Cont’d)

Mnemonic     Description                                                             Details

OL           Specifies whether ALU overflow mode is                                  page 9-40
              0 = disabled
              1 = enabled

PD           Specifies a destination data register for a PM bus transfer.            page 9-21
              00 = AY0
              01 = AY1
              10 = MY0
              11 = MY1

PMI          Specifies a DAG index address register (I4–I7) for a PM bus transfer.   page 9-18

PMM          Specifies a DAG modify address register (M4–M7) for a PM bus trans-     page 9-18
             fer.

PPP          Specifies push/pop of the PC stack.                                     page 9-50
              0 = disabled
              1 = enabled

Q            Specifies the RTI mode.                                                 page 9-42
              0 = normal
              1 = single-step

R            Specifies a result register.                                            page 9-49
              0 = MR register
              1 = SR register

REG          Specifies a core register of RGPx.                                      page 9-13

REG1         Specifies a register group 1 register                                   page 9-13
                                                                                     page 9-25




                                       ADSP-219x Instruction Set Reference                 9-5
Instruction Opcodes




      Table 9-1. Opcode mnemonics (Cont’d)

Mnemonic      Description                                                     Details

REG2          Specifies a register group 2 register                           page 9-13
                                                                              page 9-25

REG3          Specifies a register group 3 register                           page 9-13
                                                                              page 9-56

RGP           Specifies a register group.                                     page 9-13
               00 = REG0
               01 = REG1
               10 = REG2
               11 = REG3.

S             Specifies the branch type.                                      page 9-32
                                                                              page 9-41
               0 = jump
               1 = call

SDREG         Specifies the source data register for a data move operation.   page 9-13

SF            Specifies a shift function.                                     page 9-15

SPP           Specifies push/pop of the status stack.                         page 9-50
               0 = disabled
               1 = enabled

SR            Specifies whether the secondary data registers are              page 9-40
               0 = disabled
               1 = enabled




9-6       ADSP-219x Instruction Set Reference
     Table 9-1. Opcode mnemonics (Cont’d)

Mnemonic     Description                                                                  Details

SRGP         Specifies a source register group for a data move operation.                 page 9-39
              00 = REG0
              01 = REG1
              10 = REG2
              11 = REG3

SWCD         Specifies a 4-bit nonfunctional value used by ADI tools only.                page 9-52

T            Specifies the return type.                                                   page 9-42
              0 = RTS
              1 = RTI

TERM         Specifies the terminating condition for the type 11 instruction.             page 9-34
              1110 = NOT CE
              1111 = TRUE

TI           Specifies whether the timer is                                               page 9-40
              0 = disabled
              1 = enabled

U            Specifies whether the DAG index register is                                  page 9-54
              0 = premodified with no update
              1 = postmodified with update

XOP          Specifies a restricted data register used to supply the x operand value in   page 9-19
             a multifunction or conditional instruction.

XREG         Specifies the source register (REG0) in a shift function.                    page 9-13




                                     ADSP-219x Instruction Set Reference                        9-7
Instruction Opcodes




      Table 9-1. Opcode mnemonics (Cont’d)

Mnemonic       Description                                                                  Details

Y0             Specifies whether the source of the x-operand is                             page 9-11
                0 = data register
                1 = 0 (explicit value)

YOP            Specifies a restricted data register used to supply the y operand value in   page 9-19
               a multifunction or conditional instruction.

YREG           Specifies the destination register (REG0) in a shift function.               page 9-13
                                                                                            page 9-11

YY             Specifies the two MSBs of a 4-bit constant value in a type 9 instruc-        page 9-12
               tion.                                                                        page 9-27

Z              Specifies a result or feedback register                                      page 9-23
                                                                                            page 9-26
                0 = result register
                                                                                            page 9-27
                1 = feedback register                                                       page 9-11


ALU or Multiplier Function (AMF) Codes
      Table 9-2 on page 9-9 lists the AMF codes used by these instruction types:
         • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
         • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
         • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
         • “Type 9: Compute” on page 9-27




9-8        ADSP-219x Instruction Set Reference
   Table 9-2. ALU/multiplier function (AMF) codes

Code     Function              Description

Multiplier functions

00000    NOP                   No operation

00001    X * Y (RND)           Multiply

00010    MR + X * Y (RND)      Multiply and accumulate

00011    MR – X * Y (RND)      Multiply and subtract

00100    X * Y (SS)            Multiply

00101    X * Y (SU)            Multiply

00110    X * Y (US)            Multiply

00111    X * Y (UU)            Multiply

01000    MR + X * Y (SS)       Multiply and accumulate

01001    MR + X * Y (SU)       Multiply and accumulate

01010    MR + X * Y (US)       Multiply and accumulate

01011    MR + X * Y (UU)       Multiply and accumulate

01100    MR – X * Y (SS)       Multiply and subtract

01101    MR – X * Y (SU)       Multiply and subtract

01110    MR – X * Y (US)       Multiply and subtract

01111    MR – X * Y (UU)       Multiply and subtract

(RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned;
(US) =x operand unsigned, y operand signed; (UU) = both operands unsigned




                                      ADSP-219x Instruction Set Reference                    9-9
Instruction Opcodes




    Table 9-2. ALU/multiplier function (AMF) codes (Cont’d)

Code     Function               Description

ALU functions

10000    Y                      PASS/CLEAR

10001    Y+1                    PASS

10010    X+Y+C                  Add with carry

10011    X+Y                    Add

10100    NOT Y                  Negate

10101    –Y                     PASS

10110    X–Y+C–1                Subtract (X–Y) with borrow

10111    X–Y                    Subtract

11000    Y–1                    PASS

11001    Y–X                    Subtract

11010    Y–X+C–1                Subtract (Y–X) with borrow

11011    NOT X                  Negate

11100    X AND Y                AND/test bit,clear bit

11101    X OR Y                 OR/set bit

11110    X XOR Y                XOR/toggle bit

11111    ABS X                  Absolute value

 (RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned;
 (US) =x operand unsigned, y operand signed; (UU) = both operands unsigned




9-10         ADSP-219x Instruction Set Reference
Condition Codes
  Table 9-3 on page 9-11 lists the condition codes used by these instruction
  types:
       • “Type 9: Compute” on page 9-27
       • “Type 10: Direct Jump” on page 9-32
       • “Type 16: Shift Reg0” on page 9-38
       • “Type 19: Indirect Jump/Call” on page 9-41
       • “Type 20: Return” on page 9-42
       • “Type 36: Long Jump/Call” on page 9-59
       • “Type 11: Do ··· Until” on page 9-34
         uses NOT CE and TRUE only for the terminating condition.

  Table 9-3. Condition codes

Code   Condition      Description

0000   EQ             Equal to 0 (= 0)

0001   NE             Not equal to 0 (≠ 0)

0010   GT             Greater than 0 (>0)

0011   LE             Less than or equal to 0 (≤0)

0100   LT             Less than 0 (<0)

0101   GE             Greater than or equal to 0 (≥0)

0110   AV             ALU overflow

0111   NOT AV         Not ALU overflow




                             ADSP-219x Instruction Set Reference       9-11
Instruction Opcodes




      Table 9-3. Condition codes (Cont’d)

Code      Condition       Description

1000      AC              ALU carry

1001      NOT AC          Not ALU carry

1010      SWCOND          CCODE register condition

1011      NOT SWCOND      Not CCODE register condition

1100      MV              MAC overflow

1101      NOT MV          Not MAC overflow

1110      NOT CE          Counter not expired

1111      TRUE            Always true


Constant Codes
      Table 9-4 lists the valid constants used by “Type 9: Compute” on
      page 9-27. As shown, the YY/CC bits determine the constant value and the
      BO bits determine the sign of the value.


      Table 9-4. Constants

Code                     Decimal / Hex                   Decimal / Hex

YY             CC        BO = 01                         BO = 11

 00            00        1 / 0x0001                      −2 / 0xFFFE

 00            01        2 / 0x0002                      −3 / 0xFFFD

 00            10        4 / 0x0004                      −5 / 0xFFFB

 00            11        8 / 0x0008                      −9 / 0xFFF7




9-12        ADSP-219x Instruction Set Reference
      Table 9-4. Constants (Cont’d)

Code                       Decimal / Hex                Decimal / Hex

YY             CC          BO = 01                      BO = 11

 01            00          16 / 0x0010                   −17 / 0xFFEF

 01            01          32 / 0x0020                   −33 / 0xFFDF

 01            10          64 / 0x0040                   −65 / 0xFFBF

 01            11          128 / 0x0080                  −129 / 0xFF7F

 10            00          256 / 0x0100                  −257 / 0xFEFF

 10            01          512 / 0x0200                  −513 / 0xFDFF

 10            10          1024 / 0x0400                 −1025 / 0xFBFF

 10            11          2048 / 0x0800                 −2049 / 0xF7FF

 11            00          4096 / 0x1000                 −4097 / 0xEFFF

 11            01          8192 / 0x2000                 −8193 / 0xDFFF

 11            10          16384 / 0x4000                −16385 / 0xBFFF

 11            11          −32768 / 0x8000               +32767 / 0x7FFF


Core Register Codes
      Table 9-5 on page 9-14 list the core registers and their addresses. The
      complete address of any individual register is formed by appending the
      register’s address bits to its RGP bits, so, for example, the address of the I2
      register is 010010. The opcode mnemonics DREG, DDREG, SDREG, XREG, and
      YREG and the following instruction types reference these registers by their
      address bits:
         • “Type 3: Dreg/Ireg/Mreg «···» DM/PM” on page 9-22



                                  ADSP-219x Instruction Set Reference          9-13
Instruction Opcodes




          • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
          • “Type 6: Dreg «··· Data16” on page 9-24
          • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
          • “Type 9: Compute” on page 9-27
          • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
          • “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
          • “Type 15: Shift Data8” on page 9-37
          • “Type 16: Shift Reg0” on page 9-38
          • “Type 17: Any Reg «··· Any Reg” on page 9-39
          • “Type 34: Dreg «···» IOreg” on page 9-57
          • “Type 35: Dreg «···»Sreg” on page 9-58

   Table 9-5. Core registers

RGP/Address        Register Groups (RGP)

Address            00 (REG0)       01 (REG1)   10 (REG2)       11 (REG3)

0000               AX0             I0          I4              ASTAT

0001               AX1             I1          I5              MSTAT

0010               MX0             I2          I6              SSTAT

0011               MX1             I3          I7              LPSTACKP

0100               AY0             M0          M4              CCODE

0101               AY1             M1          M5              SE

0110               MY0             M2          M6              SB




9-14        ADSP-219x Instruction Set Reference
   Table 9-5. Core registers (Cont’d)

RGP/Address        Register Groups (RGP)

Address            00 (REG0)       01 (REG1)    10 (REG2)      11 (REG3)

0111               MY1             M3           M7             PX

1000               MR2             L0           L4             DMPG1

1001               SR2             L1           L5             DMPG2

1010               AR              L2           L6             IOPG

1011               SI              L3           L7             IJPG

1100               MR1             IMASK        Reserved       Reserved

1101               SR1             IRPTL        Reserved       Reserved

1110               MR0             ICNTL        CNTR           Reserved

1111               SR0             STACKA       LPSTACKA       STACKP


SF Function Codes
   Table 9-6 list the shift function (SF) codes used by these instruction types:
          • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
          • “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
          • “Type 15: Shift Data8” on page 9-37
            —shift functions (codes 0000–0111) only
          • “Type 16: Shift Reg0” on page 9-38




                                 ADSP-219x Instruction Set Reference       9-15
Instruction Opcodes




   Table 9-6. SF codes

Code               Function

 0000               LSHIFT (HI)

 0001               LSHIFT (HI, OR)

 0010               LSHIFT (LO)

 0011               LSHIFT (LO, OR)

 0100               ASHIFT (HI)

 0101               ASHIFT (HI, OR)

 0110               ASHIFT (LO)

 0111               ASHIFT (LO, OR)

 1000               NORM (HI)

 1001               NORM (HI, OR)

 1010               NORM (LO)

 1011               NORM (LO, OR)

 1100               EXP (HI)

 1101               EXP (HIX)

 1110               EXP (LO)

 1111               Derive Block Exponent




9-16     ADSP-219x Instruction Set Reference
I and M Codes
     Table 9-7 on page 9-17 lists the DAG index and modify register codes
     used by the following instruction types. The G bit (DAG1/DAG2) determines
     which group of I (index) and M (modify) registers.
        •   “Type 4: Compute | Dreg «···» DM/PM” on page 9-23.
        • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
        • “Type 19: Indirect Jump/Call” on page 9-41
        • “Type 21: Modify DagI” on page 9-43
        • “Type 21a: Modify DagI” on page 9-44
        • “Type 22: DM/PM «··· Data16” on page 9-45
        • “Type 29: Dreg «···» DM” on page 9-51
        • “Type 32: Any Reg «···» PM/DM” on page 9-54

     Table 9-7. I and M codes

               DAG1 (G=0)                      DAG2 (G=1)

Code           I                M              I               M

00             I0               M0             I4              M4

01             I1               M1             I5              M5

10             I2               M2             I6              M6

11             I3               M3             I7              M7




                                ADSP-219x Instruction Set Reference      9-17
Instruction Opcodes




DMI, DMM, PMI, and PMM Codes
      Table 9-8 lists the DAG index and modify register codes used by “Type 1:
      Compute | DregX«···DM | DregY«···PM” on page 9-21.

      Table 9-8. DMI, DMM, PMI, PMM codes

Code            DMI             DMM              PMI            PMM

 00             I0              M0               I4                 M4

 01             I1              M1               I5                 M5

 10             I2              M2               I6                 M6

 11             I3              M3               I7                 M7


IREG/MREG Codes
      Table 9-9 lists the Ireg and Mreg codes used by “Type 3: Dreg/Ireg/Mreg
      «···» DM/PM” on page 9-22 to specify a DAG index or modify register.

      Table 9-9. Ireg, Mreg codes

Code                 Register            Code            Register

 0000                I0                   1000            M0

 0001                I1                   1001            M1

 0010                I2                   1010            M2

 0011                I3                   1011            M3

 0100                I4                   1100            M4

 0101                I5                   1101            M5




9-18        ADSP-219x Instruction Set Reference
   Table 9-9. Ireg, Mreg codes (Cont’d)

Code              Register                     Code          Register

0110               I6                          1110          M6

0111               I7                          1111          M7


XOP and YOP Codes
   Table 9-10 on page 9-19 lists the XOP and YOP codes used by these
   instructions:
       • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
       • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
       • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
       • “Type 9: Compute” on page 9-27
       • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
       • “Type 23: Divide primitive, DIVQ” on page 9-47
       • “Type 24: Divide primitive, DIVS” on page 9-48

   Table 9-10. XOP/YOP codes

             XOP                                              YOP

Code         ALU             MAC       Shift          Code    ALU        MAC

 000         AX0             MX0       SI             00      AY0        MY0

 001         AX1             MX1       SR2            01      AY1        MY1

 010         AR              AR        AR             10      AF         SR1




                                   ADSP-219x Instruction Set Reference         9-19
Instruction Opcodes




   Table 9-10. XOP/YOP codes

              XOP                                          YOP

 Code         ALU       MAC        Shift     Code          ALU        MAC

 011           MR0       MR0       MR0        11           0          0

 100           MR1       MR1       MR1

 101           MR2       MR2       MR2

 110           SR0       SR0       SR0

 111           SR1       SR1       SR1



Opcode Definitions
