r2plugin/asm_adsp219x.so

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<EFBFBD><EFBFBD><EFBFBD>H<EFBFBD><03><01><><EFBFBD>H<><48>H<><48><08>MRARIF  (DB)RTIRTS, SR+=+PMDMCLRINTSETINTIDLE 0x%XDM(0x%04X) = %s%s = DM(0x%04X)%s%s%s%s = %s(%s^2)%s%s%s%s = %s(%s, 0)%s%s%s%s = %s(%s, %s)%s%s%s%s = %s(%s, %d)NONE = %s(%s, %s)%s(%s, %s), %s = %s%s = 0x%04Xtrunc L%s 0x%06XLJUMPLCALLtrunc DM_IMM16 0x%06X%cM(I%d += M%d) = 0x%04Xtrunc PM_IMM24 0x%06XPM(I%d += M%d) = 0x%06X:24%s 0x%06lx%sIF %s JUMP 0x%06lx%sIF %s %s%s%s %s, %cM(I%d += M%d) = %s%s %s, %s = %cM(I%d += M%d)%s %s, %s = %sIF %s SR = %s %sDO 0x%06lx UNTIL %sSR = %s %s BY %d%sDIS %s%sENA %sMODE NOPSAT %s%s = 0x%03XIF %s %s (I%d)%sMODIFY(I%d += M%d)DIVQ %sDIVS %s, %s%sPUSH PC%sPOP PC%sPUSH LOOP%sPOP LOOP%sPUSH STS%sPOP STSSTACK NOPDM(I%d %s %d) = %s%s = DM(I%d %s %d)%s(I%d %s M%d) = %s%s = %s(I%d %s M%d)DM(I%d %s M%d) = %s, %s = I%dMODIFY(I%d += %d)IO(0x%03X) = %s%s = IO(0x%03X)REG(0x%02X) = %s%s = REG(0x%02X)%s %dunk 0x%06XIF %s %s 0x%06XSDBROLASMM6.1.3adsp219xADSP-219x Master PluginDr. Christian GiessenLGPL-3.0-onlyMY0MY1SR1AY0AY1AFSISR2MR0MR1MR2SR0MX0MX1AX0AX1LSHIFT (HI)LSHIFT (HI, OR)LSHIFT (LO)LSHIFT (LO, OR)ASHIFT (HI)ASHIFT (HI, OR)ASHIFT (LO)ASHIFT (LO, OR)NORM (HI)NORM (HI, OR)NORM (LO)NORM (LO, OR)EXP (HI)EXP (HIX)EXP (LO)Derive Block ExponentY+1X+Y+CX+YNOT YX-Y+C-1X-YY-1Y-XY-X+C-1NOT XX AND YX OR YX XOR YABS XMR+X*Y (RND)MR-X*Y (RND)MR+X*Y (SS)MR+X*Y (SU)MR+X*Y (US)MR+X*Y (UU)MR-X*Y (SS)MR-X*Y (SU)MR-X*Y (US)MR-X*Y (UU)ASTATMSTATSSTATLPSTACKPCCODESESBPXDMPG1DMPG2IOPGIJPGRESI4I5I6I7M4M5M6M7L4L5L6L7CNTRLPSTACKAI0I1I2I3M0M1M2M3L0L1L2L3IMASKIRPTLICNTLEQNEGTLELTGENOT AVNOT ACNOT SWCONDNOT MVNOT CETRUE%s, %s=DM(I%d+=M%d), %s=PM(I%d+=M%d)`<60><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><05><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>'<27><><EFBFBD>;0<0C><><EFBFBD>LL<><4C><EFBFBD>t<1C>
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@78 `E<00>]NGap`m<00>_<00>	 <00> <00>@`0<00><00> X<00><00> <00><00> &"crtstuff.cderegister_tm_clones__do_global_dtors_auxcompleted.0__do_global_dtors_aux_fini_array_entryframe_dummy__frame_dummy_init_array_entryasm_adsp219x.cget_regreg0reg3reg2reg1archinfodecodecond_stramf_aluamf_macxop_macyop_macsf_namesmbits.0xop_aluyop_aluxop_shift__FRAME_END___fini__dso_handle_DYNAMIC__GNU_EH_FRAME_HDR__TMC_END___GLOBAL_OFFSET_TABLE__init_ITM_deregisterTMCloneTableradare_pluginsnprintf@GLIBC_2.2.5r_arch_plugin_adsp219x__gmon_start__r_str_newf_ITM_registerTMCloneTablestrdup@GLIBC_2.2.5__cxa_finalize@GLIBC_2.2.5.symtab.strtab.shstrtab.note.gnu.build-id.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rela.dyn.rela.plt.init.plt.got.text.fini.rodata.eh_frame_hdr.eh_frame.init_array.fini_array.data.rel.ro.dynamic.got.plt.data.bss.comment88$.<00><><EFBFBD>o``(8<00><00><00>@xx<00>H<00><><EFBFBD>o00U<00><><EFBFBD>oHH dhh@nB<00><00>Hx  s    @~` ` <00>p p <00><00>@7@7	<00>@@<00>GG4<00>HGHGt<00><00>W<00>W<00><00>W<00>W<00><00>W<00>W <00><00>]<00>]<00><00><00>_<00>_ <00><00>_<00>_0<00> ` `P <00>p`p`<00>0p`<00>`P%	<00>dA!g<00>
-												Fix reg1/reg2 tables: CNTR is REG2[14], STACKA is REG1[15]

Register tables were wrong per the official core register table
(docs/opcode_mnemonics.txt Table 9-5):
- reg1[15]: was CNTR, should be STACKA
- reg2[12]: was STACKA, should be RES (reserved)
- reg2[13]: was LPCSTACKA, should be RES (reserved)
- reg2[14]: was RES, should be CNTR
- reg2[15]: was RES, should be LPSTACKA

This fixes CNTR loads showing as 'RES = ...' in disassembly.
Verified: isa_test.bin now shows CNTR = 0x000A,
iir.bin shows CNTR = 0x0100 and CNTR = 0x0002.

											
										
										
											2026-04-22 20:36:54 +00:00
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-												Verify and fix gap types against assembler output

Assembler-verified and fixed:
- Type 12: XOP field corrected to bits10-8 (was bits11-9)
- Type 14: SF=4bits, XREG uses reg0[] not xop_shift[] (was 3-bit OOB)
- Type 16: XREG uses reg0[] (was xop_shift[], 4-bit index OOB)
- Type 19: I-reg field at bits3-2 (was bits1-0), now correct for jump(i2)
- Type 26: Push/Pop encoding is 10/11 not 01/10;
  PPP=bits6-5, LPP=bits4-3 (was bits6-4, bits3-2)
  All 6 variants verified: push/pop sts, loop, pc

Assembler-verified unchanged:
- Type 21/21a: MODIFY correct
- Type 23/24: DIVQ/DIVS correct
- Type 29: DM immediate modify read/write correct
- Type 32: Any Reg <-> DM read/write correct
- Type 34/35: IO/System register read/write correct
- Type 36: LJUMP 2-word correct
- Type 37: SETINT/CLRINT correct

Remaining note: Type 12 SF field may use a different mapping
than sf_names[] for combined shift+memory ops (ASHIFT encodes
as SF=2 not SF=4). Needs further investigation.

											
										
										
											2026-04-22 20:16:30 +00:00
+								A<><41><0F><>
-												Fix Type 12 SF field and sync TESTING.md

Type 12: SF is 4 bits (15-12), D is bit11 (not SF=3bits, D=bit12).
  Verified all 8 SF variants against assembler: LSHIFT/ASHIFT,
  HI/LO, plain/OR.  FIR output scaling chain now correct.

TESTING.md: Synced with actual verification status.
  34 of 37 types now assembler-verified.
  Only Type 22/22a (2-word data write), Type 31 (IDLE), and
  Type 32a (DAG store+transfer) remain structural-only.

Removed build artifacts (.o, .elf) from examples/build/.

											
										
										
											2026-04-22 20:19:41 +00:00
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-												Fix reg1/reg2 tables: CNTR is REG2[14], STACKA is REG1[15]

Register tables were wrong per the official core register table
(docs/opcode_mnemonics.txt Table 9-5):
- reg1[15]: was CNTR, should be STACKA
- reg2[12]: was STACKA, should be RES (reserved)
- reg2[13]: was LPCSTACKA, should be RES (reserved)
- reg2[14]: was RES, should be CNTR
- reg2[15]: was RES, should be LPSTACKA

This fixes CNTR loads showing as 'RES = ...' in disassembly.
Verified: isa_test.bin now shows CNTR = 0x000A,
iir.bin shows CNTR = 0x0100 and CNTR = 0x0002.

											
										
										
											2026-04-22 20:36:54 +00:00
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-												Fix Type 12 SF field and sync TESTING.md

Type 12: SF is 4 bits (15-12), D is bit11 (not SF=3bits, D=bit12).
  Verified all 8 SF variants against assembler: LSHIFT/ASHIFT,
  HI/LO, plain/OR.  FIR output scaling chain now correct.

TESTING.md: Synced with actual verification status.
  34 of 37 types now assembler-verified.
  Only Type 22/22a (2-word data write), Type 31 (IDLE), and
  Type 32a (DAG store+transfer) remain structural-only.

Removed build artifacts (.o, .elf) from examples/build/.

											
										
										
											2026-04-22 20:19:41 +00:00
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-												Fix reg1/reg2 tables: CNTR is REG2[14], STACKA is REG1[15]

Register tables were wrong per the official core register table
(docs/opcode_mnemonics.txt Table 9-5):
- reg1[15]: was CNTR, should be STACKA
- reg2[12]: was STACKA, should be RES (reserved)
- reg2[13]: was LPCSTACKA, should be RES (reserved)
- reg2[14]: was RES, should be CNTR
- reg2[15]: was RES, should be LPSTACKA

This fixes CNTR loads showing as 'RES = ...' in disassembly.
Verified: isa_test.bin now shows CNTR = 0x000A,
iir.bin shows CNTR = 0x0100 and CNTR = 0x0002.

											
										
										
											2026-04-22 20:36:54 +00:00
+								<EFBFBD><EFBFBD><EFBFBD>H<EFBFBD><03><01><><EFBFBD>H<><48>H<><48><08>MRARIF  (DB)RTIRTS, SR+=+PMDMCLRINTSETINTIDLE 0x%XDM(0x%04X) = %s%s = DM(0x%04X)%s%s%s%s = %s(%s^2)%s%s%s%s = %s(%s, 0)%s%s%s%s = %s(%s, %s)%s%s%s%s = %s(%s, %d)NONE = %s(%s, %s)%s(%s, %s), %s = %s%s = 0x%04Xtrunc L%s 0x%06XLJUMPLCALLtrunc DM_IMM16 0x%06X%cM(I%d += M%d) = 0x%04Xtrunc PM_IMM24 0x%06XPM(I%d += M%d) = 0x%06X:24%s 0x%06lx%sIF %s JUMP 0x%06lx%sIF %s %s%s%s %s, %cM(I%d += M%d) = %s%s %s, %s = %cM(I%d += M%d)%s %s, %s = %sIF %s SR = %s %sDO 0x%06lx UNTIL %sSR = %s %s BY %d%sDIS %s%sENA %sMODE NOPSAT %s%s = 0x%03XIF %s %s (I%d)%sMODIFY(I%d += M%d)DIVQ %sDIVS %s, %s%sPUSH PC%sPOP PC%sPUSH LOOP%sPOP LOOP%sPUSH STS%sPOP STSSTACK NOPDM(I%d %s %d) = %s%s = DM(I%d %s %d)%s(I%d %s M%d) = %s%s = %s(I%d %s M%d)DM(I%d %s M%d) = %s, %s = I%dMODIFY(I%d += %d)IO(0x%03X) = %s%s = IO(0x%03X)REG(0x%02X) = %s%s = REG(0x%02X)%s %dunk 0x%06XIF %s %s 0x%06XSDBROLASMM6.1.3adsp219xADSP-219x Master PluginDr. Christian GiessenLGPL-3.0-onlyMY0MY1SR1AY0AY1AFSISR2MR0MR1MR2SR0MX0MX1AX0AX1LSHIFT (HI)LSHIFT (HI, OR)LSHIFT (LO)LSHIFT (LO, OR)ASHIFT (HI)ASHIFT (HI, OR)ASHIFT (LO)ASHIFT (LO, OR)NORM (HI)NORM (HI, OR)NORM (LO)NORM (LO, OR)EXP (HI)EXP (HIX)EXP (LO)Derive Block ExponentY+1X+Y+CX+YNOT YX-Y+C-1X-YY-1Y-XY-X+C-1NOT XX AND YX OR YX XOR YABS XMR+X*Y (RND)MR-X*Y (RND)MR+X*Y (SS)MR+X*Y (SU)MR+X*Y (US)MR+X*Y (UU)MR-X*Y (SS)MR-X*Y (SU)MR-X*Y (US)MR-X*Y (UU)ASTATMSTATSSTATLPSTACKPCCODESESBPXDMPG1DMPG2IOPGIJPGRESI4I5I6I7M4M5M6M7L4L5L6L7CNTRLPSTACKAI0I1I2I3M0M1M2M3L0L1L2L3IMASKIRPTLICNTLEQNEGTLELTGENOT AVNOT ACNOT SWCONDNOT MVNOT CETRUE%s, %s=DM(I%d+=M%d), %s=PM(I%d+=M%d)`<60><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><05><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>'<27><><EFBFBD>;0<0C><><EFBFBD>LL<><4C><EFBFBD>t<1C>
-												Fix Type 12 SF field and sync TESTING.md

Type 12: SF is 4 bits (15-12), D is bit11 (not SF=3bits, D=bit12).
  Verified all 8 SF variants against assembler: LSHIFT/ASHIFT,
  HI/LO, plain/OR.  FIR output scaling chain now correct.

TESTING.md: Synced with actual verification status.
  34 of 37 types now assembler-verified.
  Only Type 22/22a (2-word data write), Type 31 (IDLE), and
  Type 32a (DAG store+transfer) remain structural-only.

Removed build artifacts (.o, .elf) from examples/build/.

											
										
										
											2026-04-22 20:19:41 +00:00
+								<00><00>_H<00>h@	<00><><EFBFBD>oH<00><><EFBFBD>o<00><><EFBFBD>o0<00><><EFBFBD>o<00><00>]6 F V  `<00>CGCC: (Debian 14.2.0-19) 14.2.0<00><>p <00> !<00> 7p`C<00>Wj !v<00>W<00><00><><00>0!L<00><00>\<00><00>`[<00><00><00>[<00><00>`\<00><00><00>!<00><00>!<00><00>`]<00><00>`Z<00><00><00>Z<00><00>`Y@<00><00>X <00><00>Y<00><00>W@
-												Fix reg1/reg2 tables: CNTR is REG2[14], STACKA is REG1[15]

Register tables were wrong per the official core register table
(docs/opcode_mnemonics.txt Table 9-5):
- reg1[15]: was CNTR, should be STACKA
- reg2[12]: was STACKA, should be RES (reserved)
- reg2[13]: was LPCSTACKA, should be RES (reserved)
- reg2[14]: was RES, should be CNTR
- reg2[15]: was RES, should be LPSTACKA

This fixes CNTR loads showing as 'RES = ...' in disassembly.
Verified: isa_test.bin now shows CNTR = 0x000A,
iir.bin shows CNTR = 0x0100 and CNTR = 0x0002.

											
										
										
											2026-04-22 20:36:54 +00:00
+								<00>Y@Y  Y@<00><>$<00>H<00><>2
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