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Rewrite Type 9/9a decode: five sub-encodings

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Type 9a (register-file, unconditional):
  - XREG=bits11-8 (4 bits), YREG=bits3-0 (4 bits), both reg0[]
  - Discriminated by bits5-4 = 10
  - Verified: ar=mx0 xor my0, mr=ax0*ay0(ss)

Type 9 standard (conditional):
  - XOP=bits10-8, YOP=bits12-11, COND=bits3-0
  - bits7-4 = 0000 required
  - Verified: all ALU ops, conditional MAC

Type 9 YOP=0:
  - bits12-11 = 11, bits7-4 = 0000
  - Renders f(xop, 0)

Type 9 MAC squaring:
  - bits12-11 = 00, bit4 = 1, bits7-5 = 000
  - Renders f(xop^2)

Type 9 constant YOP:
  - CC=bits7-6, BO=bits5-4
  - Renders f(xop, const)

Tested with open21xx assembler output for 15 instructions.
Full regression: isa_test, fir, iir unchanged.
This commit is contained in:
Dr. Christian Giessen
2026-04-22 20:01:08 +00:00
parent dbcf04eb62
commit 1c28f027b8
3 changed files with 97 additions and 14 deletions
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30
examples/build/type9_test.dsp Normal file
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/*
* type9_test.dsp -- Test all Type 9/9a sub-encodings.
*/
.section/PM program0;
.global _start;
_start:
/* Type 9 standard: conditional ALU */
ar = ax0 + ay0;
if ne ar = ax0 - ay0;
ar = ax0 and ay0;
ar = pass ax0;
ar = -ax0;
ar = abs ax0;
/* Type 9 standard: conditional MAC */
mr = mx0 * my0 (ss);
if eq mr = mr + mx0 * my0 (ss);
mr = mr - mx0 * my0 (ss);
mr = 0;
/* Type 9a: unconditional register-file ALU */
ar = ax0 + ay1;
ar = mx0 xor my0;
/* Type 9a: unconditional register-file MAC */
mr = ax0 * ay0 (ss);
nop;
_halt:
jump _halt;