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Update all docs and test generator to match verified assembler opcodes

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- README.md: Complete project overview with plugin status
- ARCHITECTURE.md: Fixed register tables (CNTR in REG1, not REG2)
- GETTING_STARTED.md: r2-native workflow, removed Python disasm refs
- PRACTICAL_EXAMPLE.md: Uses verified open21xx opcodes with bit layouts
- ROM_ANALYSIS_WALKTHROUGH.md: Updated format detection and r2 commands
- r2plugin/README.md: Simplified, points to assembler test ROM
- gen_isa_test.py: All opcodes from open21xx assembler with labels
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# ADSP-219x Architecture Reference ⚙️
# ADSP-219x Architecture Reference
## Core Features
The ADSP-219x family consists of a 16-bit fixed-point DSP core with a 24-bit instruction word.
- **Harvard Architecture**: Separate Program Memory (PM) and Data Memory (DM) buses.
- **Instruction Width**: Exactly 24 bits. Padded often with a leading 0x00 or trailing zero byte if stored in 32-bit words, or packed as 3 bytes.
- **Memory Model**:
- PM Adressraum (24-bit Wörter): 16-bit to 24-bit depending on the model.
- DM Adressraum (16-bit Wörter): Up to 64K words.
The ADSP-219x family is a 16-bit fixed-point DSP core with a 24-bit
instruction word.
## Register Set 🗳️
- **Harvard Architecture**: Separate Program Memory (PM) and Data
Memory (DM) buses.
- **Instruction Width**: 24 bits (3 bytes). ROM dumps are typically
packed (3 bytes per word, big-endian) or padded (4 bytes with a
leading 0x00).
- **Memory Model**:
- PM: 24-bit words, up to 64K words (model-dependent).
- DM: 16-bit words, up to 64K words.
| Group | Registry | Purpose |
|-------|----------|---------|
| **REG0** | AX0, AX1, MX0, MX1, AY0, AY1, MY0, MY1, MR2, SR2, AR, SI, MR1, SR1, MR0, SR0 | ALU, Multiplier, MAC, and Shifter registers. |
| **REG1** | I0-I3, M0-M3, L0-L3, IMASK, IRPTL, ICNTL, STACKA | DAG1 (Data Address Generator) indices, modifies, lengths, and interrupt control. |
| **REG2** | I4-I7, M4-M7, L4-L7, Reserved, CNTR, LPSTACKA | DAG2 indices, modifies, lengths, and hardware loop structures. |
| **REG3** | ASTAT, MSTAT, SSTAT, LPSTACKP, CCODE, SE, SB, PX, DMPG1, DMPG2, IOPG, IJPG, Reserved, STACKP | Status registers, page registers, and control stacks. |
## Register Set
| Group | Registers (index 0-15) | Purpose |
|----------|------------------------------------------------------------------------------------------|--------------------------------------------------|
| **REG0** | AX0, AX1, MX0, MX1, AY0, AY1, MY0, MY1, MR2, SR2, AR, SI, MR1, SR1, MR0, SR0 | ALU, Multiplier, Shifter operand/result registers |
| **REG1** | I0, I1, I2, I3, M0, M1, M2, M3, L0, L1, L2, L3, IMASK, IRPTL, ICNTL, CNTR | DAG1 + interrupt control + counter |
| **REG2** | I4, I5, I6, I7, M4, M5, M6, M7, L4, L5, L6, L7, STACKA, LPCSTACKA, (reserved x2) | DAG2 + stack/loop registers |
| **REG3** | ASTAT, MSTAT, SSTAT, LPSTACKP, CCODE, SE, SB, PX, DMPG1, DMPG2, IOPG, IJPG, (res x3), STACKP | Status, page, and control registers |
## Arithmetic Elements
- **ALU**: 16-bit with overflow and saturation logic.
- **Multiplier/MAC**: 16x16 → 40-bit accumulation (MR).
- **Barrel Shifter**: 32-bit with 16-bit input and bit-manipulation capabilities.
## Instruction Types 🕹️
There are ~37 distinct instruction types, distinguished by their MSB encoding.
- **ALU**: 16-bit, supports add/subtract/logic/pass/abs with
carry, overflow, and saturation.
- **Multiplier/MAC**: 16x16 -> 40-bit accumulator (MR0/MR1/MR2).
Signed/unsigned modes (SS, SU, US, UU) plus rounding.
- **Barrel Shifter**: 32-bit shift register (SR0/SR1), supports
logical/arithmetic shift, normalize, and exponent detect.
- **Type 1**: Compute + Dual Memory Read (Multifunction).
- **Type 3**: Direct Register Read/Write.
- **Type 4**: Compute + Single Memory Read/Write.
- **Type 6/7**: Load Immediate 16-bit to Register.
- **Type 10/10a/19/36**: Jumps and Calls (Relative/Indirect/Long).
- **Type 15/16**: Shifter operations.
## Instruction Encoding (Top-Level Dispatch)
Instructions are decoded by their most-significant bits:
| Bits 23-22 | Bits 21-20 | Type(s) |
|------------|------------|-----------------------------------|
| 11 | xx | Type 1: Compute + DM + PM (multifunction) |
| 10 | xx | Type 3/3a: Direct memory access |
| 01 | 00 | Type 6: Dreg = Imm16 (REG0) |
| 01 | 01 | Type 7: Reg = Imm16 (REG1) |
| 01 | 10 | Type 11/33/34/35 (DO, IO, REG3) |
| 01 | 11 | Type 4: Compute + DM/PM postmodify |
| 00 | 11 | Type 7: Reg = Imm16 (REG2) |
| 00 | 10 | Type 9/9a: Compute (standalone) |
| 00 | 01 | Type 10/10a: Jump/Call |
| 00 | 00 | Type 15/17/18/20/25/30/31 (misc) |
## Boot and ROM Format
The ADSP-2191 boots from external memory (SPI flash, host, etc.).
A raw ROM dump contains packed 24-bit instructions in big-endian
byte order. Boot-stream images may include block headers:
[Target Addr] [Byte Count] [Flags] [Data...]
The reset vector is at PM address 0x0000.