diff --git a/analysis/analyze_rom.py b/analysis/analyze_rom.py new file mode 100644 index 0000000..d09dc7a --- /dev/null +++ b/analysis/analyze_rom.py @@ -0,0 +1,45 @@ +import r2pipe +import json +import sys + +# Load local disasm from disassembler dir +sys.path.append("../disassembler") +from adsp219x_disasm import decode_24 + +def analyze_rom(filename): + """ + Automated ROM analysis using radare2 + Python disassembler. + """ + r2 = r2pipe.open(filename) + r2.cmd("e asm.arch = adsp219x") # Custom arch handled by our script logic + r2.cmd("aa") # Basic analysis (will fail but good practice) + + # Iterate over file bytes + file_info = json.loads(r2.cmd("iX")) + size = file_info[0]["size"] + + print(f"Analyzing {filename} ({size} bytes)...") + + # 3-byte step for ADSP-219x + for offset in range(0, size, 3): + # Read 3 bytes + chunk = r2.cmdj(f"pxj 3 @ {offset}") + if not chunk or len(chunk) < 3: break + + opcode = (chunk[0] << 16) | (chunk[1] << 8) | chunk[2] + disasm = decode_24(opcode) + + # Set flags, comments, etc., back into r2 + r2.cmd(f"CC {disasm} @ {offset}") + print(f"0x{offset:04X}: {disasm}") + + # Output comment report + print("\nAnalysis Summary:\n") + print(r2.cmd("CC")) + r2.quit() + +if __name__ == "__main__": + if len(sys.argv) < 2: + print("Usage: analyze_rom.py ") + else: + analyze_rom(sys.argv[1]) diff --git a/disassembler/adsp219x_disasm.py b/disassembler/adsp219x_disasm.py new file mode 100644 index 0000000..74760d2 --- /dev/null +++ b/disassembler/adsp219x_disasm.py @@ -0,0 +1,147 @@ +import sys + +# AMF (ALU/Multiplier Function) codes (5 bits, 0-31) +AMF_ALU = { + 0x10: "Y", 0x11: "Y+1", 0x12: "X+Y+C", 0x13: "X+Y", + 0x14: "NOT Y", 0x15: "-Y", 0x16: "X-Y+C-1", 0x17: "X-Y", + 0x18: "Y-1", 0x19: "Y-X", 0x1a: "Y-X+C-1", 0x1b: "NOT X", + 0x1c: "X AND Y", 0x1d: "X OR Y", 0x1e: "X XOR Y", 0x1f: "ABS X" +} +AMF_MAC = { + 0x00: "NOP", 0x01: "X * Y (RND)", 0x02: "MR + X * Y (RND)", + 0x03: "MR - X * Y (RND)", 0x04: "X * Y (SS)", 0x05: "X * Y (SU)", + 0x06: "X * Y (US)", 0x07: "X * Y (UU)", 0x08: "MR + X * Y (SS)", + 0x09: "MR + X * Y (SU)", 0x0a: "MR + X * Y (US)", 0x0b: "MR + X * Y (UU)", + 0x0c: "MR - X * Y (SS)", 0x0d: "MR - X * Y (SU)", 0x0e: "MR - X * Y (US)", + 0x0f: "MR - X * Y (UU)" +} + +# Registers (RGP, Address) +REG_MAP = { + (0,0): "AX0", (0,1): "AX1", (0,2): "MX0", (0,3): "MX1", + (0,4): "AY0", (0,5): "AY1", (0,6): "MY0", (0,7): "MY1", + (0,8): "MR2", (0,9): "SR2", (0,10): "AR", (0,11): "SI", + (0,12): "MR1", (0,13): "SR1", (0,14): "MR0", (0,15): "SR0", + (1,0): "I0", (1,1): "I1", (1,2): "I2", (1,3): "I3", + (1,4): "M0", (1,5): "M1", (1,6): "M2", (1,7): "M3", + (1,8): "L0", (1,9): "L1", (1,10): "L2", (1,11): "L3", + (1,12): "IMASK", (1,13): "IRPTL", (1,14): "ICNTL", (1,15): "STACKA", + (2,0): "I4", (2,1): "I5", (2,2): "I6", (2,3): "I7", + (2,4): "M4", (2,5): "M5", (2,6): "M6", (2,7): "M7", + (2,8): "L4", (2,9): "L5", (2,10): "L6", (2,11): "L7", + (2,12): "RSVD", (2,13): "CNTR", (2,14): "LPSTACKA", (2,15): "RSVD", + (3,0): "ASTAT", (3,1): "MSTAT", (3,2): "SSTAT", (3,3): "LPSTACKP", + (3,4): "CCODE", (3,5): "SE", (3,6): "SB", (3,7): "PX", + (3,8): "DMPG1", (3,9): "DMPG2", (3,10): "IOPG", (3,11): "IJPG", + (3,15): "STACKP" +} + +# Condition Codes +COND_CODES = { + 0x0: "EQ", 0x1: "NE", 0x2: "GT", 0x3: "LE", 0x4: "LT", 0x5: "GE", + 0x6: "AV", 0x7: "NOT AV", 0x8: "AC", 0x9: "NOT AC", 0xA: "SWCOND", + 0xB: "NOT SWCOND", 0xC: "MV", 0xD: "NOT MV", 0xE: "NOT CE", 0xF: "TRUE" +} + +# XOP/YOP Code for ALU/MAC +XOP_ALU = ["AX0", "AX1", "AR", "MR0", "MR1", "MR2", "SR0", "SR1"] +YOP_ALU = ["AY0", "AY1", "AF", "0"] # 11 = 0 +XOP_MAC = ["MX0", "MX1", "AR", "MR0", "MR1", "MR2", "SR0", "SR1"] +YOP_MAC = ["MY0", "MY1", "SR1", "0"] + +def get_reg_name(rgp, addr): + return REG_MAP.get((rgp, addr), f"REG({rgp},{addr})") + +def decode_24(opcode): + """ + Decodes a 24-bit ADSP-219x instruction into its assembly string. + """ + # Type 1: 11xxxxxx (Compute | DregX←DM | DregY←PM) + if (opcode >> 22) == 0b11: + pd = (opcode >> 20) & 0x3 + dd = (opcode >> 18) & 0x3 + amf = (opcode >> 13) & 0x1F + yop = (opcode >> 11) & 0x3 + xop = (opcode >> 8) & 0x7 + pmi = (opcode >> 6) & 0x3 + pmm = (opcode >> 4) & 0x3 + dmi = (opcode >> 2) & 0x3 + dmm = opcode & 0x3 + + # Check for NOP multifunction (All AMF bits zero) + if amf == 0: + comp_str = "NOP" + elif amf >= 0x10: + comp_str = f"{AMF_ALU[amf]}({XOP_ALU[xop]}, {YOP_ALU[yop]})" + else: + comp_str = f"{AMF_MAC[amf]}({XOP_MAC[xop]}, {YOP_MAC[yop]})" + + return f"{comp_str}, {XOP_ALU[dd]} = DM(I{dmi} += M{dmm}), {YOP_ALU[pd]} = PM(I{pmi+4} += M{pmm+4})" + + # Type 3: Register read/write to immediate 16-bit address + # Type 3 (Ireg/Mreg): 101 D addr16 IREG/MREG + if (opcode >> 21) == 0b101: + d = (opcode >> 20) & 0x1 + addr = (opcode >> 4) & 0xFFFF + reg_code = opcode & 0xF + reg_rgp = 1 if reg_code < 8 else 1 # Simple I/M mapping for type 3 + # In reality, Type 3 Ireg/Mreg uses a specific table. 0-7 are I0-I7, 8-15 are M0-M7. + reg_name = f"I{reg_code}" if reg_code < 8 else f"M{reg_code-8}" + if d: return f"DM(0x{addr:04X}) = {reg_name}" + else: return f"{reg_name} = DM(0x{addr:04X})" + + # Type 6: 0100 Dreg Data16 (Dreg = Data16) + if (opcode >> 20) == 0b0100: + data = (opcode >> 4) & 0xFFFF + dreg = opcode & 0xF + reg_name = get_reg_name(0, dreg) + return f"{reg_name} = 0x{data:04X}" + + # Type 10: 000110B addr13 COND (Jump relative) + if (opcode >> 19) == 0b00011: + type_bits = (opcode >> 17) & 0x7 + if type_bits == 0b110: # Type 10: 00011 0 delayed(B) ... + b = (opcode >> 16) & 0x1 + addr = (opcode >> 4) & 0x1FFF + cond = opcode & 0xF + db = " (DB)" if b else "" + cond_str = f"IF {COND_CODES[cond]} " if cond != 0xF else "" + return f"{cond_str}JUMP 0x{addr:04X}{db}" + elif type_bits == 0b100: # Type 12: Shift | Dreg ... + pass # TODO + + # Type 30: 00000000 (NOP) + if (opcode >> 12) == 0: + return "NOP" + + return f"UNKNOWN (0x{opcode:06X})" + +def main(): + if len(sys.argv) < 2: + print("Usage: adsp219x_disasm.py [3|4 (packed|padded)]") + return + + filename = sys.argv[1] + format = int(sys.argv[2]) if len(sys.argv) > 2 else 3 # Default 3-byte packed + + with open(filename, "rb") as f: + data = f.read() + + step = format + for i in range(0, len(data), step): + chunk = data[i:i+step] + if len(chunk) < 3: break + + if format == 3: + # Packed: B0 B1 B2 + opcode = (chunk[0] << 16) | (chunk[1] << 8) | chunk[2] + else: + # Padded 32-bit (assume leading zero or big-endian dump): 0x00 B0 B1 B2 + # or check your dump! + opcode = (chunk[1] << 16) | (chunk[2] << 8) | chunk[3] + + addr = i // format + print(f"0x{addr:04X}: 0x{opcode:06X} {decode_24(opcode)}") + +if __name__ == "__main__": + main() diff --git a/docs/9x_ALUops.pdf b/docs/9x_ALUops.pdf new file mode 100644 index 0000000..35b139f Binary files /dev/null and b/docs/9x_ALUops.pdf differ diff --git a/docs/9x_flowops.pdf b/docs/9x_flowops.pdf new file mode 100644 index 0000000..9a1216d Binary files /dev/null and b/docs/9x_flowops.pdf differ diff --git a/docs/9x_flowops.txt b/docs/9x_flowops.txt new file mode 100644 index 0000000..c8c648a --- /dev/null +++ b/docs/9x_flowops.txt @@ -0,0 +1,2865 @@ +8 PROGRAM FLOW + INSTRUCTIONS + Figure 8-0. + Table 8-0. + Listing 8-0. + + The instruction set provides program flow instructions for controlling the + sequence in which the DSP executes instructions. Generally, the instruc- + tions in a program execute sequentially, one after another, unless + otherwise directed by various program structures—branches, loops, sub- + routines, or interrupts—that intervene and temporarily or permanently + redirect this linear flow. These program structures enable an application to + respond to events or conditions as they occur. Program flow control + instructions include: + • “DO UNTIL (PC relative)” on page 8-22 + • “Direct JUMP (PC relative)” on page 8-27 + • “CALL (PC relative)” on page 8-30 + • “JUMP (PC relative)” on page 8-34 + • “Long CALL” on page 8-37 + • “Long JUMP” on page 8-40 + • “Indirect CALL” on page 8-42 + • “Indirect JUMP” on page 8-45 + • “Return from Interrupt” on page 8-48 + • “Return from Subroutine” on page 8-52 + • “PUSH or POP Stacks” on page 8-55 + • “PUSH or POP Stacks” on page 8-55 + + + + ADSP-219x Instruction Set Reference 8-1 + Program Flow Instructions + + + + + • “FLUSH CACHE” on page 8-61 + • “Set Interrupt” on page 8-62 + • “Clear Interrupt” on page 8-64 + • “No Operation” on page 8-66 + • “Idle” on page 8-67 + • “Mode Control” on page 8-69 + This chapter describes each of the move instructions and the following + related topics: + • “Conditions” on page 8-2 + • “Counter-Based Conditions” on page 8-3 + • “CCODE Register” on page 8-4 + • “MSTAT Mode Control Register” on page 8-4 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + • “Stacks” on page 8-7 + • “Stack Status Flags” on page 8-12 + • “Interrupts” on page 8-13 + • “Application Performance” on page 8-17 + +Conditions + Table 2-8 on page 2-15 lists the conditions used in conditional (IF COND) + instructions and their opcodes. Besides these conditions (which mainly + relate to the status of the ALU, multiplier, and counter) it is possible to + + + +8-2 ADSP-219x Instruction Set Reference + Counter-Based Conditions + + + + + use the SWCOND condition and the value in the CCODE register to test for + other DSP status conditions. For more information, see “Condition Code + (CCODE) Register” on page 2-6. Also, you can test for bit states to gener- + ate conditions using the TSTBIT instruction. For more information, see + “Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT” on page + 3-18., + +Counter-Based Conditions + Both IF Condition (conditional) instructions and the DO UNTIL (loop) + instructions can base execution on the NOT CE condition. Although the DO + UNTIL instruction uses the CE syntax only, the condition actually tested is + NOT CE—counter not expired. + + To use a counter condition with either instruction type, you must load the + CNTR register with an initial counter value (>1) before issuing the instruc- + tion that uses the counter condition. + There are some important differences between how conditional and loop + instructions implement (decrement and test) the counter condition: + • To implement the NOT CE condition in an IF Condition (condi- + tional) instruction, the DSP decrements and tests the value loaded + in the CNTR register before executing the conditional instruction. For + a conditional instruction based on NOT CE, the DSP tests whether the + CNTR register contains a value >1. + + • To implement the CE condition in a DO UNTIL (loop) instruction, the + DSP loads the loop counter stack from the CNTR register at the start + of the loop, then decrements and tests the counter value in the loop + counter stack (not the CNTR register) at the end of each pass through + the loop. For a loop instruction based on CE, the DSP tests whether + the loop counter stack’s counter value >0. For more information, + see “Loop Stacks Operation” on page 8-10. + + + + + ADSP-219x Instruction Set Reference 8-3 + Program Flow Instructions + + + + +CCODE Register + Table 2-3 on page 2-7 lists the CCODE register values used to test the + SWCOND and NOT SWCOND software conditions. Although the source each + value tests is specific to each DSP in the ADSP-219x family, these values + (except 0x08 and 0x09) map to the software interrupt bits in the IMASK + and IRPTL registers. + To test for any software condition, first load the CCODE register with the + value of the source you want to test, then test for the true or false state. + For example, 0x08 represents ALU saturation status, you might code this + sequence: + CCODE = 0x08; /* ALU Saturated (AR_SAT) cond */ + AR = AX0 + AY1; + IF SWCOND JUMP fix_data; /* Jump to fix_data if AR_SAT */ + + fix_data: + NOP; /* code to fix data ALU_SAT */ + + Or, to test for a shifter overflowed result: + CCODE = 0x09; /* Shifter Overflowed (SV) cond */ + AR = 3; SE = AR; /* shift code, left shift 3 bits */ + SI = 0xB6A3; /* value of hi word of input data */ + IF NOT SWCOND SR = ASHIFT SI (HI); /* ashift high word if SV */ + + A value written to CCODE isn’t available on the next cycle, so you must + insert at least one instruction between the write to CCODE and the condi- + tional instruction that tests the software condition. Otherwise, the + conditional instruction will test the previous value of CCODE. + +MSTAT Mode Control Register + As shown in Table 2-6 on page 2-11, bits 0 through 7 of the MSTAT register + control various DSP modes. These modes determine some conditions for + how status flags are set. + + + + +8-4 ADSP-219x Instruction Set Reference + Branch Options + + + + +Branch Options + All of the DSP’s branch instructions (except DO UNTIL and LJUMP/LCALL), + support two branch options: immediate and delayed. These options deter- + mine whether the DSP executes the first two instructions directly + following the branch instruction before it executes the instruction at the + branch target address. Because of the instruction pipeline, a number of + latency cycles (usually four) occur between execution of the branch + instruction and execution of the branch target instruction. + By default, the branch instructions perform an immediate branch, which + means that the next instruction the DSP executes after the branch instruc- + tion is the instruction at the branch target address, but only after a + number of NOP cycles. Using the delayed option, you can salvage two of + the NOP cycles and perform useful work. To do so, you include the (DB) + option in the branch instruction and code in the two delay slots directly + following the branch instruction the two instructions that you want exe- + cuted before the branch target instruction. + + ! You cannot insert or + JUMP instructions in delay branch slots. + CALL + You can insert only one two-word instruction, and it must occupy + the first delay branch slot. + When the DSP executes an RTI or RTS instruction to return to the main + program, it returns to execute the first or third instruction after the + branch instruction, depending on whether the branch is immediate or + delayed. + Return from immediate branch: + IF AV CALL immediate_pump; /* immed branches may be cond */ + NOP; /* RTS returns program flow here */ + NOP; + + immediate_pump: + NOP; + RTS; + + + + + ADSP-219x Instruction Set Reference 8-5 + Program Flow Instructions + + + + + Return from delayed branch: + CALL delayed_pump (DB); /* delayed branches must be uncond */ + NOP; /* 1st_delay_instruction */ + NOP; /* 2nd_delay_instruction */ + NOP; /* RTS returns program flow here */ + NOP; + + delayed_pump: + NOP; + RTS; + + +Addressing Branch Targets + When you issue a JUMP or CALL instruction, you specify the address of the + instruction to branch to in one of three ways: + • PC relative + Offset from the current PC. The immediate value you specify in the + instruction is added to the PC of the branch instruction to form the + address of the branch target location. For example, the CALL in the + following code goes to PC-relative address (find_me): + .EXTERN find_me; /* matches .global in other file */ + CALL find_me (DB); + NOP; + + • Far absolute + The full 24-bit address of the branch target location is specified in + the instruction. You can program this instruction explicitly in an + LJUMP/ LCALL instruction. The assembler automatically substitutes + this instruction when the actual address assembled from a PC rela- + tive address is insufficient. + + + + +8-6 ADSP-219x Instruction Set Reference + Stacks + + + + + • Indirect + The address of the branch target location is specified using a DAG + index register (I0−I7) and the IJPG page register. For example, the + CALL in the following code goes to an address using the indirect + address from the I0 register: + .EXTERN find_me_too; /* matches .global in other file */ + IJPG = 0x0; /* set memory page for CALL */ + I0 = find_me_too; /* loads I0 with address */ + NOP; + NOP; + CALL (I0) (DB); + NOP; + + +Stacks + Loops and other branch instructions use the DSP’s stacks to implement + their respective operations. + • PC stack (33 words × 24 bits) + Holds the address of the next instruction to execute on return from + a called subroutine. Only the CALL, RTI, RTS, and PUSH/POP PC + instructions use this stack. + • Loop begin stack (8 words × 24 bits) + Holds the address of the first instruction in a loop. Only the DO UNTL + and PUSH/POP LOOP instructions use this stack. + • Loop end stack (8 words × 24 bits) + Holds the address of the last instruction in a loop. Only the DO UNTL + and PUSH/POP LOOP instructions use this stack. + • Loop counter stack (8 words × 16 bits) + Holds the current value of the loop counter that is loaded from the + CNTR register. This value—not the value in the CNTR register—is + + + + + ADSP-219x Instruction Set Reference 8-7 + Program Flow Instructions + + + + + tested and decremented at the end of each pass through the loop. + Only the DO UNTL and PUSH/POP LOOP instructions use this stack. + • Status stack (16 words × 32 bits) + Holds the current value of the ASTAT and MSTAT registers. Only RTI + and PUSH/POP STS instructions use this stack. (When globally + enabled and unmasked interrupts occur, the DSP automatically + saves the two status registers to this stack.) + +PC and Status Stack Operation + Applications use these stacks to implement function calls and interrupt + service routines (ISRs). + Function Calls. When a CALL instruction executes, it automatically pushes + onto the PC stack the address of the next instruction to execute upon + returning from the subroutine. The CALL instruction does not push the + status registers onto the status stack. + The RTS instruction, executed at the end of the subroutine, returns pro- + gram execution to either the first or third instruction following the CALL + instruction, depending on whether the CALL was immediate or delayed, + respectively. + + + + +8-8 ADSP-219x Instruction Set Reference + Stacks + + + + +ISRs. When interrupts are globally enabled and an unmasked interrupt +occurs, it cause the DSP to automatically save its current state before +entering the interrupt’s ISR. To do so, the DSP: + • Pushes onto the PC stack the address of the next instruction to exe- + cute upon returning from the ISR. + If the interrupt is higher than the core’s current level of operation, + the DSP pushes the address of the current instruction onto the PC + stack and branches immediately to the interrupt’s ISR. + If the interrupt is lower than the core’s current level of operation, + the DSP finishes the current operation, pushes the address of the + next sequential instruction onto the PC stack, and then branches to + the interrupt’s ISR. + • Pushes onto the status stack, in order, the ASTAT and MSTAT registers. +The RTI instruction, executed at the end of the ISR, pops the PC stack +returning program execution to the instruction at the retrieved address. It +also pops the status stack, restoring the ASTAT and MSTAT registers to their +previous values. So, if the ISR enables any of the MSTAT mode bits, the RTI +operation automatically disables them. +PUSH/POP PC/STS. You can explicitly push and pop the PC and status +stacks as needed. The DSP automatically performs these operations when +using nested interrupts. +Pushing (PUSH STS) and popping (POP STS) the status stack automatically +saves or restores the ASTAT and MSTAT registers. But, pushing (PUSH PC) and +popping (POP PC) the PC stack requires a few more steps that involve the +STACKA and STACKP registers. + +For PUSH/POP PC operations, the 16-bit STACKA register supplies or receives, +respectively, the sixteen LSBs of an instruction’s 24-bit address, and the +8-bit STACKP register supplies or receives the eight MSBs. So, before you + + + + + ADSP-219x Instruction Set Reference 8-9 + Program Flow Instructions + + + + + issue a PUSH PC instruction, you must load the STACKA and STACKP registers + with the appropriate values: + STACKA = 0x3521; + STACKP = 0x02; + PUSH PC; + + Likewise, after you pop the PC stack, you can check the contents of the + STACKA and STACKP registers: + + POP PC; + AX0 = STACKA; + AY0 = STACKP; + + + " Abut a or or + PUSH + PUSH + POP PC has one cycle of latency for all SSTAT register bits, + POP LOOP or STS has one cycle of latency only for the + STKOVERFLOW bit in the SSTAT register. + + +Loop Stacks Operation + Applications use this stack to implement loop operations. + When a DO UNTIL instruction executes, it automatically pushes data onto + the three loop stacks: + • Loop begin stack Receives the loop start address (current PC). + • Loop end stack Receives the loop end address. + • Counter stack Receives the counter value from the CNTR register + for finite loops. If the loop is infinite, the + counter stack still receives the counter value; the + DSP decrements this value on the stack, but + ignores the result. + Finite Loops (DO UNTIL CE). The CE terminator specifies a finite + loop. To accommodate the write effect latency, you must load the CNTR + register with the number of iterations to execute the loop at least two + instructions before the DO UNTIL instruction. When the DO UNTIL instruc- + + + +8-10 ADSP-219x Instruction Set Reference + Stacks + + + + +tion executes, it automatically pushes the CNTR value onto the counter +stack. (The CNTR register retains the original value, until explicitly changed +with a data move or POP LOOP instruction.) +The loop mechanism decrements and tests the value at the top of the +counter stack at the end of each pass through the loop. The loop ends +when the counter expires (decrements to 1). At loop end, program execu- +tion automatically continues with the instruction directly following the +end of the loop. +Infinite Loops (DO [UNTIL FOREVER]). To end an infinite loop, the +loop must contain an explicit JUMP to an instruction outside the loop to +exit and end it. The JUMP is based on a condition created inside the loop +and typically branches to a POP LOOP instruction to recover the loop +stacks—the goal is to adjust the loop stack pointers, not retrieve the loop +start and end addresses. After that, another JUMP instruction returns pro- +gram execution to the next sequential instruction following the loop’s end. +PUSH/POP LOOP. You can explicitly push and pop the loop stacks. +These operations are necessary to recover and maintain the loop stacks +when you abort a loop. +PUSH/POP LOOP instructions operate on all three loop stacks in parallel. +Both operations involve the STACKA, STACKP, LPSTACKA, LPSTACKP, and +CNTR registers. Before you issue a PUSH LOOP instruction, you must load the +STACKA, STACKP, LPSTACKA, and LPSTACKP registers with appropriate values. + + • The 16-bit STACKA and 8-bit STACKP register supply or receive the + loop start address from the loop begin stack. + STACKA holds the sixteen LSBs of the 24-bit, loop start address, and + STACKP holds the eight MSBs. + + + + + ADSP-219x Instruction Set Reference 8-11 + Program Flow Instructions + + + + + • The 16-bit LPSTACKA and 16-bit LPSTACKP register supply or receive + the loop end address from the loop end stack. (Only bit 15 and bits + 7:0 of LPSTACKP are valid—bits 14:8 should always be zero.) + LPSTACKA holds the sixteen LSBs of the 24-bit, loop end address, and + LPSTACKP holds the eight MSBs in bits 7:0 and the loop terminator + condition, CE or FOREVER, in bit 15. When the FOREVER bit is set, the + loop logic ignores the loop counter value. + • The 16-bit CNTR register supplies or receives the counter value from + the counter stack. + On a pop, the CNTR register receives whatever value is at the top of + the counter stack. For finite loops, since the value in the counter + stack is decremented at the end of each pass through the loop, a POP + loads CNTR with a new value, overwriting the original count value, + unless the POP occurs before the first pass through the loop. + For infinite loops, the PUSH LOOP instruction pushes the current + value of the CNTR register onto the loop counter stack. This value is + irrelevant but pushing it maintains the pointer’s correct position in + the loop counter stack. + + " Abut a or or + PUSH + PUSH + POP PC has one cycle of latency for all SSTAT register bits, + POP LOOP or STS has one cycle of latency only for the + STKOVERFLOW bit in the SSTAT register. + + +Stack Status Flags + As shown in Table 2-7 on page 2-14, bits 0 through 7 of the SSTAT register + record the status of the DSP’s stacks. This status information is useful for + managing the stack and servicing stack interrupts. + The stack interrupt is always generated by a stack overflow condition, but + can also be generated by ORing together the stack overflow status (STK- + + + + +8-12 ADSP-219x Instruction Set Reference + Interrupts + + + + + OVERFLOW) bit and stack high/low level status ( PCSTKLVL) bit. The level bit + is set when: + • The PC stack is pushed and the resulting level is at the high water + mark. + • The PC stack is popped and the resulting level is at the low water- + mark. + This spill-fill mode (using the stack to generate a stack interrupt) is dis- + abled on reset. Two bits in the ICNTL register (bit 10 —PC Stack + Interrupt Enable) can be used to enable interrupts for the three corre- + sponding stacks. + + " When switching on spill-fill mode, a spurious low water mark inter- + rupt may occur (depending on the level of the stack). In this case, + the interrupt handler should push some values on the stack to raise + the level above the low watermark level. + +Interrupts + The DSP uses interrupts to communicate with the outside world. The + DSP’s core generates internal interrupts, the peripherals generate external + interrupts, and software can generate software interrupts. + When an interrupt occurs, the DSP suspends its current operation, saving + the ASTAT and MSTAT registers, and jumps to the location in memory of the + interrupt’s service routine (ISR) and begins executing that program code. + When it has completed the interrupt’s ISR, an RTI instruction at the end + of the routine forces program flow to return to the suspended operation + and continue executing code at the location where it left off, after the DSP + restores the ASTAT and MSTAT registers. + Each interrupt has a priority rank and its own vector address. The inter- + rupt’s vector address specifies the location in memory of its service + routine. Its priority determines the order in which the interrupt gets ser- + + + + + ADSP-219x Instruction Set Reference 8-13 + Program Flow Instructions + + + + + viced relative to the other interrupts. An interrupt with higher priority + gets serviced before one with lower priority. As shown in Table 2-5 on + page 2-10, the lower the interrupt’s position in the IMASK/IRPTL register + the higher its priority. + To implement and use interrupts, your software must perform these tasks: + • Globally enable interrupts. + • Individually enable the particular interrupt. + • At the beginning of the ISR, switch context to secondary register + sets and perform the necessary tasks to handle the interrupt condi- + tion. For details, see “Switching Contexts” on page 8-16. + If your program requires nested interrupts, it might need to perform + a few extra tasks within each interrupt’s ISR. For details, see “Nest- + ing Interrupts” on page 8-16. + • At the end of the ISR, insert an RTI instruction to branch back (RTI) + to the suspended operation. The RTI instruction automatically + switches context back to the primary register sets. + • Continue executing program code at the return address. + +Enabling Interrupts + When an interrupt occurs, the DSP services it only when all interrupts are + globally enabled and the particular interrupt is individually enabled. Typ- + ically, you enable interrupts both globally and individually in your main + program and at the appropriate place wait for an interrupt to occur. + Global Interrupts. You can enable and disable interrupts globally using + these instructions: + ENA INT; /* Enable interrupts globally */ + DIS INT; /* Disable interrupts globally */ + + + + +8-14 ADSP-219x Instruction Set Reference + Interrupts + + + + +With interrupts globally disabled, the DSP does not recognize or latch any +interrupts that occur and so cannot service them. +Individual Interrupts. You can enable and disable interrupts individually +using the register load instruction (for details, see, “Direct Register Load” +on page 7-27). For example, to enable (unmask) interrupts 3, 5, 7, and 8, +you set them to 1: + IMASK = 0x01A8; /* Enable interrupts 8, 7, 5, & 3 only */ + +Interrupt 0 is nonmaskable in IMASK and cannot be enabled or disabled +globally. +With interrupts globally enabled and individual interrupts enabled in +IMASK, the DSP automatically services them when it detects their respec- +tive bits set in IRPTL. +With interrupts globally enabled and individual interrupts disabled in +IMASK, when they occur and are latched in IRPTL, you can choose to +unmask their respective bits in IRPTL and service them or to clear their bits +and reject them. For example: + ENA INT; /* globally enable ints */ + IMASK = 0x0000; /* individually disable all ints */ + NOP; + NOP; /* any number of instructions */ + NOP; + AX0 = IRPTL; /* load IRPTL into AX0 */ + AF = TSTBIT 8 OF AX0; /* test interrupt 8 */ + IF NE JUMP normal; /* If 0 continue normal flow */ + AR = CLRBIT 8 of AX0; /* else clear interrupt (bit 8) */ + IRPTL = AR; /* load IRPTL with new value */ + normal: + NOP; /* continue normal program flow */ + +IMASK is the interrupt mask register, and IRPTL is the interrupt latch regis- +ter. As shown in Table 2-5 on page 2-10, the IMASK and the IRPTL registers +match each other bit for bit. + + + + + ADSP-219x Instruction Set Reference 8-15 + Program Flow Instructions + + + + +Switching Contexts + The DSP has two sets of DAG address registers and two sets of data regis- + ters that enable you to quickly switch between the context of normal + processing and the context of interrupt processing as needed. The second- + ary register sets eliminate the need to save the state of the data and address + registers before processing an interrupt and reduces interrupt latency. (For + details on DSP modes, see “MSTAT Mode Control Register” on + page 8-4.) + Typically, you switch from primary to secondary registers at the beginning + of the interrupt’s ISR. To do so, you use the following instructions: + ENA SEC_REG; /* enable secondary data registers */ + ENA SEC_DAG; /* enable secondary DAG address registers */ + + You use the RTI instruction at the end of the routine to return program + flow to the main program. This instruction automatically switches context + back to the primary registers when it restores the ASTAT, MSTAT, and SSTAT + registers. So, for example, an interrupt service routine might look like this: + service_interrupt: + ENA SEC_REG, ENA SEC_DAG; /* enable secondary registers */ + NOP; + NOP; /* ISR code */ + NOP; + RTI; /* return from interrupt and */ + /* enable primary registers */ + + +Nesting Interrupts + Nested interrupts enable the DSP to respond to more than one interrupt + at a time. A higher priority interrupt suspends a lower priority interrupt’s + routine. After the higher priority interrupt’s RTI executes, the lower prior- + ity interrupt’s routine continues executing. + Without nested interrupts, only one interrupt at a time gets serviced, so + other interrupts remain pending until the RTI of the current routine exe- + cutes. Then the pending interrupt with highest priority gets serviced. + + + +8-16 ADSP-219x Instruction Set Reference + Application Performance + + + + + To use nested interrupts, you must enable them in the ICNTL register. To + do so, you explicitly set bit 4 of INCTL: + ICNTL = 0x0010; + + Once enabled, any interrupt with higher priority than the currently exe- + cuting ISR suspends that ISR’s execution. Table 2-4 on page 2-8 lists and + describes the bits of the ICNTL register. + The DSP supports up to sixteen nested interrupts, but has only one set of + secondary data and DAG address registers. So, if your application uses + deeply nested interrupts, you may need to manually save the state of the + data registers and DAG address registers to memory in your ISR routines. + To do so: + • Set up a segment in memory to save the current state of the data and + DAG address registers. + • In the ISR, save to memory the state of the data registers and the + state of the DAG address registers that you intend to use. + +Application Performance + The ADSP-219x’s instruction set provides many ways to optimize code to + accommodate particular applications. This section discusses optimization + strategies for these topics: + • Exiting a loop + • Using long jumps and calls + • Effect latencies + +Exiting a Loop + When you exit an infinite loop or abort a finite loop prematurely, the loop + hardware fixes and restores the loop stacks before the POP LOOP instruction + + + + ADSP-219x Instruction Set Reference 8-17 + Program Flow Instructions + + + + + executes. So, with few restrictions, you can branch out of a loop from + almost any location, regardless of the length of the loop. However, for + optimal performance, consider these scenarios: + • Jumps or calls nearby loop ends may add extra cycles of loop stack + clean-up when the jump or call is taken. + CNTR = 5; + MX0 = 0xFF; + MY0 = 0xFF; + DO mac_loop UNTIL CE; /* start of mac_loop */ + NOP; + NOP; + MR = MX0 * MY0 (SS); + IF MV JUMP abort_loop; + mac_loop: + NOP; /* end of mac_loop */ + NOP; /* 1st instr after mac_loop */ + NOP; /* 2nd instr after mac_loop */ + NOP; /* 3rd instr after mac_loop */ + abort_loop: /* loop exit routine */ + POP LOOP; + JUMP mac_loop + 1; + + The jump to abort_loop takes 1, 2, or 3 extra cycles, depending on + whether the first, second, and third instruction after the end of the + mac_loop are also loop ends, to clean up the loop stacks before the + POP LOOP instruction executes. Impact on performance is minimal if + the POP occurs only once. + • Jumps or calls nearby loop ends add 1, 2, or 3 extra cycles each time + the branch is taken. + CNTR = 5; + DO little_loop UNTIL CE; + NOP; /* 1st instr. of little_loop */ + NOP; /* 2nd instr. of little_loop */ + NOP; /* 3rd instr. of little_loop */ + IF MV CALL fix_my_data; + little_loop: + NOP; /* end of little_loop */ + NOP; /* 1st instr. after little_loop */ + + + + +8-18 ADSP-219x Instruction Set Reference + Application Performance + + + + + NOP; /* 2nd instr. after little_loop */ + NOP; /* 3rd instr. after little_loop */ + NOP; /* 4th instr. after little_loop */ + + fix_my_data: + NOP; + NOP; + RTS; + + The call to fix takes 1, 2, or 3 extra cycles, depending on whether + the first, second, and third instructions after the end of little_loop + are also loop ends, to clean up the loop stacks. To avoid the degra- + dation in performance this construct incurs, you could move the + CALL instruction further up in the loop or insert the called subrou- + tine in the loop. +• Because the loop begin stack and PC stack are separate and distinct, + this loop construct causes a loop to fall gracefully through the next + loop end. + CNTR = 5; + DO bigger_loop UNTIL CE; + NOP; /* 1st instr. of bigger_loop */ + NOP; /* 2nd instr. of bigger_loop */ + NOP; /* 3rd instr. of bigger_loop */ + IF MV CALL fix_bigger_data; + NOP; + NOP; + bigger_loop: + NOP; /* end of bigger_loop */ + NOP; /* 1st instr. after bigger_loop */ + NOP; /* 2nd instr. after bigger_loop */ + NOP; /* 3rd instr. after bigger_loop */ + + fix_bigger_data: + NOP; + NOP; + RTS; + + The call to fix_bigger_data takes no extra cycles, unless the loop is + aborted. One abort routine can serve all loops in nearby code space + + + + + ADSP-219x Instruction Set Reference 8-19 + Program Flow Instructions + + + + + since the routine is identical for each. Even after the loop is aborted, + the end of the bigger_loop still executes, and the loop falls grace- + fully out. + +Using Long Jumps and Calls + The instruction set provides several jump/call instructions that support + different address ranges for addressing branch targets: + • -4096 to +4095 “Direct JUMP (PC relative)” on page 8-27 + • -32768 to +32767 “CALL (PC relative)” on page 8-30 + • -32768 to +32767 “JUMP (PC relative)” on page 8-34 + • -16777216 to +16777215“Long CALL” on page 8-37 + • -16777216 to +16777215“Long JUMP” on page 8-40 + Usually, programmers must determine in advance the offset of the target + from the branch and use the appropriate branch instruction, making sure + the address of the branch target falls within the address range of the + branch instruction. + However, using an option provided in the assembler and in the linker with + any of the PC relative branch instructions, you can let the tools determine + and select which branch instruction to use based on the actual address of + the branch target. To do so, you encode PC relative branch instructions + and use the assembler’s and linker’s -jcs21 option, which directs the tools + to substitute, during linking, LJUMP or LCALL for any particular PC relative + branch instruction as appropriate. For details, see the Assembler Manual + for ADSP-219x Family DSPs and the Linker & Utilities Manual for + ADSP-219x Family DSPs. + When using the linker’s -jcs21 option, you need to understand how it + alters the linker’s operation, so you can fine tune your code accordingly. + + + + +8-20 ADSP-219x Instruction Set Reference + Application Performance + + + + + When the linker substitutes LJUMP or LCALL for a corresponding PC rela- + tive branch instruction: + • It substitutes an absolute address for the PC relative address. + • If it encounters the (DB) option in a PC relative instruction, it moves + the 48 bits (either two one-word instructions or one two-word + instruction) from the two delay slots following the PC relative + instruction and inserts them directly in front of the LCALL or LJUMP + instruction. + For conditional PC relative instructions, this procedure could + change the condition code upon which the branch instruction is + predicated. To avoid this potential bug, base (DB) branch instruc- + tions on negated conditions (IF NOT COND), not positive ones (IF + COND). + + • For unconditional PC relative instructions, it always encodes the + TRUE condition. + + +Effect Latencies + An effect latency occurs when some instructions write or load a value into + a register, which changes the value of one or more bits in the register. + Effect latency refers to the time it takes after the write or load instruction + for the effect of the new value to become available for other instructions to + use. For more information, see “Register Load Latencies” on page 7-9. + + + + + ADSP-219x Instruction Set Reference 8-21 + Program Flow Instructions + + + + +DO UNTIL (PC relative) + + DO [UNTIL ] ; + + +FUNCTION + + Sets up the looping circuitry for zero-overhead looping. The DO UNTIL + instruction uses the current PC (Program Counter) as the basis for deter- + mining the beginning of the loop and the PC-relative 12-bit offset value + (Imm12) as the end of a loop. +INPUT + + Imm12 12-bit, positive offset value added to the address (PC) of the DO + UNTIL instruction. Valid values range from 1 to 4095. (For good + programming practice, use declared labels.) + Term Loop terminator. Valid loop termination conditions are FOREVER + and CE. +OUTPUT + + None. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +LPSTKEMPTY (always cleared), LPSTKFULL, PCSTKEMPTY, PCSTKFULL, PCSTKLVL, +STKOVERFLOW STSSTKEMPTY + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + + + +8-22 ADSP-219x Instruction Set Reference + DO UNTIL (PC relative) + + + + +DETAILS + + The loop begins at the instruction directly following the DO UNTIL instruc- + tion (PC + 1) and ends at the instruction located at the offset address + specified in the DO UNTIL instruction—(PC + ). + When using the FOREVER (infinite loop) termination condition, you must + explicitly exit the loop by generating a status condition on which to base a + jump to a location outside the loop. If you omit a terminator (DO ), + the instruction defaults to FOREVER. + When using the CE (counter expired) termination condition, before enter- + ing the loop, you must load the CNTR register with the number of times to + execute the loop. Each pass through the loop decrements and tests the + counter value in the loop counter stack, not the CNTR register (for details, + see “Loop Stacks Operation” on page 8-10). When the counter expires, + looping terminates. + + " Ifter.using termination, you must load a value >1 in the + CE CNTR regis- + + + + Finite loops ( CE terminator) execute repeatedly until the loop terminator + occurs. Infinite loops (FOREVER) execute repeatedly until a condition + occurs that invokes an explicit jump to the address of an instruction out- + side the loop. + At execution, the DO UNTIL instruction pushes: + • The address of the loop start instruction (PC + 1) onto the loop begin + stack. + • The address of the loop end instruction (PC + ) and the code + of the loop terminator onto the loop end stack. + • The contents of the CNTR register onto the loop counter stack. + + + + + ADSP-219x Instruction Set Reference 8-23 + Program Flow Instructions + + + + + During execution of a finite loop, the DSP tests and decrements the loop + counter value stored in the loop counter stack—not the value in the CNTR + register—at the end of each pass of the loop. + + " The register retains the original loop counter value until you + CNTR + load it with a new value, either explicitly with a load instruction or + with a POP LOOP instruction. + + To test the current value of the decrementing loop counter, you pop + the value off the loop counter stack into the CNTR register, move the + CNTR contents into a data register, and then push the CNTR contents + back onto the stack. + During execution of an infinite loop, the DSP pushes the current value of + the CNTR register and the FOREVER bit onto the loop counter stack. When + the FOREVER bit is set, the loop logic ignores the loop counter value. If you + set up an infinite loop with the PUSH LOOP instruction instead of the DO + UNTIL instruction, you must set the FOREVER bit of LPSTACKP (bit 15). (For + details, see “Loop Stacks Operation” on page 8-10 and “PUSH or POP + Stacks” on page 8-55.) + You can nest up to eight loops because each of the loop stacks have eight + locations. The DSP pushes the loop begin stack, loop end stack, and loop + counter stack for each level of nesting. + Follow these guidelines when coding loops: + • For nested loops, set up a separate counter for each loop, and end + each loop with a separate instruction. + • Do not use the RTI or RTS instruction inside a loop. + • Do not use a PUSH or POP instruction in the last seven lines of a loop. + Avoid using PUSH or POP instructions within loops. + + + + +8-24 ADSP-219x Instruction Set Reference + DO UNTIL (PC relative) + + + + + • Do not use a CALL instruction in the last line of a loop because the + return address then resides outside of the loop, a condition that + causes incorrect sequencing. + • You can use a JUMP instruction in the last line of an infinite loop. + • If you use a JUMP or CALL instruction to abort a loop, make sure you + handle the loop stacks properly (POP LOOP). POP LOOP automatically + pops each of the loop stacks. For details, see “Stacks” on page 8-7 + and “PUSH or POP Stacks” on page 8-55. +EXAMPLES + + /* a finite loop example */ + CNTR = 0xF; + IOPG = 0x1; + SI = AX0; + DM(I0 += M0) = SI; + MR=0, MX0 = DM(I0+=M0), MY0 = PM(I4+=M4); + DO a_finite_loop UNTIL CE; + MR = MR+MX0*MY0(SS), MX0 = DM(I0+=M0), MY0=PM(I4+=M4); + MR = MR+MX0*MY0(RND); + a_finite_loop: + IO(0xFF) = MR1; + + /* an infinite loop example */ + IOPG = 0x1; + I0 = 0x1000; + M0 = 1; + L0 = 0; + DO an_infinite_loop; + AX0 = DM(I0+=M0); + AR = AX0 + AY0; + IF AV JUMP exit_an_infinite_loop; + an_infinite_loop: + DM(I0 + 100) = AR; + NOP; /* 1st instruction after an infinite loop */ + NOP; + NOP; /* any number of instructions */ + NOP; + exit_an_infinite_loop: + POP LOOP; + + + + + ADSP-219x Instruction Set Reference 8-25 + Program Flow Instructions + + + + + JUMP an_infinite_loop +1; + + /* a nested loop example */ + AX0 = DM(I0 += M0), AY0 = PM(I4 += M4); + CNTR = 10; + DO outer_nested_loop UNTIL CE; + CNTR = 20; + DO middle_nested_loop UNTIL CE; + CNTR = 30; + DO inner_nested_loop UNTIL CE; + AR =AX0 + AY0, AX0=DM(I0 += M0), AY0=PM(I4 += M4); + inner_nested_loop: + DM(I2 += M2) = AR; + middle_nested_loop: + NOP; + outer_nested_loop: + NOP; + +SEE ALSO + + • “Type 11: Do ··· Until” on page 9-34 + • “Conditions” on page 8-2 + • “Counter-Based Conditions” on page 8-3 + • “Stacks” on page 8-7 + + + + +8-26 ADSP-219x Instruction Set Reference + Direct JUMP (PC relative) + + + + +Direct JUMP (PC relative) + + [IF COND] JUMP [(DB)] ; + + +FUNCTION + + This branch instruction causes program execution to continue at the offset + address specified in the instruction. The offset address is the sum of the PC + of the JUMP instruction and the 13-bit immediate value supplied in the + instruction (PC + ). + If execution is based on an optional condition, the JUMP instruction exe- + cutes only if the condition evaluates true and a NOP operation executes if + the condition evaluates false. Omitting the condition forces unconditional + execution of the loop. For a list of valid conditions, see “Conditions” on + page 8-2. + The branch can be immediate or delayed (using the optional ((DB)). If + immediate, the branch instruction executes immediately, but the instruc- + tion at the offset address (branch target) executes after a latency of four + NOP cycles. + + If using the optional delayed branch ((DB)) syntax, the branch instruction + executes immediately, but the instruction at the offset address (branch tar- + get) executes after a latency equal to four cycles. The two instructions + directly following the JUMP instruction execute in sequence during the first + two latency cycles if the branch is taken. Even if the branch is not taken, + the instructions occupying the two branch delay slots still execute. +INPUT + + Imm13 A 13-bit, twos-complement offset value added to the address (PC) + of the JUMP instruction. Valid values range from −4096 to + 4095. + + For good programming practice, always use a label, rather than a + numeric value, since a label is relocatable. + + + + + ADSP-219x Instruction Set Reference 8-27 + Program Flow Instructions + + + + +OUTPUT + + None. +STATUS FLAGS + + None. +DETAILS + + When using the (DB) option, you cannot insert the following instructions + after the JUMP instruction, in the two delayed branch slots: + • Stack manipulation instructions—PUSH/POP + • Branch instructions—JUMP, CALL, RTI, RTS + • Loop instruction—DO UNTIL + You can use the Indirect 16-bit Memory Write—Immediate Data instruc- + tion. For details, see “Indirect 16-bit Memory Write—immediate data” on + page 7-55. Because it is a double-word instruction, you must place it in + the first delay branch slot, right after the CALL instruction. + The number of cycles required to perform a JUMP operation depends on + whether the branch is taken or not. With the immediate branch option, + when the branch is taken, the DSP flushes the instruction pipeline except + for the JUMP instruction and inserts four NOP cycles. As shown in Table 8-1 + on page 8-29, when you use the (DB) option, the operation still takes five + cycles (JUMP instruction + four cycles of latency), but the DSP executes in + sequence the two instructions following the JUMP instruction, flushing + only the top of the instruction pipeline. + If the address range of this instruction is inadequate, you can use the + LJUMP instruction, but lose use of the (DB) option, or you can retain the + (DB) option and let the tools determine during assembly/linking whether + to use this instruction or substitute the LJUMP instruction. For details see + “Using Long Jumps and Calls” on page 8-20. + + + + +8-28 ADSP-219x Instruction Set Reference + Direct JUMP (PC relative) + + + + + Table 8-1. Branch (JUMP) Execution Cycles + +Branch Case Time to Execute Delayed Branch Fills Delayed Branch NOPs + +Taken 5 cycles 2 cycles 2 cycles + +Not Taken 1 cycle 0 cycles 0 cycles + + +EXAMPLES + + JUMP first_branch_target; /* immediate branch jump */ + NOP; /* any number of instructions */ + first_branch_target: + NOP; /* any number of instructions */ + NOP; + Jump second_branch_target (DB); /* delayed branch jump */ + AR = PASS 0; + AR = AX0 + AY0; /* these two instr. after jump execute */ + NOP; + NOP; /* any number of instructions */ + second_branch_target: + NOP; + NOP; /* any number of instructions */ + IF NE JUMP third_branch_target (DB); + MR = 0; /* these two instr. after (DB) jump execute */ + AR = PASS 0; /* whether or not cond branch is taken */ + NOP; + NOP; /* any number of instructions */ + third_branch_target: + NOP; + NOP; /* any number of instructions */ + +SEE ALSO + + • “Type 10: Direct Jump” on page 9-32 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + + + + + ADSP-219x Instruction Set Reference 8-29 + Program Flow Instructions + + + + +CALL (PC relative) + + CALL [(DB)] ; + + +FUNCTION + + This instruction causes the Program Sequencer to branch to the offset + address specified in the instruction and execute the subroutine at that + location. The offset address is the sum of the PC of the CALL instruction + and the 16-bit immediate value supplied in the instruction (PC + ). + The branch can be immediate or delayed (using the optional ((DB)). If + immediate, the branch instruction executes immediately, but the instruc- + tion at the offset address (branch target) executes after a latency of four + NOP cycles. + + If using the optional delayed branch ((DB)) syntax, the branch instruction + executes immediately, but the instruction at the offset address (branch tar- + get) executes after a latency equal to four cycles. The two instructions + directly following the CALL instruction execute in sequence during the first + two latency cycles of the branch. +INPUT + + imm16 16-bit, twos-complement offset value added to the address (PC) of + the CALL instruction or a declared label. Valid values range from + −32768 to +32767. + + For good programming practice, always use a label, rather than a + numeric value, since a label is relocatable. +OUTPUT + + None. + + + + +8-30 ADSP-219x Instruction Set Reference + CALL (PC relative) + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +PCSTKFULL, PCSTKLVL, STKOVERFLOW, LPSTKEMPTY, LPSTKFULL, STSSTKEMPTY +PCSTKEMPTY + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + +DETAILS + + Before branching, the Program Sequencer automatically pushes onto the + PC stack the return address of the next instruction to execute after return- + ing from the called subroutine. The next instruction to execute is: + • Immediate CALL The first instruction following the CALL + instruction. + • Delayed CALL The third instruction following the CALL + instruction. + To return from the subroutine, you must explicitly issue an RTS instruc- + tion. For details, see “Return from Subroutine” on page 8-52. + When using the (DB) option, you cannot insert the following instructions + after the CALL instruction, in the two delay branch slots: + • Stack manipulation instructions—PUSH/POP + • Branch instructions—JUMP, CALL, RTI, RTS + • Loop instruction—DO UNTIL + You can use the Indirect 16-bit Memory Write—Immediate Data instruc- + tion. For details, see “Indirect 16-bit Memory Write—immediate data” on + page 7-55. Because it is a double-word instruction, you must place it in + the first delay branch slot, right after the CALL instruction. + + + + + ADSP-219x Instruction Set Reference 8-31 + Program Flow Instructions + + + + + The number of cycles required to perform a CALL operation depends on + whether the branch is taken or not. With the immediate branch option, + when the branch is taken, the DSP flushes the instruction pipeline except + for the CALL instruction and inserts four NOP cycles. As shown in Table 8-2 + on page 8-32, when you use the (DB) option, the operation still takes five + cycles (CALL instruction + four cycles of latency), but the DSP executes in + sequence the two instructions following the CALL instruction, flushing + only the top of the instruction pipeline. + + Table 8-2. Branch (CALL) Execution Cycles + +Branch Case Time to Execute Delayed Branch Fills Delayed Branch NOPs + + Taken 5 cycles 2 cycles 2 cycles + + Not Taken 1 cycle 0 cycles 0 cycles + + + If the address range of this instruction is inadequate, you can use the + LCALL instruction, but you lose use of the (DB) option, or you can retain + the (DB) option and let the tools determine during assembly/linking + whether to use this instruction or substitute the LCALL instruction. For + details see “Using Long Jumps and Calls” on page 8-20 and “Long CALL” + on page 8-37. +EXAMPLES + + CALL data_shift_subroutine (DB); + AX0 = DM(I0 += M1), AY0 = PM(I4 += M5); /* these two instr. */ + AR = PASS 0; /* execute before (DB) branch starts */ + DM(I1 += M1) = SR0; /* RTS returns here */ + NOP; + NOP; /* any number of instructions */ + NOP; + data_shift_subroutine: + AR = AX0 + AY0; + AX1 = 3; SE = AR; + SR = ASHIFT SI (HI); + RTS; /* returns operation */ + + + + +8-32 ADSP-219x Instruction Set Reference + CALL (PC relative) + + + + +SEE ALSO + + • “Type 10: Direct Jump” on page 9-32 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + + + + + ADSP-219x Instruction Set Reference 8-33 + Program Flow Instructions + + + + +JUMP (PC relative) + + JUMP [(DB)] ; + + +FUNCTION + + This branch instruction causes program execution to continue at the offset + address specified in the instruction. The offset address is the sum of the PC + of the JUMP instruction and the 16-bit immediate value supplied in the + instruction (PC + ). + The branch can be immediate or delayed (using the optional ((DB)). If + immediate, the branch instruction executes immediately, but the instruc- + tion at the offset address (branch target) executes after a latency of four + NOP cycles. + + If using the optional delayed branch ((DB)) syntax, the branch instruction + executes immediately, but the instruction at the offset address (branch tar- + get) executes after a latency equal to four cycles. The two instructions + directly following the JUMP instruction execute in sequence during the first + two latency cycles of the branch. +INPUT + + imm16 16-bit, twos-complement offset value added to the address (PC) of + the JUMP instruction or a declared label. Valid values range from + −32768 to +32767. + + For good programming practice, always use a label, rather than a + numeric value, since a label is relocatable. +OUTPUT + + None. + + + + +8-34 ADSP-219x Instruction Set Reference + JUMP (PC relative) + + + + +STATUS FLAGS + + None. +DETAILS + + When using the (DB) option, you cannot insert the following instructions + in the two delay branch slots directly after the JUMP instruction: + • Stack manipulation instructions—PUSH/POP + • Branch instructions—JUMP, CALL, RTI, RTS + • Loop instruction—DO UNTIL + You can use the Indirect 16-bit Memory Write—Immediate Data instruc- + tion. For details, see “Indirect 16-bit Memory Write—immediate data” on + page 7-55. Because it is a double-word instruction, you must place it in + the first delay branch slot, right after the CALL instruction. + The number of cycles required to perform a JUMP operation depends on + whether the branch is taken or not. With the immediate branch option, + when the branch is taken, the DSP flushes the instruction pipeline except + for the JUMP instruction and inserts four NOP cycles. As shown in Table 8-1 + on page 8-29, when you use the (DB) option, the operation still takes five + cycles (JUMP instruction + four cycles of latency), but the DSP executes in + sequence the two instructions following the JUMP instruction, flushing + only the top of the instruction pipeline. + If the address range of this instruction is inadequate, you can use the + LJUMP instruction, but you lose use of the (DB) option, or you can retain + the (DB) option and let the tools determine during assembly/linking + whether to use this instruction or substitute the LJUMP instruction. For + details see “Using Long Jumps and Calls” on page 8-20 and “Long JUMP” + on page 8-40. + + + + + ADSP-219x Instruction Set Reference 8-35 + Program Flow Instructions + + + + +EXAMPLES + + .SECTION/PM seg_code; + JUMP my_cod2_label; /* jumps to 16-bit relative address */ + NOP; + NOP; /* any number of instructions */ + NOP; + my_code_exit_label: + NOP; /* jump from seg_cod2 comes here */ + NOP; + NOP; /* any number of instructions */ + NOP; + .SECTION/PM seg_cod2; + my_cod2_label: + NOP; + NOP; /* any number of instructions */ + NOP; + JUMP my_code_exit_label; + +SEE ALSO + + • “Type 10: Direct Jump” on page 9-32 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + + + + +8-36 ADSP-219x Instruction Set Reference + Long CALL + + + + +Long CALL + + [IF COND] LCALL ; + + +FUNCTION + + This instruction causes the Program Sequencer to branch to the absolute + address specified in the instruction and execute the subroutine at that + location. The absolute address is the 24-bit immediate value supplied in + the instruction. The 24-bit immediate value enables programs to access + any location in program memory address space. + If execution is based on a condition, the JUMP instruction executes only if + the condition evaluates true and a NOP operation executes if the condition + evaluates false. Omitting the condition forces unconditional execution of + the loop. For a list of valid conditions, see “Conditions” on page 8-2. +INPUT + + Imm24 24-bit, twos-complement value or a declared label. Values range + from −16777216 to +16777215. + + For good programming practice, always use a label, rather than a + numeric value, since a label is relocatable. +OUTPUT + + None. + + + + + ADSP-219x Instruction Set Reference 8-37 + Program Flow Instructions + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +PCSTKFULL, PCSTKLVL, STKOVERFLOW, LPSTKEMPTY, LPSTKFULL, STSSTKEMPTY +PCSTKEMPTY + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + +DETAILS + + For details on using the assembler’s and linker’s -jcs21 option to direct + the tools to determine when to replace PC relative CALL instructions with + this instruction, see “Using Long Jumps and Calls” on page 8-20. + This is a double-word instruction, so it executes in six (2 instruction + 4 + latency) cycles. + Before branching, the Program Sequencer automatically pushes onto the + PC stack the return address of the next instruction to execute after return- + ing from the called subroutine. The next instruction to execute is the first + instruction following the LCALL instruction. + To return from the subroutine, you must explicitly issue an RTS instruc- + tion. For details, see “Return from Subroutine” on page 8-52. +EXAMPLES + + .SECTION/PM seg_code; + IF EQ LCALL my_faraway_routine; + NOP; /* execution returns here */ + NOP; + NOP; /* any number of instructions */ + NOP; + + .SECTION/PM seg_cod2; + my_faraway_routine: + NOP; + NOP; /* any number of instructions */ + + + + +8-38 ADSP-219x Instruction Set Reference + Long CALL + + + + + NOP; + RTS; + +SEE ALSO + + • “Type 36: Long Jump/Call” on page 9-59 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + • “Using Long Jumps and Calls” on page 8-20. + + + + + ADSP-219x Instruction Set Reference 8-39 + Program Flow Instructions + + + + +Long JUMP + + [IF COND] LJUMP ; + + +FUNCTION + + This branch instruction causes program execution to continue at the abso- + lute address specified in the instruction. The absolute address is the 24-bit + immediate value supplied in the instruction. The 24-bit immediate value + enables programs to access any location in program memory address space. + If execution is based on a condition, the JUMP instruction executes only if + the condition evaluates true and a NOP operation executes if the condition + evaluates false. Omitting the condition forces unconditional execution of + the loop. For a list of valid conditions, see “Conditions” on page 8-2. + + " This instruction is a two-word instruction and requires (at mini- + mum) six cycles to execute. For more information, see “Type 36: + Long Jump/Call” on page 9-59. +INPUT + + Imm24 24-bit, twos-complement value or a declared variable. Values range + from −16777216 to +16777215. + + For good programming practice, always use a label, rather than a + numeric value, since a label is relocatable. +OUTPUT + + None. +STATUS FLAGS + + None. + + + + +8-40 ADSP-219x Instruction Set Reference + Long JUMP + + + + +DETAILS + + For details on using the ADSP-219x assembler’s -jcs2l (convert + Jump/Call Short to Long) option to direct the tools to determine when to + replace PC relative JUMP instructions with LJUMP instructions, see “Using + Long Jumps and Calls” on page 8-20. +EXAMPLES + + /* Long JUMP example nearby half */ + + .SECTION/PM seg_code; + .GLOBAL my_local_exit_label; + .EXTERN my_faraway_label; + LJUMP my_faraway_label; /* jumps to 24-bit relative addr */ + NOP; + NOP; /* any number of instructions */ + NOP; + my_local_exit_label: + NOP; /* jump from seg_cod2 comes here */ + NOP; + NOP; /* any number of instructions */ + + /* Long JUMP example faraway half */ + + .SECTION/PM seg_xpmc; + .GLOBAL my_faraway_label; + .EXTERN my_local_exit_label; + my_faraway_label: + NOP; /* any number of instructions */ + NOP; + LJUMP my_local_exit_label; + +SEE ALSO + + • “Type 36: Long Jump/Call” on page 9-59 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + • “Using Long Jumps and Calls” on page 8-20. + + + + ADSP-219x Instruction Set Reference 8-41 + Program Flow Instructions + + + + +Indirect CALL + + [IF COND] CALL () [(DB)] ; + + +FUNCTION + + This instruction causes the Program Sequencer to branch to the address + pointed to by the DAG index register ( Ireg). The Ireg supplies the six- + teen LSBs of the 24-bit address, and the IJPG register supplies the eight + MSBs (page address) of the 24-bit address. You must explicitly load the + IJPG register with the eight MSBs of the address before executing this + instruction (for details, see “Data Move Instructions” on page 7-1). + If execution is based on a condition, the CALL instruction executes only if + the condition evaluates true, and a NOP operation executes if the condition + evaluates false. Omitting the condition forces unconditional execution of + the loop. For a list of valid conditions, see “Conditions” on page 8-2. + The branch can be immediate or delayed (using the optional ((DB)). If + immediate, the branch instruction executes immediately, but the instruc- + tion at the offset address (branch target) executes after a latency of four + NOP cycles. + + If using the optional delayed branch ((DB)) syntax, the branch instruction + executes immediately, but the instruction at the offset address (branch tar- + get) executes after a latency equal to four cycles. The two instructions + directly following the CALL instruction execute in sequence during the first + two latency cycles if the branch is taken. Even if the branch is not taken, + the instructions occupying the two branch delay slots still execute. +INPUT + + Ireg I0–I3 (DAG1 index registers) or I4–I7 (DAG2 index registers) + +OUTPUT + + None. + + + +8-42 ADSP-219x Instruction Set Reference + Indirect CALL + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +PCSTKFULL, PCSTKLVL, STKOVERFLOW, LPSTKEMPTY, LPSTKFULL, STSSTKEMPTY +PCSTKEMPTY + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + +DETAILS + + Before branching, the Program Sequencer automatically pushes onto the + PC stack the return address of the next instruction to execute after return- + ing from the called subroutine. The next instruction to execute is: + • Immediate CALL The first instruction following the CALL + instruction. + • Delayed CALL The third instruction following the CALL + instruction. + + " Toinstruction. + return from the subroutine, you must explicitly issue an + For details, see “Return from Subroutine” on + RTS + + + page 8-52. + When using the (DB) option, you cannot insert the following instructions + after the CALL instruction, in the two delay branch slots: + • Stack manipulation instructions—PUSH/POP + • Branch instructions—JUMP, CALL, RTI, RTS + • Loop instruction—DO UNTIL + You can use the Indirect 16-bit Memory Write—Immediate Data instruc- + tion (for details, see page 7-55), but because it is a double-word + instruction, you must place it in the first delay branch slot, right after the + CALL instruction. + + + + + ADSP-219x Instruction Set Reference 8-43 + Program Flow Instructions + + + + + The number of cycles required to perform a CALL operation depends on + whether the branch is taken or not. With the immediate branch option, + when the branch is taken, the DSP flushes the instruction pipeline except + for the CALL instruction and inserts four NOP cycles. As shown in Table 8-2 + on page 8-32, when you use the (DB) option, the operation still takes five + cycles (CALL instruction + four cycles of latency), but the DSP executes in + sequence the two instructions following the CALL instruction, flushing + only the top of the instruction pipeline. +EXAMPLES + + I5 = sampling_routine; + AR = AR + AX0; + IF EQ CALL (I5) (DB); + DM(I0 += M1) = AR; /* these two instr. execute */ + AR = 0; /* whether or not the branch is taken */ + AR = PASS 0; /* RTS returns execution to this instr. */ + NOP; + NOP; /* any number of instructions */ + NOP; + + sampling_routine: + MX0 = DM(I0+=M1); + MR = MX0 * MY0 (SS); + NOP; + NOP; /* any number of instructions */ + NOP; + RTS; + +SEE ALSO + + • “Type 19: Indirect Jump/Call” on page 9-41 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + + + + +8-44 ADSP-219x Instruction Set Reference + Indirect JUMP + + + + +Indirect JUMP + + [IF COND] JUMP () [(DB)] ; + + +FUNCTION + + This branch instruction causes program execution to continue at the + address pointed to by the DAG index register (Ireg). The Ireg supplies + the sixteen LSBs of the 24-bit address, and the IJPG register supplies the + eight MSBs (page address) of the 24-bit address. You must explicitly load + the IJPG register with the eight MSBs of the address before executing this + instruction (for details, see “Data Move Instructions” on page 7-1). + If execution is based on a condition, the JUMP instruction executes only if + the condition evaluates true, and a NOP operation executes if the condition + evaluates false. Omitting the condition forces unconditional execution of + the loop. For a list of valid conditions, see “Conditions” on page 8-2. + The branch can be immediate or delayed (using the optional ((DB)). If + immediate, the branch instruction executes immediately, but the instruc- + tion at the offset address (branch target) executes after a latency of four + NOP cycles. + + If using the optional delayed branch ((DB)) syntax, the branch instruction + executes immediately, but the instruction at the offset address (branch tar- + get) executes after a latency equal to four cycles. The two instructions + directly following the JUMP instruction execute in sequence during the first + two latency cycles if the branch is taken. Even if the branch is not taken, + the instructions occupying the two branch delay slots still execute. +INPUT + + Ireg I0–I3 (DAG1 index registers) or I4–I7 (DAG2 index registers) + +OUTPUT + + None. + + + + ADSP-219x Instruction Set Reference 8-45 + Program Flow Instructions + + + + +STATUS FLAGS + + None. +DETAILS + + Loading the IJPG register or an Ireg has a zero (0) effect latency for this + instruction, so the new value is available on the next instruction cycle. + When using the (DB) option, you cannot insert the following instructions + after the JUMP instruction, in the two delay branch slots: + • Stack manipulation instructions—PUSH/POP + • Branch instructions—JUMP, CALL, RTI, RTS + • Loop instruction—DO UNTIL + You can use the Indirect 16-bit Memory Write—Immediate Data instruc- + tion. For details, see “Indirect 16-bit Memory Write—immediate data” on + page 7-55. Because it is a double-word instruction, you must place it in + the first delay branch slot, right after the JUMP instruction. + The number of cycles required to perform a JUMP operation depends on + whether the branch is taken or not. With the immediate branch option, + when the branch is taken, the DSP flushes the instruction pipeline except + for the JUMP instruction and inserts four NOP cycles. As shown in Table 8-1 + on page 8-29, when you use the (DB) option, the operation still takes five + cycles (JUMP instruction + four cycles of latency), but the DSP executes in + sequence the two instructions following the JUMP instruction, flushing + only the top of the instruction pipeline. +EXAMPLES + + I4 = sampling; + I5 = next_sample; + + sampling: + AR = AR + AX0; + IF EQ JUMP (I5) (DB); + + + + +8-46 ADSP-219x Instruction Set Reference + Indirect JUMP + + + + + DM(I0 += M1) = AR; /* these two instr. execute */ + AR = 0; /* whether or not the branch is taken */ + JUMP (I4) (DB); + AX0 = DM(I0 += M1); /* these two instr. execute */ + AR = AX0; /* before the branch starts */ + + next_sample: + MX0 = DM(I0 += M1); + MR = MX0 * MY0 (SS); + NOP; + NOP; /* any number of instructions */ + NOP; + JUMP (I4); /* goes back to sampling */ + +SEE ALSO + + • “Type 19: Indirect Jump/Call” on page 9-41 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + + + + + ADSP-219x Instruction Set Reference 8-47 + Program Flow Instructions + + + + +Return from Interrupt + + [IF COND] RTI [(DB)] [(SS)] ; + + +FUNCTION + + This instruction executes a return from an interrupt service routine (ISR). + It returns program execution to the address of either the first or third + instruction following the branch instruction that launched the ISR. + If execution is based on a condition, the RTI instruction executes only if + the condition evaluates true, and a NOP operation executes if the condition + evaluates false. Omitting the condition forces unconditional execution of + the loop. For a list of valid conditions, see “Conditions” on page 8-2. + The branch can be immediate or delayed (using the optional ((DB)). If + immediate, the branch instruction executes immediately, but the instruc- + tion at the offset address (branch target) executes after a latency of four + NOP cycles. + + If using the optional delayed branch ((DB)) syntax, the branch instruction + executes immediately, but the instruction at the offset address (branch tar- + get) executes after a latency equal to four cycles. The two instructions + directly following the RTI instruction execute in sequence during the first + two latency cycles if the branch is taken. Even if the branch is not taken, + the instructions occupying the two branch delay slots still execute. + For emulation, the RTI instruction supports an additional option, the sin- + gle-step (SS) return interrupt. This option causes the instruction at the + return address to generate an interrupt when it executes during emulation. +INPUT + + None. + + + + +8-48 ADSP-219x Instruction Set Reference + Return from Interrupt + + + + +OUTPUT + + None. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + PCSTKFULL, PCSTKEMPTY, PCSTKLVL LPSTKEMPTY, LPSTKFULL, STKOVER- + FLOW, STSSTKEMPTY + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + +DETAILS + + This instruction pops and uses the address at top of the PC stack for the + return address. It also pops the value at the top of the status stack and + loads it into the arithmetic status register (ASTAT) and the mode status reg- + ister (MSTAT). So if the ISR enabled secondary registers or changed other + DSP modes in MSTAT, the RTI instruction automatically disables them + when it executes. + + " Do not use an instruction inside a loop without explicitly per- + forming stack maintenance. + RTI + + + + When using the (DB) option, you cannot insert the following instructions + after the RTI instruction, in the two delay branch slots: + • Stack manipulation instructions—PUSH/POP + • Branch instructions—JUMP, CALL, RTI, RTS + • Loop instruction—DO UNTIL + You can use the Indirect 16-bit Memory Write—Immediate Data instruc- + tion. For details, see “Indirect 16-bit Memory Write—immediate data” on + page 7-55. Because it is a double-word instruction, you must place it in + the first delay branch slot, directly following the RTI instruction. + + + + ADSP-219x Instruction Set Reference 8-49 + Program Flow Instructions + + + + + The number of cycles required to perform an RTI depends on whether the + branch is taken or not. With the immediate branch option, when the + branch is taken, the DSP flushes the instruction pipeline except for the + RTI instruction and inserts four NOP cycles. As shown in Table 8-3, when + you use the (DB) option, the operation still takes five cycles (RTI instruc- + tion + four cycles of latency), but the DSP executes in sequence the two + instructions following the RTI instruction, flushing only the top of the + instruction pipeline. + + Table 8-3. Branch (RTI) Execution Cycles + +Branch Case Time to Execute Delayed Branch Fills Delayed Branch NOPs + + Taken 5 cycles 2 cycles 2 cycles + + Not Taken 2 cycle 0 cycles 1 cycle + + +EXAMPLES + + interrupt_setup: + /* defined addr of inter. priority registers in IO() memory */ + #define IPR0 0x203 + #define IPR1 0x204 + #define IPR2 0x205 + #define IPR3 0x206 + /* loads interrupt priorities into IPR registers */ + AX0 = 0x3210; + IO(IPR0) = AX0; /* set priorities for peripherals 3-0 */ + AX0 = 0x7654; + IO(IPR1) = AX0; /* set priorities for peripherals 7-4 */ + AX0 = 0xBA98; + IO(IPR2) = AX0; /* set priorities for peripherals 11-8 */ + AX0 = 0x0BBB; + IO(IPR3) = AX0; /* set priorities for peripherals 14-12 */ + + ICNTL = 0x0010; /* set GIE global interrupt enable bit */ + IMASK = 0x4000; /* unmask interrupt ID 14, which is + assigned to Timer Interrupt A by IPR2 */ + ENA INT; /* enable interrupts */ + + + + +8-50 ADSP-219x Instruction Set Reference + Return from Interrupt + + + + + wait_here_for_interrupt: /* loop waiting for interrupt */ + NOP; + NOP; /* any number of instructions */ + NOP; + JUMP wait_here_for_interrupt; + + .SECTION/PM irq_14; /* map this ISR to addr. 0x01C0 with LDF */ + timer_a_int: + ENA SEC_REG, ENA SEC_DAG; + NOP; + NOP; /* up to 32 instructions */ + NOP; + RTI; + +SEE ALSO + + • “Type 20: Return” on page 9-42 + • “Interrupts” on page 8-13 + • “Set Interrupt” on page 8-62 + • “Clear Interrupt” on page 8-64. + + + + + ADSP-219x Instruction Set Reference 8-51 + Program Flow Instructions + + + + +Return from Subroutine + + [IF COND] RTS [(DB)] ; + + +FUNCTION + + This instruction executes a return from a subroutine. It returns program + execution to the address of either the first or third instruction following + the branch instruction that called the subroutine. + If execution is based on a condition, the RTS instruction executes only if + the condition evaluates true, and a NOP operation executes if the condition + evaluates false. Omitting the condition forces unconditional execution of + the branch. For a list of valid conditions, see “Conditions” on page 8-2. + The branch can be immediate or delayed (using the optional ((DB)). If + immediate, the branch instruction executes immediately, but the instruc- + tion at the offset address (branch target) executes after a latency of four + NOP cycles. + + If using the optional delayed branch ((DB)) syntax, the branch instruction + executes immediately, but the instruction at the offset address (branch tar- + get) executes after a latency equal to four cycles. The two instructions + directly following the RTS instruction execute in sequence during the first + two latency cycles if the branch is taken. Even if the branch is not taken, + the instructions occupying the two branch delay slots still execute. + + " Do not use an instruction inside a loop without explicitly per- + RTS + forming stack maintenance. For details, see begin stack. +INPUT + + None. +OUTPUT + + None. + + + + +8-52 ADSP-219x Instruction Set Reference + Return from Subroutine + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + PCSTKFULL, PCSTKEMPTY, PCSTKLVL LPSTKEMPTY, LPSTKFULL, STKOVER- + FLOW, STSSTKEMPTY + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + +DETAILS + + This instruction pops and uses the address at top of the PC stack for the + return address. + When using the (DB) option, you cannot insert the following instructions + after the RTS instruction, in the two delay branch slots: + • Stack manipulation instructions—PUSH/POP + • Branch instructions—JUMP, CALL, RTI, RTS + • Loop instruction—DO UNTIL + You can use the Indirect 16-bit Memory Write—Immediate Data instruc- + tion (for details, see page 7-55), but because it is a double-word + instruction, you must place it in the first delay branch slot, right after the + RTI instruction. + + The number of cycles required to perform an RTS depends on whether the + branch is taken or not. With the immediate branch option, when the + branch is taken, the DSP flushes the instruction pipeline except for the + RTS instruction and inserts four NOP cycles. As shown in Table 8-4 on + page 8-54, when you use the (DB) option, the operation still takes five + cycles (RTS instruction + four cycles of latency), but the DSP executes in + + + + + ADSP-219x Instruction Set Reference 8-53 + Program Flow Instructions + + + + + sequence the two instructions following the RTS instruction, flushing only + the top of the instruction pipeline. + + Table 8-4. Branch (RTS) Execution Cycles + +Branch Case Time to Execute Delayed Branch Fills Delayed Branch NOPs + + Taken 5 cycles 2 cycles 2 cycles + + Not Taken 1 cycle 0 cycles 0 cycle + + +EXAMPLES + + I5 = sample_routine; + AR = AR + AX0; + IF EQ CALL (I5) (DB); + DM(I0 += M1) = AR; /* these two instr. execute */ + AR = 0; /* whether or not the branch is taken */ + AR = PASS 0; /* RTS returns execution to this instr. */ + NOP; + NOP; /* any number of instructions */ + NOP; + + sample_routine: + MX0 = DM(I0+=M1); + MR = MX0 * MY0 (SS); + NOP; + NOP; /* any number of instructions */ + NOP; + RTS; + +SEE ALSO + + • “Type 20: Return” on page 9-42 + • “Branch Options” on page 8-5 + • “Addressing Branch Targets” on page 8-6 + + + + +8-54 ADSP-219x Instruction Set Reference + PUSH or POP Stacks + + + + +PUSH or POP Stacks + + PUSH PC ; + POP LOOP + STS + + +FUNCTION + + This instruction PUSHes (stores) or POPs (retrieves) a value from the top of + the specified stack: PC, LOOP, or STS. + • PC + + On a PUSH, stores onto the top of the PC stack a 24-bit address value + assembled from the STACKA and STACKP registers. STACKA provides + the sixteen LSBs of the address, and STACKP provides the eight MSBs + of the address. + On a POP, retrieves the most recently stacked 24-bit address value + from the top of the PC stack into the STACKA and STACKP registers. + STACKA receives the sixteen LSBs of the address, and STACKP receives + the eight MSBs of the address. + • LOOP + + On a PUSH, stores onto the top of the loop begin stack the 24-bit + loop start address assembled from the STACKA and STACKP registers, + pushes onto the top of the loop end stack the 24-bit loop end + address assembled from the LPSTACKA and LPSTACKP registers, and + pushes onto the top of the loop counter stack the current loop + counter value from the CNTR register. + On a POP, retrieves the most recently stacked 24-bit loop start + address from the top of the loop begin stack into the STACKA and + STACKP registers, pops the most recently stacked 24-bit loop end + address from the top of the loop end stack into the LPSTACKA and + + + + + ADSP-219x Instruction Set Reference 8-55 + Program Flow Instructions + + + + + LPSTACKP registers, and pops the current loop counter value from + the top of the loop counter stack into the CNTR register. + • STS + + On a PUSH, stores the current values of the ASTAT and MSTAT registers + onto the status stack. After each push, the status stack pointer incre- + ments by one to access the next available location in the stack. + On a POP, retrieves the most recently stacked 16-bit value of the + ASTAT and MSTAT registers from the top of the status stack. After each + individual pop, the status stack pointer decrements by one to access + the next lowest location (next register value) in the stack. + + " Abut a or or + PUSH + PUSH + POP PC has one cycle of latency for all SSTAT register bits, + POP LOOP or STS has one cycle of latency only for the + STKOVERFLOW bit in the SSTAT register. + +INPUT + + None. +OUTPUT + + None. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +PCSTKEMPTY (affected on POP), PCSTK- (none) +FULL, PCSTKLVL (affected on POP), +LPSTKEMPTY, LPSTKFULL, STSSTKEMPTY +(affected on POP), STKOVERFLOW + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + + + +8-56 ADSP-219x Instruction Set Reference + PUSH or POP Stacks + + + + +DETAILS ( PUSH ) + + You can push up to two stacks in parallel by issuing two PUSH instructions + on the same instruction line, pushing either: + PUSH PC, PUSH STS; + + or + PUSH LOOP, PUSH STS; + + + " Do not). push the PC and LOOP stacks in parallel ( + LOOP; + PUSH PC, PUSH + + + + If you push the PC and loop stacks in parallel, you push the same + address value onto both the PC stack and the loop begin stack. This + occurs because STACKA and STACKP serve as the source registers for + both stacks. + Regardless of the number of stacks pushed, this instruction always exe- + cutes in a single cycle. + Subroutines, loops, and interrupts automatically push certain stacks: + • Calls to subroutines and entry into interrupt service routines auto- + matically push the PC stack. + • Execution of the DO UNTIL instruction pushes the loop begin stack, + the loop end stack, and the loop counter stack. +Do not use this instruction in either of the two slots directly following a +delayed branch instruction. + + " Do not use this instruction inside a loop without explicitly perform- + ing stack maintenance. For details, see “PUSH or POP Stacks” on + page 8-55 + + + + + ADSP-219x Instruction Set Reference 8-57 + Program Flow Instructions + + + + + " Ifmustyousetsetbitup15anofinfinite looptowith + LPSTACKP + thePUSH LOOP instruction, you + indicate FOREVER. Although the + LPSTACKP register has sixteen bits, but only bit 15 and bits 7:0 are + valid. When the FOREVER bit is set (bit 15 = 1), the loop logic ignores + the loop counter value. When the FOREVER bit is cleared (bit 15 = 0), + CE is the loop terminator condition, and the loop logic decrements + the loop counter value. +DETAILS ( POP ) + + You can pop up to two stacks in parallel by issuing two POP instructions + on the same instruction line, popping either: + POP PC, POP STS; + + or + POP LOOP, POP STS; + + + " Do not pop the PC and loop stacks in parallel ( POP PC, POP LOOP;). + + + If you pop the PC and loop stacks in parallel, you lose the loop start + address retrieved from the loop begin stack. This occurs because + STACKA and STACKP serve as the destination registers for values + popped from both the PC stack and the loop begin stack. In this + case, STACKA and STACKP receive the most recently stacked PC value. + Regardless of the number of stacks popped, this instruction always exe- + cutes in a single cycle. + Subroutines, loops, and interrupts automatically pop certain stacks: + • Upon exiting, RTS and RTI instructions automatically pop the PC + stack. + • Loop termination automatically pops the loop begin stack, the loop + end stack, and the loop counter stack + + + + +8-58 ADSP-219x Instruction Set Reference + PUSH or POP Stacks + + + + + " Do not use this instruction in either of the two slots directly follow- + ing a delayed branch instruction. + + " Do not use this instruction inside a loop without explicitly perform- + ing stack maintenance. For details, see “PUSH or POP Stacks” on + page 8-55. +EXAMPLES ( PUSH ) + + /* Pushing an infinite loop—loop terminator condition = + FOREVER: */ + + STACKA = 0x0045; + STACKP = 0x03; + LPSTACKA = 0x004C; + LPSTACKP = 0x03; + PUSH LOOP; + + /* Saving the DSP’s current state: */ + + STACKA = 0x0022; + STACKP = 0x05; + PUSH PC, PUSH STS; + +EXAMPLES ( POP ) + + /* Restoring the DSP’s current state: */ + + POP PC, POP STS; + AR = TSTBIT 6 OF AX0; + IF EQ CALL primary; + AX1 = STACKA; + AY1 = STACKP; + IJPG = AY1; + primary: DIS SEC_DAG, DIS SEC_REG; + RTS; + + /* Aborting a loop: */ + + CNTR = 10; + MX0 = DM(I2 += M2), + MY0 = PM(I5 += M5); + DO mac UNTIL CE; + + + + + ADSP-219x Instruction Set Reference 8-59 + Program Flow Instructions + + + + + MR = MR + MX0 * MY0 (SS), + MX0 = DM(I2 += M2), + MY0 = PM(I5 += M5); + IF MV JUMP abort; + mac: + DM(I0 += M1) = MR0; + NOP; + NOP; /* any number of instructions */ + NOP; + abort: + POP LOOP; + JUMP mac + 1; + +SEE ALSO + + • “Type 26:Push/Pop/Cache” on page 9-50 + • “MSTAT Mode Control Register” on page 8-4 + • “Stacks” on page 8-7 + • “PC and Status Stack Operation” on page 8-8 + • “Loop Stacks Operation” on page 8-10 + + + + +8-60 ADSP-219x Instruction Set Reference + FLUSH CACHE + + + + +FLUSH CACHE + + FLUSH CACHE ; + + +FUNCTION + + This instruction flushes the instruction cache, invalidating all instructions + currently cached, so the next instruction fetch results in a memory access. + Use this instruction when program memory changes to resynchronize the + instruction cache with program memory. +INPUT + + None. +OUTPUT + + None. +STATUS FLAGS + + None. +DETAILS + + This operation may require up to six cycles to take effect. + + " Do not use this instruction in either of the two slots directly follow- + ing a delayed branch instruction. +EXAMPLES + + FLUSH CACHE; + +SEE ALSO + + • “Type 26:Push/Pop/Cache” on page 9-50 + + + + + ADSP-219x Instruction Set Reference 8-61 + Program Flow Instructions + + + + +Set Interrupt + + SETINT n ; + + +FUNCTION + + This instruction sets bit n (n = 1) in the interrupt latch register (IRPTL) and + its associated interrupt. If the specified interrupt is unmasked, its corre- + sponding bit in the IMASK register is set, program flow immediately + branches to and executes the interrupt’s service routine. Otherwise, the + interrupt request remains latched but ignored until the program unmasks + it or clears it. If unmasked, the interrupt’s ISR executes; if cleared, the + interrupt request is rejected. +INPUT + + n Specifies which bit (and interrupt) in the IRPTL register to set. + Valid values range from 0–15. + The mapping of bits to interrupts is specific to particular DSPs in + the ADSP-219x family. For details, see the ADSP-219x/2191 DSP + Hardware Reference. +OUTPUT + + None. +OPTIONS + + None. + + + + +8-62 ADSP-219x Instruction Set Reference + Set Interrupt + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +PCSTKFULL, PCSTKEMPTY, PCSTKLVL, LPSTKEMPTY, LPSTKFULL +STSSTKEMPTY, STKOVERFLOW + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + +DETAILS + + This instruction has no associated effect latency. +EXAMPLES + + MR = MR+MX0*MY0(SS), MX0 = DM(I0+=M0), MY0 = PM(I4+=M4); + IF MV SAT MR; + IF LT JUMP adjust; + + adjust: SETINT 12; + +SEE ALSO + + “Stacks” on page 8-7. + “Interrupts” on page 8-13. + “Clear Interrupt” on page 8-64. + “Type 37: Interrupt” on page 9-60. + + + + + ADSP-219x Instruction Set Reference 8-63 + Program Flow Instructions + + + + +Clear Interrupt + + CLRINT n ; + + +FUNCTION + + This instruction clears bit n ( n = 0) in the interrupt latch register (IRPTL) + and its associated interrupt. + This instruction clears a pending interrupt. It is used, in an ISR for exam- + ple, to clear a pending interrupt that has been detected, but not yet been + serviced. +INPUT + + n Specifies which bit (and interrupt) in the IRPTL register to clear. + Valid values range from 0–15. + The mapping of bits to interrupts is specific to particular DSPs in + the ADSP-219x family. For details, see the ADSP-219x/2191 DSP + Hardware Reference. +OUTPUT + + None. +OPTIONS + + None. + + + + +8-64 ADSP-219x Instruction Set Reference + Clear Interrupt + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + PCSTKFULL, PCSTKEMPTY, PCSTKLVL, + STSSTKEMPTY, STKOVERFLOW, LPST- + KEMPTY, LPSTKFULL + +For information on these status bits in the SSTAT register, see Table 2-7 on page 2-14. + + +DETAILS + + This instruction has no associated latency. +EXAMPLES + + AX0 = IRPTL; + AR = TSTBIT 12 of AX0; + IF EQ JUMP clear; + + clear: CLRINT 12; + +SEE ALSO + + “Stacks” on page 8-7. + “Interrupts” on page 8-13. + “Return from Interrupt” on page 8-48. + “Set Interrupt” on page 8-62. + “Type 37: Interrupt” on page 9-60. + + + + + ADSP-219x Instruction Set Reference 8-65 + Program Flow Instructions + + + + +No Operation + + NOP ; + + +FUNCTION + + This instruction causes the DSP’s core to perform no operation for one + cycle. Program execution continues with the instruction directly following + the NOP instruction. +INPUT + + None. +OUTPUT + + None. +STATUS FLAGS + + None. +DETAILS + + Only the core ceases operation for one cycle; the on-chip peripherals con- + tinue their respective operations. +EXAMPLES + + NOP; /* no operation */ + +SEE ALSO + + “Type 30: NOP” on page 9-52. + + + + +8-66 ADSP-219x Instruction Set Reference + Idle + + + + +Idle + + IDLE ; + + +FUNCTION + + This instruction directs the DSP’s core to wait indefinitely in a low-power + state until an interrupt occurs. When an interrupt occurs, the DSP’s core + exits the low-power state, services the interrupt, then continues program + execution at the instruction directly following the IDLE instruction. +INPUT + + None. +OUTPUT + + None. +OPTIONS + + A 4-bit divisor value used to calculate the reduction in frequency of + the DSP’s internal clock during Slow Idle mode. The Slow Idle rate + equals the frequency of the internal clock divided by this value. + Valid values are 0-15. + + " This option is not available on the 2192 or 2191. +STATUS FLAGS + + None. +DETAILS + + Applications typically use this instruction to implement a low-power + standby loop: + standby: IDLE(16); + JUMP standby; + + + + + ADSP-219x Instruction Set Reference 8-67 + Program Flow Instructions + + + + + next_instruction; + + In Idle mode, the DSP’s response time to incoming interrupts is one cycle. + In Slow Idle mode, the DSP’s response time to incoming interrupts slows + accordingly. When an incoming interrupt occurs, full recovery from the + IDLE(imm4) state takes up to DSP cycles. + + Using IDLE(imm4) in systems that have an externally-generated serial clock + may result in a serial clock rate that is faster than the DSP’s reduced inter- + nal clock rate. Because of this and the DSP’s reduced response time to + interrupts, applications must avoid generating interrupts faster than the + DSP can service them. + Some DSPs in the ADSP-219x family also support a sleep mode, in which + the DSP’s core and all of its on-chip peripherals enter Idle mode. To + invoke sleep mode, the application must program the appropriate bits in + the PLL control and I/O clock control registers and use the standard IDLE + instruction. Exiting sleep mode requires a hardware reset. +EXAMPLES + + IDLE; /* Idle at internal clock’s rate */ + +SEE ALSO + + “No Operation” on page 8-66. + “Type 31: Idle” on page 9-53. + + + + +8-68 ADSP-219x Instruction Set Reference + Mode Control + + + + +Mode Control + + ENA SEC_REG ; + BIT_REV + DIS + AV_LATCH + AR_SAT + M_MODE + TIMER + SEC_DAG + INT + + +FUNCTION + + This instruction enables (ENA) or disables (DIS) from one to seven DSP + modes in parallel. To enable or disable a mode, this instruction sets (1) or + clears (0), respectively, the mode’s bit in the mode status register, MSTAT + (for details, “Mode Status (MSTAT) Register” on page 2-11). The DSP + modes are: + • SEC_REG Secondary computation register bank (MSTAT[0]). + • BIT_REV Bit-reversed addressing mode (MSTAT[1]). + • AV_LATCH ALU overflow status mode (MSTAT[2]). + • AR_SAT ALU AR register saturation mode (MSTAT[3]). + • M_MODE MAC integer operand format mode (MSTAT[4]). + • TIMER Timer enable (MSTAT[5]). + • SEC_DAG Secondary DAG address register bank (MSTAT[6]). + • INT Global interrupts +INPUT + SEC_REG, BIT_REV, AV_LATCH, AR_SAT, M_MODE, TIMER, SEC_DAG, INT + + + + + ADSP-219x Instruction Set Reference 8-69 + Program Flow Instructions + + + + +OUTPUT + + None. +STATUS FLAGS + + None. +DETAILS + + You can enable or disable one or more modes in parallel by issuing multi- + ple DIS or ENA instructions on the same instruction line, as in: + ENA AR_SAT, ENA M_MODE, ENA AV_LATCH, ENA SEC_REG; + + + " You cannot issue both and + DIS instructions on the same instruc- + ENA + tion line to enable and disable modes in parallel (as in: ENA AR_SAT, + DIS AV_LATCH, ENA SEC_DAG;) + + As shown in Table 7-2 on page 7-10, changing modes using this instruc- + tion, as opposed to register writes or popping the status stack, does not + incur any cycles of latency. Latency is the delay, in number of instruction + cycles, between the time the mode change instruction executes and the + time when the mode change takes effect, such that other instructions can + execute operations based on the new value. A latency of 0 means that + mode change is available to the instruction directly following the mode + change instruction. + + " effect on thesetsnextorinstruction + ENA/DIS INT clears bit 5 in the + cycle. + ICNTL register. The write takes + + + +EXAMPLES + + /* Switching contexts during an ISR: */ + + ENA INT; + IMASK = 0x21A0; + ENA SEC_REG, ENA SEC_DAG; + AY0 = DM(I0 += M0); + RTI (DB); + + + + +8-70 ADSP-219x Instruction Set Reference + Mode Control + + + + + AR = AX0 + AY0; + DM(I0 += M0) = AR; + + /* Bit-reversing DAG1 output to memory: */ + + ENA BIT_REV; + AY0 = DM(I0 += M0); + AR = AX0 + AY0; + DM(I0 += M0) = AR; + DIS BIT_REV; + +SEE ALSO + + • “Type 18: Mode Change” on page 9-40 + • “MSTAT Mode Control Register” on page 8-4 + • “Enabling Interrupts” on page 8-14 + • “Effect Latencies” on page 8-21 + + + + + ADSP-219x Instruction Set Reference 8-71 + Program Flow Instructions + + + + +8-72 ADSP-219x Instruction Set Reference + \ No newline at end of file diff --git a/docs/9x_intro.pdf b/docs/9x_intro.pdf new file mode 100644 index 0000000..b888313 Binary files /dev/null and b/docs/9x_intro.pdf differ diff --git a/docs/9x_intro.txt b/docs/9x_intro.txt new file mode 100644 index 0000000..187083f --- /dev/null +++ b/docs/9x_intro.txt @@ -0,0 +1,361 @@ +1 INTRODUCTION + Figure 1-0. + Table 1-0. + Listing 1-0. + + + + +Purpose + The ADSP-219x DSP Instruction Set Reference provides assembly syntax + information for the ADSP-219x Digital Signal Processor (DSP). The syn- + tax descriptions cover instructions that execute within the DSP’s processor + core (processing elements, program sequencer, and data address genera- + tors). For architecture and design information on the DSP, see the + ADSP-219x/2191 DSP Hardware Reference. + + +Audience + DSP system designers and programmers who are familiar with signal pro- + cessing concepts are the primary audience for this manual. This manual + assumes that the audience has a working knowledge of microcomputer + technology and DSP-related mathematics. + DSP system designers and programmers who are unfamiliar with signal + processing can use this manual, but should supplement this manual with + other texts, describing DSP techniques. + All readers, particularly programmers, should refer to the DSP’s develop- + ment tools documentation for software development information. For + additional suggested reading, see “For More Information About Analog + Products” on page 1-6. + + + + + ADSP-219x DSP Instruction Set Reference 1-1 + Contents Overview + + + + +Contents Overview + This reference presents instruction information organized by the type of + the instruction. Instruction types relate to the machine language opcode + for the instruction. On this DSP, the opcodes categorize the instructions + by the portions of the DSP architecture that execute the instructions. The + following chapters cover the different types of instructions: + • “Instruction Set Summary” on page 2-1—This chapter provides a + syntax summary of all instructions and describes the conventions + that are used on the instruction reference pages. + • “ALU Instructions” on page 3-1—These instruction specify opera- + tions that occur in the DSP’s ALU. + • “MAC Instructions” on page 4-1—These instructions specify oper- + ations that occur in the DSP’s Multiply–Accumulator. + • “Shifter Instructions” on page 5-1—These instructions specify + operations that occur in the DSP’s Shifter. + • “Multifunction Instructions” on page 6-1—These instructions + specify parallel, single-cycle operations. + • “Data Move Instructions” on page 7-1—These instructions specify + memory and register access operations. + • “Program Flow Instructions” on page 8-1—These instructions spec- + ify program sequencer operations. + • “Instruction Opcodes” on page 9-1—This chapter lists the instruc- + tion encoding fields for all instructions. + Each of the DSP’s instructions is specified in this text. The reference page + for an instruction shows the syntax of the instruction, describes its func- + tion, gives one or two assembly-language examples, and identifies fields of + its opcode. The instructions are referred to by type, ranging from 1 to 37. + + + + +1-2 ADSP-219x DSP Instruction Set Reference + Introduction + + + + + These types correspond to the opcodes that ADSP-219x DSPs recognize, + but are for reference only and have no bearing on programming. + Some instructions have more than one syntactical form; for example, + instruction “Type 9: Compute” on page 9-27 has many distinct forms. + Many instructions can be conditional. These instructions are prefaced by + IF COND; for example: + + If COND compute; + + In a conditional instruction, the execution of the entire instruction is + based on the specified condition. + + +Development Tools + The ADSP-219x is supported by VisualDSP®, an easy-to-use project + management environment, comprised of an Integrated Development + Environment (IDE) and Debugger. VisualDSP lets you manage projects + from start to finish from within a single, integrated interface. Because the + project development and debug environments are integrated, you can + move easily between editing, building, and debugging activities. + Flexible Project Management. The IDE provides flexible project manage- + ment for the development of DSP applications. The IDE includes access + to all the activities necessary to create and debug DSP projects. You can + create or modify source files or view listing or map files with the IDE Edi- + tor. This powerful Editor is part of the IDE and includes multiple + language syntax highlighting, OLE drag and drop, bookmarks, and stan- + dard editing operations such as undo/redo, find/replace, copy/paste/cut, + and goto. + Also, the IDE includes access to the C Compiler, C Runtime Library, + Assembler, Linker, Loader, Simulator, and Splitter. You specify options + for these Tools through Property Page dialogs. Property Page dialogs are + easy to use, and make configuring, changing, and managing your projects + + + + ADSP-219x DSP Instruction Set Reference 1-3 + Development Tools + + + + + simple. These options control how the tools process inputs and generate + outputs, and have a one-to-one correspondence to the tools’ command + line switches. You can define these options once, or modify them to meet + changing development needs. You can also access the Tools from the oper- + ating system command line if you choose. + Greatly Reduced Debugging Time. The Debugger has an easy-to-use, + common interface for all processor simulators and emulators available + through Analog Devices and third parties or custom developments. The + Debugger has many features that greatly reduce debugging time. You can + view C source interspersed with the resulting Assembly code. You can pro- + file execution of a range of instructions in a program; set simulated watch + points on hardware and software registers, program and data memory; and + trace instruction execution and memory accesses. These features enable + you to correct coding errors, identify bottlenecks, and examine DSP per- + formance. You can use the custom register option to select any + combination of registers to view in a single window. The Debugger can + also generate inputs, outputs, and interrupts so you can simulate real + world application conditions. + Software Development Tools. Software Development Tools, which sup- + port the ADSP-219x Family, allow you to develop applications that take + full advantage of the DSP architecture, including shared memory and + memory overlays. Software Development Tools include C Compiler, C + Runtime Library, DSP and Math Libraries, Assembler, Linker, Loader, + Simulator, and Splitter. + C Compiler & Assembler. The C Compiler generates efficient code that is + optimized for both code density and execution time. The C Compiler + allows you to include Assembly language statements inline. Because of + this, you can program in C and still use Assembly for time-critical loops. + You can also use pretested Math, DSP, and C Runtime Library routines to + help shorten your time to market. The ADSP-219x Family Assembly lan- + guage is based on an algebraic syntax that is easy to learn, program, and + + + + +1-4 ADSP-219x DSP Instruction Set Reference + Introduction + + + + +debug. The add instruction, for example, is written in the same manner as +the actual equation (for example, AR = AX0 + AY0;). +Linker & Loader. The Linker provides flexible system definition through +Linker Description Files (.LDF). In a single LDF, you can define different +types of executables for a single or multiprocessor system. The Linker +resolves symbols over multiple executables, maximizes memory use, and +easily shares common code among multiple processors. The Loader sup- +ports creation of host (8- or 16-bit) port, SPI port, UART port, and +PROM boot images. Along with the Linker, the Loader allows a variety of +system configurations with smaller code and faster boot time. +Simulator. The Simulator is a cycle-accurate, instruction-level simulator +— allowing you to simulate your application in real time. +3rd-Party Extensible. The VisualDSP environment enables third-party +companies to add value using Analog Devices’ published set of Applica- +tion Programming Interfaces (API). Third party products—runtime +operating systems, emulators, high-level language compilers, multiproces- +sor hardware —can interface seamlessly with VisualDSP thereby +simplifying the tools integration task. VisualDSP follows the COM API +format. Two API tools, Target Wizard and API Tester, are also available +for use with the API set. These tools help speed the time-to-market for +vendor products. Target Wizard builds the programming shell based on +API features the vendor requires. The API tester exercises the individual +features independently of VisualDSP. Third parties can use a subset of +these APIs that meets their application needs. The interfaces are fully sup- +ported and backward compatible. +Further details and ordering information are available in the VisualDSP +Development Tools data sheet. This data sheet can be requested from any +Analog Devices sales office or distributor. + + + + + ADSP-219x DSP Instruction Set Reference 1-5 + For More Information About Analog Products + + + + +For More Information About Analog +Products + Analog Devices is online on the internet at http://www.analog.com. Our + Web pages provide information on the company and products, including + access to technical information and documentation, product overviews, + and product announcements. + You may also obtain additional information about Analog Devices and its + products in any of the following ways: + • Visit our World Wide Web site at www.analog.com + • FAX questions or requests for information to 1(781)461-3010. + • Access the Computer Products Division File Transfer Protocol + (FTP) site at ftp ftp.analog.com or ftp 137.71.23.21 or + ftp://ftp.analog.com. + + + +For Technical or Customer Support + You can reach our Customer Support group in the following ways: + • E-mail questions to dsp.support@analog.com or + dsp.europe@analog.com (European customer support) + + • Telex questions to 924491, TWX:710/394-6577 + • Cable questions to ANALOG NORWOODMASS + • Contact your local ADI sales office or an authorized ADI distributor + + + + +1-6 ADSP-219x DSP Instruction Set Reference + Introduction + + + + + • Send questions by mail to: + Analog Devices, Inc. + DSP Division + One Technology Way + P.O. Box 9106 + Norwood, MA 02062-9106 + USA + + + +What’s New in This Manual + This is the preliminary edition of the ADSP-219x DSP Instruction Set + Reference. Summaries of changes between editions will start with the next + edition. + + +Related Documents + For more information about Analog Devices DSPs and development + products, see the following documents: + • ADSP-2191 DSP Microcomputer Data Sheet + • ADSP-219x/2191 DSP Hardware Reference + • Getting Started Guide for VisualDSP & ADSP-219x Family DSPs + • VisualDSP User's Guide for ADSP-219x Family DSPs + • C Compiler & Library Manual for ADSP-219x Family DSPs + • Assembler Manual for ADSP-219x Family DSPs + • Linker & Utilities Manual for ADSP-219x Family DSPs + All the manuals are included in the software distribution CD-ROM. To + access these manuals, use the Help Topics command in the VisualDSP + environment’s Help menu and select the Online Manuals book. From this + + + + ADSP-219x DSP Instruction Set Reference 1-7 + Conventions + + + + + Help topic, you can open any of the manuals, which are in Adobe Acrobat + PDF format. + + +Conventions + The following are conventions that apply to all chapters. Note that addi- + tional conventions, which apply only to specific chapters, appear + throughout this document. + + Table 1-1. Instruction set notation + + Notation Meaning + + UPPERCASE Explicit syntax—assembler keyword. (The assembler is case- + insensitive.) + + ; A semicolon terminates an instruction line. + + , A comma separates multiple, parallel instructions in the same + instruction line. + + // single line comment // or /* */ indicate comments or remarks that explain program code, + /* multi line comment */ but that the assembler ignores. For more details, see the Assembler + Manual for ADSP-219x Family DSPs. + + | option1 | You must choose one of the items enclosed within two vertical bars. + | option2 | + + [ (DB) ] Brackets enclose an optional instruction component. The option’s + syntax includes everything within the brackets, as shown. In this + case, (DB) is the delayed branch option. + + Denotes an immediate value (data or address) of # bits. + + + COND Denotes a status condition. + + + + +1-8 ADSP-219x DSP Instruction Set Reference + Introduction + + + + +Table 1-1. Instruction set notation (Cont’d) + +Notation Meaning + + TERM Denotes a loop termination condition. For details, see “Type 11: Do + ··· Until” on page 9-34. + + Dreg Denotes an unrestricted (Group 0) data register used as either an x + or y-input operand. For details, see “Core Registers” on page 7-2. + + XOP Denotes a restricted data register used for the x-input operand in a + compute instruction. For details, see “Input Registers” on page 3-2. + + YOP Denotes a restricted data register used for the y-input operand in a + compute operation. For details, see “Input Registers” on page 3-2. + + Ireg DAG address register. Denotes an index register (I0–I7). + + Mreg DAG address register. Denotes a modify register (M0–M7). + + Lreg DAG address register. Denotes a length register (L0–L7). + + Breg DAG address register. Denotes a base register (B0–B7). + + (Ireg + Mreg) Indirect addressing mode. Denotes premodify addressing with no + update. Same as (Mreg, Ireg) syntax. + + (Ireg += Mreg) Indirect addressing mode. Denotes postmodify addressing with + update. Same as (Ireg, Mreg) syntax. + + 0x Denotes number in hexidecimal format (0xFFFF). + + h# Denotes number in hexidecimal format (h#FFFF). + + b# Denotes number in binary format (b#0001000100010001). + + + + + ADSP-219x DSP Instruction Set Reference 1-9 + Conventions + + + + +1-10 ADSP-219x DSP Instruction Set Reference + \ No newline at end of file diff --git a/docs/9x_is_IX.pdf b/docs/9x_is_IX.pdf new file mode 100644 index 0000000..daff196 Binary files /dev/null and b/docs/9x_is_IX.pdf differ diff --git a/docs/9x_is_TC.pdf b/docs/9x_is_TC.pdf new file mode 100644 index 0000000..3746e4c Binary files /dev/null and b/docs/9x_is_TC.pdf differ diff --git a/docs/9x_iset.pdf b/docs/9x_iset.pdf new file mode 100644 index 0000000..588064a Binary files /dev/null and b/docs/9x_iset.pdf differ diff --git a/docs/9x_iset.txt b/docs/9x_iset.txt new file mode 100644 index 0000000..5f20fa1 --- /dev/null +++ b/docs/9x_iset.txt @@ -0,0 +1,1021 @@ +2 INSTRUCTION SET SUMMARY + Figure 2-0. + Table 2-0. + Listing 2-0. + + + + This chapter provides a summary of the instructions in the ADSP-219x + DSP’s instruction set. Chapters 3 through 9 describe these instructions in + more detail as follows: + • “ALU Instructions” on page 3-1 + • “MAC Instructions” on page 4-1 + • “Shifter Instructions” on page 5-1 + • “Multifunction Instructions” on page 6-1 + • “Data Move Instructions” on page 7-1 + • “Program Flow Instructions” on page 8-1 + • “Instruction Opcodes” on page 9-1 + Also, this chapter identifies mnemonics for using DSP registers, bits, and + operating conditions. This information appears in the following + summaries: + • “Core Registers Summary” on page 2-3 + • “Arithmetic Status (ASTAT) Register” on page 2-5 + • “Condition Code (CCODE) Register” on page 2-6 + • “Interrupt Control (ICNTL) Register” on page 2-8 + • “Interrupt Mask (IMASK) & Latch (IRPTL) Registers” on page + 2-10 + + + + ADSP-219x Instruction Set Reference 2-1 + Instruction Set Summary + + + + + • “Mode Status (MSTAT) Register” on page 2-11 + • “Stack Status (SSTAT) Register” on page 2-14 + • “Condition Codes Summary” on page 2-15 + • “ALU Instructions” on page 2-19 + • “Multiplier Instructions” on page 2-20 + • “Shifter Instructions” on page 2-21 + • “Multifunction Instructions” on page 2-24 + • “Data Move Instructions” on page 2-22 + • “Program Flow Instructions” on page 2-23 + For information on instruction reference notation, see “Conventions” on + page 1-8. + + + + +2-2 ADSP-219x Instruction Set Reference + Core Registers Summary + + + + +Core Registers Summary + The DSP has three categories of registers: core registers, system control + registers, and I/O registers. Table 2-1 lists and describes the DSP’s core + registers. For information about system control and I/O registers, see the + ADSP-219x/2191 DSP Hardware Reference. + + Table 2-1. Core registers + +Type Registers Function + +ALU data AX0, AX1, AY0, AY1, 16-bit data registers (X and Y) provide input + AR, AF for ALU, multiplier, and shifter operations. + AR and AF are ALU result and feedback regis- +Multiplier data MX0, MX1, MY0, MY1, + ters. MR and SR are multiplier results and + MR0, MR1, MR2 + feedback registers. SR also is the shifter results + register. +Shifter data SI, SE, SB, SR0, SR1, SR2 + In this text, the word Dreg denotes unre- + stricted use of data registers as a data register + file, while the words XOP and YOP denote + restricted use. + The data registers (except AF, SE, and SB) + serve as a register file, for unconditional, sin- + gle-function instructions. + +DAG address I0, I1, I2, I3 DAG1 index registers + I4, I5, I6, I7 DAG2 index registers + + M0, M1, M2, M3 DAG1 modify registers + M4, M5, M6, M7 DAG2 modify registers + + L0, L1, L2, L3 DAG1 length registers + L4, L5, L6, L7 DAG2 length registers + +System control B0, B1, B2, B3, B4, B5, DAG1 base address registers (B0-3), DAG2 + B6, B7, SYSCTL, CACTL base address registers (B4-7), System control, + Cache control + + + + + ADSP-219x Instruction Set Reference 2-3 + Instruction Set Summary + + + + + Table 2-1. Core registers + +Type Registers Function + + Program flow CCODE Software condition register + LPSTACKA Loop PC stack A register, 16 address LSBs + LPSTACKP Loop PC stack P register, 8 address MSBs + STACKA PC stack A register, 16 address LSBs + STACKP PC stack P register, 8 address MSBs + + Interrupt ICNTL Interrupt control register + IMASK Interrupt mask register + IRPTL Interrupt latch register + + Status ASTAT Arithmetic status flags + MSTAT Mode control and status flags + SSTAT (read-only) System status + + Page DMPG1 DAG1 page register, 8 address MSBs + DMPG2 DAG2 page register, 8 address MSBs + IJPG Indirect jump page register, 8 address MSBs + IOPG I/O page register, 8 address MSBs + + Bus exchange PX Holds eight LSBs of 24-bit memory data for + transfers between memory and data registers + only. + + Shifter SE Shifter exponent register + SB Shifter block exponent register + + + + +2-4 ADSP-219x Instruction Set Reference + Arithmetic Status (ASTAT) Register + + + + +Arithmetic Status (ASTAT) Register + The DSP updates the status bits in ASTAT, indicating the status of the + most recent ALU, multiplier, or shifter operation. + + Table 2-2. ASTAT register bit definitions + +Bit Name Description + +0 AZ ALU result zero. Logical NOR of all bits written to the ALU result register + (AR) or ALU feedback register (AF). + 0 = ALU output ≠ 0 + 1 = ALU output = 0 + +1 AN ALU result negative. Sign of the value written to the ALU result register + (AR) or ALU feedback register (AF). + 0 = ALU output positive (+) + 1 = ALU output negative (−) + +2 AV ALU result overflow. + 0 = No overflow + 1 = Overflow + +3 AC ALU result carry. + 0 = No carry + 1 = Carry + +4 AS ALU x input sign. Sign bit of the ALU x-input operand; set by the ABS + instruction only. + 0 = Positive (+) + 1 = Negative (−) + + + + + ADSP-219x Instruction Set Reference 2-5 + Instruction Set Summary + + + + + Table 2-2. ASTAT register bit definitions (Cont’d) + +Bit Name Description + + 5 AQ ALU quotient. Sign of the resulting quotient; set by the DIVS or DIVQ + instructions. + 0 = Positive (+) + 1 = Negative (−) + + 6 MV Multiplier overflow. Records overflow/underflow condition for MR result + register. + 0 = No overflow or underflow + 1 = Overflow or underflow + + 7 SS Shifter input sign. Sign of the shifter input operand. + 0 = Positive (+) + 1 = Negative (−) + + 8 SV Shifter overflow. Records overflow/underflow condition for SR result reg- + ister. + 0 = No overflow or underflow + 1 = Overflow or underflow + + + +Condition Code (CCODE) Register + Using the CCODE register, conditional instructions may base execution + on a comparison of the CCODE value (user-selected) and the SWCOND + condition (DSP status). The CCODE register holds a value between 0x0 + and 0xF, which the instruction tests against when the conditional instruc- + + + + +2-6 ADSP-219x Instruction Set Reference + Condition Code (CCODE) Register + + + + + tion uses SWCOND or NOT SWCOND. Note that the CCODE register + has a one cycle effect latency. + + Table 2-3. CCODE register bit definitions + +CCODE Software Condition + +Value SWCOND (1010) NOT SWCOND (1011) + +0x00 PF0 pin high PF0 pin low + +0x01 PF1 pin high PF1 pin low + +0x02 PF2 pin high PF2 pin low + +0x03 PF3 pin high PF3 pin low + +0x04 PF4 pin high PF4 pin low + +0x05 PF5 pin high PF5 pin low + +0x06 PF6 pin high PF6 pin low + +0x07 PF7 pin high PF7 pin low + +0x08 AS NOT AS + +0x09 SV NOT SV + +0x0A PF8 pin high PF8 pin low + +0x0B PF9 pin high PF9 pin low + +0x0C PF10 pin high PF10 pin low + +0x0D PF11 pin high PF11 pin low + +0x0E PF12 pin high PF12 pin low + +0x0F PF13 pin high PF13 pin low + + + + + ADSP-219x Instruction Set Reference 2-7 + Instruction Set Summary + + + + +Interrupt Control (ICNTL) Register + Table 2-4. ICNTL register bit definitions + +Bit Name Description + + 0 reserved write 0 + + 1 reserved write 0 + + 2 reserved write 0 + + 3 reserved write 0 + + 4 INE Interrupt nesting mode enable. + 0 = Disabled + 1 = Enabled + + 5 GIE Global interrupt enable. + 0 = Disabled + 1 = Enabled + + 6 reserved write 0 + + 7 BIASRND MAC biased rounding mode. + 0 = Disabled + 1 = Enabled + + 8-9 reserved write 0 + + 10 PCSTKE PC stack interrupt enable. + 0 = Disabled + 1 = Enabled + + + + +2-8 ADSP-219x Instruction Set Reference + Interrupt Control (ICNTL) Register + + + + + Table 2-4. ICNTL register bit definitions (Cont’d) + +Bit Name Description + +11 EMUCNTE Emulator cycle counter interrupt enable. + 0 = Disabled + 1 = Enabled + +12-15 reserved write 0 + + + + + ADSP-219x Instruction Set Reference 2-9 + Instruction Set Summary + + + + +Interrupt Mask (IMASK) & Latch (IRPTL) Registers + Table 2-5. IMASK & IRPTL Registers Bit Definitions + +Bit Name Description + + 0 EMU Emulator. Nonmaskable. Highest priority + + 1 PWDN Powerdown. Maskable only with GIE bit in ICNTL. + + 2 SSTEP Single-step (during emulation) + + 3 STACK Stack interrupt. Generated from any of the following stack status + states: (if PCSTKE enabled) PC stack is pushed or popped and hits + high-water mark, any stack overflows, or the status or PC stacks under- + flow. + + 4 User-defined + + 5 User-defined + + 6 User-defined + + 7 User-defined + + 8 User-defined + + 9 User-defined + + 10 User-defined + + 11 User-defined + + 12 User-defined + + 13 User-defined + + 14 User-defined + + 15 User-defined Lowest priority + + + + +2-10 ADSP-219x Instruction Set Reference + Mode Status (MSTAT) Register + + + + +Mode Status (MSTAT) Register + Table 2-6. MSTAT register bit definitions + +Bit Name Description + +0 SEC_REG Secondary data registers. + or Determines which set of data registers is currently active. + SR 0 = Deactivate secondary set of data registers (default). + Primary register set (set that is active at reset) enabled and + used for normal operation; secondary register set disabled. + 1 = Activate secondary set of data registers. + Secondary register set enabled and used for alternate DSP + context (for example, interrupt servicing); primary register + set disabled, current contents preserved. + For details, see “Switching Contexts” on page 8-16. + +1 BIT_REV Bit-reversed address output. + or Enables and disables bit-reversed addressing on DAG1 index regis- + ters only. + BR + 0 = Disable + 1 = Enable + For details, see “Bit-Reversed Addressing” on page 7-17. + + + + + ADSP-219x Instruction Set Reference 2-11 + Instruction Set Summary + + + + + Table 2-6. MSTAT register bit definitions (Cont’d) + +Bit Name Description + + 2 AV_LATCH ALU overflow latch mode. Determines how the ALU overflow flag, + AV, gets cleared. + or + 0 = Disable + OL + Once an ALU overflow occurs and sets the AV bit in the + ASTAT register, the AV bit remains set until explicitly + cleared or is cleared by a subsequent ALU operation that does + not generate an overflow. + 1 = Enable + Once an ALU overflow occurs and sets the AV bit in the + ASTAT register, the AV bit remains set until the application + explicitly clears it. For details on clearing the AV bit, see “Bit + Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT” on + page 3-18 and “Register to Register Move” on page 7-22. + + 3 AR_SAT ALU saturation mode. + or For signed values, determines whether ALU AR results that over- + flowed or underflowed are saturated or not. Enables or disables sat- + AS + uration for all subsequent ALU operations. + 0 = Disable + AR results remain unsaturated and return as is. + 1 = Enable + AR results saturated according to the state of the AV and AC + status flags in ASTAT. + AV AC AR register + 0 0 ALU output + 0 1 ALU output + 1 0 0x7FFF + 1 1 0x8000 + Only the results written to the AR register are saturated. If results + are written to the AF register, wraparound occurs, but the AV and + AC flags reflect the saturated result. + + + + +2-12 ADSP-219x Instruction Set Reference + Mode Status (MSTAT) Register + + + + + Table 2-6. MSTAT register bit definitions (Cont’d) + +Bit Name Description + +4 M_MODE MAC result mode. + or Determines the numeric format of multiplier operands. For all + MAC operations, the multiplier adjusts the format of the result + MM + according to the selected mode. + 0 = Fractional mode, 1.15 format. + 1 = Integer mode, 16.0 format. + For details, see “Data Format Options” on page 4-3. + +5 TIMER Timer enable. + or Starts and stops the timer counter. + TI 0 = Stops the timer count. + 1 = Starts the timer count. + For details on timer operation, see the ADSP-219x/2191 DSP + Hardware Reference. + +6 SEC_DAG Secondary DAG registers. + or Determines which set of DAG address registers is currently active. + SD 0 = Primary registers. + 1 = Secondary registers. + For details, see “Secondary DAG Registers” on page 7-8 and + “Switching Contexts” on page 8-16. + + + + + ADSP-219x Instruction Set Reference 2-13 + Instruction Set Summary + + + + +Stack Status (SSTAT) Register + Table 2-7. SSTAT register bit definitions + +Bit Name Description + + 0 PCSTKEMPTY PC stack empty. + or 0 = PC stack contains at least one pushed address. + PCE 1 = PC stack is empty. + + 1 PCSTKFULL PC stack full. + or 0 = PC stack contains at least one empty location. + PCF 1 = PC stack is full. + + 2 PCSTKLVL PC stack level. + or 0 = PC stack contains between 3 and 28 pushed addresses. + PCL 1 = PC stack is at or above the high-water mark (28 pushed + addresses), or it is at or below the low-water mark (3 + pushed addresses). + + 3 Reserved + + 4 LPSTKEMPTY Loop stack empty. + or 0 = Loop stack contains at least one pushed address. + LSE 1 = Loop stack is empty. + + 5 LPSTKFULL Loop stack full. + or 0 = Loop stack contains at least one empty location. + LSF 1 = Loop stack is full. + + + + +2-14 ADSP-219x Instruction Set Reference + Condition Codes Summary + + + + + Table 2-7. SSTAT register bit definitions (Cont’d) + +Bit Name Description + +6 STSSTKEMPTY Status stack empty. + or 0 = Status stack contains at least one pushed status. + SSE 1 = Status stack is empty. + +7 STKOVERFLOW Stacks overflowed. + or 0 = Overflow/underflow has not occurred. + SOV 1 = At least one of the stacks (PC, loop, counter, status) has + overflowed, or the PC or status stack has underflowed. + This bit cleared only on reset. Loop stack underflow is + not detected because it occurs only as a result of a POP + LOOP operation. + + + +Condition Codes Summary + Table 2-8. Condition codes summary + +Code Condition Description + +0000 EQ Equal to zero (= 0). + +0001 NE Not equal to zero (≠ 0). + +0010 GT Greater than zero (> 0). + +0011 LE Less than or equal to zero (≤ 0). + +0100 LT Less than zero (< 0). + +0101 GE Greater than or equal to zero (≥ 0). + +0110 AV ALU overflow. + +0111 NOT AV Not ALU overflow. + + + + + ADSP-219x Instruction Set Reference 2-15 + Instruction Set Summary + + + + + Table 2-8. Condition codes summary (Cont’d) + +Code Condition Description + + 1000 AC ALU carry. + + 1001 NOT AC Not ALU carry. + + 1010 SWCOND SWCOND (based on CCODE register condition). (For + CCODE details, see Table 2-3 on page 2-7.) + + 1011 NOT SWCOND Not SWCOND (based on CCODE register condition). + (For CCODE details, see Table 2-3 on page 2-7.) + + 1100 MV MAC overflow. + + 1101 NOT MV Not MAC overflow. + + 1110 NOT CE Counter not expired. + + 1111 TRUE Always true. + + + + +2-16 ADSP-219x Instruction Set Reference + Condition Codes Summary + + + + +Instruction Summary + The conventions for ADSP-219x instruction syntax descriptions appear in + Table 2-9. Other parts of the instruction syntax and opcode information + also appear in this section. Following this table, the following sections + provide summaries of the DSP’s instruction set: + • “ALU Instructions” on page 2-19 + • “Multiplier Instructions” on page 2-20 + • “Shifter Instructions” on page 2-21 + • “Data Move Instructions” on page 2-22 + • “Program Flow Instructions” on page 2-23 + • “Multifunction Instructions” on page 2-24 + For a list of instructions by types, see “Instruction Opcodes” on page 9-1. + + Table 2-9. Instruction Set Notation + +Notation Meaning + +UPPERCASE Explicit syntax—assembler keyword (notation only; assembler is + case-insensitive and lowercase is the preferred programming conven- + tion) + +; Semicolon—instruction terminator + +, Comma—separates multiple optional items within vertical bars + or separates parallel operations in multifunction instructions + +| option1, option2 | Vertical bars—List of options separated with commas (choose one) + +[optional] Square brackets—enclose optional part of instruction + +Compute ALU, multiplier, shifter or multifunction operation + + + + + ADSP-219x Instruction Set Reference 2-17 + Instruction Set Summary + + + + + Table 2-9. Instruction Set Notation (Cont’d) + +Notation Meaning + + ALU, MAC, SHIFT ALU, multiplier, or shifter operation + + Cond Status condition + + Term Loop termination condition + + Reg Any register from register groups Reg0, Reg1, Reg2, or Reg3 + + Dreg Data register (register file) registers—subset of Reg0 registers + + Ireg Any DAG I register + + Mreg Any DAG M register + + Lreg Any DAG L register + + Ia I3-I0 (DAG1 index register) + + Mb M3-M0 (DAG1 modify register) + + Ic I7-I4 (DAG2 index register) + + Md M7-M4 (DAG2 modify register) + + n-bit immediate data value + + n-bit immediate modify value + + n-bit immediate address value + + n-bit immediate PC-relative address value + + Const constant value; For valid constant values, see Table 3-1 on page 3-3. + + C carry bit + + (DB) Delayed branch + + + + +2-18 ADSP-219x Instruction Set Reference + ALU Instructions + + + + +ALU Instructions + Table 2-10. Summary of ALU instructions + +Instruction Type Details + +|AR, AF| = Dreg1 + |Dreg2, Dreg2 + C, C |; 9, 9a page 3-5 + +[IF Cond] |AR, AF| = Xop + |Yop, Yop + C, C, Const, Const + C|; 9 page 3-5 + +|AR, AF| = Dreg1 − |Dreg2, Dreg2 + C −1, +C −1|; 9, 9a page 3-8 + +[IF Cond] |AR, AF| = Xop − |Yop, Yop+C−1, +C−1, Const, Const +C −1|; 9 page 3-8 + +|AR, AF| = Dreg2 − |Dreg1, Dreg1 + C −1|; 9, 9a page 3-12 + +[IF Cond] |AR, AF| = Yop − |Xop, Xop+C−1|; 9 page 3-12 + +[IF Cond] |AR, AF| = − |Xop + C −1, Xop + Const, Xop + Const + C −1|; 9 page 3-12 + +|AR, AF| = Dreg1 |AND, OR, XOR| Dreg2; 9, 9a page 3-15 + +[IF Cond] |AR, AF| = Xop |AND, OR, XOR| |Yop, Const|; 9 page 3-15 + +[IF Cond] |AR, AF| = |TSTBIT, SETBIT, CLRBIT, TGLBIT| n of Xop; 9, 9a page 3-18 + +|AR, AF| = PASS |Dreg1, Dreg2, Const|; 9, 9a page 3-20 + +|AR, AF| = PASS 0; 9, 9a page 3-20 + +[IF Cond] |AR, AF| = PASS |Xop, Yop, Const|; 9 page 3-20 + +|AR, AF| = NOT |Dreg|; 9, 9a page 3-23 + +[IF Cond] |AR, AF| = NOT |Xop, Yop|; 9 page 3-23 + +|AR, AF| = ABS Dreg; 9, 9a page 3-26 + +[IF Cond] |AR, AF| = ABS Xop; 9 page 3-26 + + + + + ADSP-219x Instruction Set Reference 2-19 + Instruction Set Summary + + + + + Table 2-10. Summary of ALU instructions (Cont’d) + +Instruction Type Details + + |AR, AF| = Dreg +1; 9, 9a page 3-29 + + [IF Cond] |AR, AF| = Yop +1; 9 page 3-29 + + |AR, AF| = Dreg −1; 9, 9a page 3-32 + + [IF Cond] |AR, AF| = Yop −1; 9 page 3-32 + + DIVS Yop, Xop; 24 page 3-35 + + DIVQ Xop; 23 page 3-35 + + NONE = ALU (Xop, Yop); 8 page 3-44 + + + +Multiplier Instructions + Table 2-11. Summary of multiplier instructions + +Instruction Type Details + + |MR, SR| = Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; 9a page 4-8 + + [IF Cond] |MR, SR| = Xop * Yop [(|RND, SS, SU, US, UU|)]; 9 page 4-8 + + [IF Cond] |MR, SR| = Yop * Xop [(|RND, SS, SU, US, UU|)]; 9 page 4-8 + + |MR, SR| = |MR, SR| + Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; 9a page 4-11 + + [IF Cond]|MR, SR| = |MR, SR| + Xop * Yop [(|RND, SS, SU, US, UU|)]; 9 page 4-11 + + [IF Cond] |MR, SR| = |MR, SR| + Yop * Xop [(|RND, SS, SU, US, UU|)]; 9 page 4-11 + + |MR, SR| = |MR, SR| − Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; 9a page 4-14 + + [IF Cond] |MR, SR| = |MR, SR| − Xop * Yop [(|RND, SS, SU, US, UU|)]; 9 page 4-14 + + + + +2-20 ADSP-219x Instruction Set Reference + Shifter Instructions + + + + + Table 2-11. Summary of multiplier instructions (Cont’d) + +Instruction Type Details + +[IF Cond] |MR, SR| = |MR, SR| − Yop * Xop [(|RND, SS, SU, US, UU|)]; 9 page 4-14 + +[IF Cond] |MR, SR| = 0; 9 page 4-17 + +[IF Cond] MR = MR [(RND)]; 9 page 4-19 +[IF Cond] SR = SR [(RND)]; + +SAT MR; 25 page 4-21 +SAT SR; + + + +Shifter Instructions + Table 2-12. Summary of shifter instructions + +Instruction Type Details + +[IF Cond] SR = [SR OR] ASHIFT Dreg [(|HI, LO|)]; 16 page 5-6 + +SR = [SR OR] ASHIFT BY [(|HI, LO|)]; 15 page 5-8 + +[IF Cond] SR = [SR OR] LSHIFT Dreg [(|HI, LO|)]; 16 page 5-10 + +SR = [SR OR] LSHIFT BY [(|HI, LO|)]; 15 page 5-12 + +[IF Cond] SR = [SR OR] NORM Dreg [(|HI, LO|)]; 16 page 5-14 + +[IF Cond] SE = EXP Dreg [(|HIX, HI, LO|)]; 16 page 5-20 + +[IF Cond] SB = EXPADJ Dreg; 16 page 5-23 + + + + + ADSP-219x Instruction Set Reference 2-21 + Instruction Set Summary + + + + +Data Move Instructions + Table 2-13. Summary of data move instructions + +Instruction Type Details + + Reg = Reg; 17 page 7-22 + + |DM() = |Dreg, Ireg, Mreg|; 3 page 7-24 + + |Dreg, Ireg, Mreg| = |DM()|; 3 page 7-24 + + |, , | = ; 6, 7, 7A page 7-27 + + Reg3 = ; 33 page 7-27 + + |DM(Ia += Mb), DM(Ic += Md)| = Reg; 32 page 7-30 + + Reg = |DM(Ia += Mb), DM(Ic += Md)|; 32 page 7-30 + + |DM(Ia + Mb), DM(Ic + Md)| = Reg; 32 page 7-34 + + Reg = |DM (Ia + Mb), DM (Ic + Md)|; 32 page 7-34 + + |PM(Ia += Mb), PM(Ic += Md)| = Reg; 32 page 7-37 + + Reg = |PM(Ia += Mb), PM(Ic += Md)|; 32 page 7-37 + + |PM(Ia + Mb), PM(Ic + Md)| = Reg; 32 page 7-41 + + Reg = |PM(Ia + Mb), PM(Ic + Md)|; 32 page 7-41 + + DM(Ireg1 += Mreg1) = |Ireg2, Mreg2, Lreg2|, |Ireg2, Mreg2, Lreg2| = Ireg1; 32A page 7-45 + + Dreg = DM(Ireg += ); 29 page 7-49 + + DM(Ireg += ) = Dreg; 29 page 7-49 + + Dreg = DM(Ireg + ); 29 page 7-52 + + + + +2-22 ADSP-219x Instruction Set Reference + Program Flow Instructions + + + + + Table 2-13. Summary of data move instructions (Cont’d) + +Instruction Type Details + +DM(Ireg + ) = Dreg; 29 page 7-52 + +|DM(Ia += Mb), DM (Ic += Md)| = ; 22 page 7-55 + +|PM (Ia += Mb), PM (Ic += Md)| = :24; 22A page 7-57 + +IO() = Dreg; 34 page 7-59 + +Dreg = IO (); 34 page 7-59 + +REG() = Dreg; 35 page 7-61 + +Dreg = REG(); 35 page 7-61 + +|MODIFY (Ia += Mb), MODIFY (Ic += Md)|; 21 page 7-63 + +MODIFY (Ireg += ); 21A page 7-65 + + + +Program Flow Instructions + Table 2-14. Summary of program flow instructions + +Instruction Type Details + +DO UNTIL [CE, FOREVER]; 11 page 8-22 + +[IF Cond] JUMP [(DB)]; 10 page 8-27 + +CALL [(DB)]; 10a page 8-30 + +JUMP [(DB)]; 10a page 8-34 + +[IF Cond] CALL ; 36 page 8-37 + +[IF Cond] JUMP ; 36 page 8-40 + + + + + ADSP-219x Instruction Set Reference 2-23 + Instruction Set Summary + + + + + Table 2-14. Summary of program flow instructions (Cont’d) + +Instruction Type Details + + [IF Cond] CALL [(DB)]; 19 page 8-42 + + [IF Cond] JUMP [(DB)]; 19 page 8-45 + + [IF Cond] RTI [(DB)]; 20 page 8-48 + + [IF Cond] RTS [(DB)]; 20 page 8-52 + + PUSH |PC, LOOP, STS|; 26 page 8-55 + + POP |PC, LOOP, STS|; 26 page 8-55 + + FLUSH CACHE; 26 page 8-61 + + SETINT ; 37 page 8-62 + + CLRINT ; 37 page 8-64 + + NOP; 30 page 8-66 + + IDLE; 31 page 8-67 + + ENA | TI, MM, AS, OL, BR, SR, BSR, INT | ; 18 page 8-69 + + DIS | TI, MM, AS, OL, BR, SR, BSR, INT | ; 18 page 8-69 + + + +Multifunction Instructions + Table 2-15. Summary of multifunction instructions + +Instruction Type Details + + |, |, Xop = DM(Ia += Mb), Yop = PM(Ic += Md); 1 page 6-3 + + Xop = DM(Ia += Mb), Yop = PM(Ic += Md); 1 page 6-7 + + + + +2-24 ADSP-219x Instruction Set Reference + Multifunction Instructions + + + + + Table 2-15. Summary of multifunction instructions (Cont’d) + +Instruction Type Details + +|, , |, Dreg = |DM(Ia += Mb), PM(Ic += Md)|; 4, 12 page 6-10 + +|, , |, |DM(Ia += Mb), PM(Ic += Md)| = Dreg; 4, 12 page 6-14 + +|, , |, Dreg = Dreg; 8, 14 page 6-18 + + + + + ADSP-219x Instruction Set Reference 2-25 + Instruction Set Summary + + + + +2-26 ADSP-219x Instruction Set Reference + \ No newline at end of file diff --git a/docs/9x_mltops.pdf b/docs/9x_mltops.pdf new file mode 100644 index 0000000..0bac274 Binary files /dev/null and b/docs/9x_mltops.pdf differ diff --git a/docs/9x_mltops.txt b/docs/9x_mltops.txt new file mode 100644 index 0000000..36f9a81 --- /dev/null +++ b/docs/9x_mltops.txt @@ -0,0 +1,926 @@ +4 MAC INSTRUCTIONS + Figure 4-0. + Table 4-0. + Listing 4-0. + + + + The instruction set provides MAC instructions for performing high-speed + multiplication and multiply with cumulative add/subtract operations. + MAC instructions include: + • “Multiply” on page 4-8 + • “Multiply with Cumulative Add” on page 4-11 + • “Multiply with Cumulative Subtract” on page 4-14 + • “MAC Clear” on page 4-17 + • “MAC Round/Transfer” on page 4-19 + • “MAC Saturate” on page 4-21 + • “Generate MAC Status Only: NONE” on page 4-24 + This chapter describes the individual MAC instructions and the following + related topics: + • “MAC Input Registers” on page 4-2 + • “MAC Output Registers” on page 4-2 + • “Data Format Options” on page 4-3 + • “Status Flags” on page 4-7 + For details on condition codes and data input and output registers, see + “Condition Codes” on page 9-11 and “Core Register Codes” on page + 9-13. + + + + ADSP-219x Instruction Set Reference 4-1 + MAC Instructions + + + + +MAC Input Registers + All unconditional, single-function multiply and multiply with accumula- + tive add or subtract instructions can use any DREG data register for the x + and y input operands (for details, see “Core Register Codes” on page + 9-13). So, the program can use, for example, the ALU registers for the + multiplication or shifter operations, without issuing a separate data move + instruction. This capability simplifies register allocation in algorithm cod- + ing. For example, using the DSP’s dual accumulator: + SR = SR + MX0 * MY0 (SS); + + But in multifunction operations, you can use only certain registers for the + x-input operand (AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1) and the y-input + operand ( MY0, MY1, SR1, 0). + All conditional MAC instructions must use the restricted xop and yop data + registers for the x and y input operands, or an xop register for the x-input + and 0 for the y-input. + +MAC Output Registers + All MAC instructions can use the multiplier MR output registers or the + shifter SR output registers to receive the result of a multiplier operation. + Availability of the shifter SR output registers for multiplier operations pro- + vides dual accumulator functionality. + When MR is the result register, results are directly available from MR0, MR1, + or MR2 as the x-input operand into the very next multiplier operation. + MR = MR + AX0 * AX0 (SS); + + When SR is the result register, the 16-bit value in SR1 (bits 31:16 of the + 40-bit result) is directly available as the y-input operand into the very next + multiplier operation. This functionality is most useful when shifting the + + + + +4-2 ADSP-219x Instruction Set Reference + Data Format Options + + + + + results of a multiply/accumulate operation since it decreases the number + of required data moves. + SR = SR + AX0 * AY0 (SS); + SR = SR + SR1 * AY0 (SS); + + +Data Format Options + Multiplier operations require the instruction to specify the data format of + the input operands (either signed or unsigned) or specify that the multi- + plier rounds (RND) the product of two signed operands. + All data format options, except the round option ( RND), which affects the + product stored in the result register, specify the format of both input oper- + ands in x/y order. The data format options are: + • (RND) Round value in result register. + When overflow occurs, rounds the product to the most significant + twenty-four bits—SR2/SR1 or MR2/MR1 represent the rounded 24-bit + result. Otherwise, rounds bits 31:16 to sixteen bits—MR1 or SR1 con- + tain the rounded 16-bit result. + With (RND) selected, the multiplier considers both input operands + signed (twos complement). If the DSP is in fractional mode + (MSTAT:M_MODE = 0), the multiplier rounds the result after adjusting + for fractional data format. For details, see “Numeric Format Modes” + on page 4-6. + The DSP provides two rounding modes, biased and unbiased, to + support a variety of application algorithms. For details, see “Round- + ing Modes” on page 4-4. + + + + + ADSP-219x Instruction Set Reference 4-3 + MAC Instructions + + + + + • (SS) Both input operands are signed numbers. Signed numbers + are in twos complement format. + You use this option to multiply two signed single-precision numbers + or to multiply the upper portions of two signed multiprecision + numbers. + • (SU) X-input operand is signed; y-input operand is unsigned. + You use this option to multiply a signed single-precision number by + an unsigned single-precision number. + • (US) X-input operand is unsigned; y-input operand is signed. + You use this option to multiply an unsigned single-precision num- + ber by a signed single-precision number. + • (UU) Both input operands are unsigned numbers. Unsigned num- + bers are in ones complement format. + You use this option to multiply two unsigned single-precision num- + bers or to multiply the lower portions of two signed multiprecision + numbers. + +Rounding Modes + Rounding operates on the boundary between bits 15 and 16 of the 40-bit + adder result. The multiplier directs the rounded output to either the MR + or the SR result registers. + The ADSP-219x provides two modes for rounding. The rounding algo- + rithm is the same for both modes, but the final results can differ when the + product equals the midway value (MR0 = 0x8000). + In both methods, the multiplier adds 1 to value of bit 15 in the adder + chain. But when MR0 = 0x8000, the multiplier forces bit 16 in the result + output to 0. Although applied on every rounding operation, the result of + this algorithm is evident only when MR0 = 0x8000 in the adder chain. + + + +4-4 ADSP-219x Instruction Set Reference + Data Format Options + + + + + The rounding mode determines the final result. The BIASRND bit in the + ICNTL register selects the mode. BIASRND = 0 selects unbiased rounding, + and BIASRND = 1 selects biased rounding. + • Unbiased rounding Default mode. Rounds up only when + MR1/SR1 set to an odd value; otherwise, + rounds down. Yields a zero large-sample bias. + • Biased rounding Always rounds up when MR0/SR0 is set to + 0x8000. + + Table 4-1 shows the results of rounding for both modes. + + Table 4-1. MR result values + +MR Value before RND Biased RND Result Unbiased RND Result + +00-0000-8000 00-0001-0000 00-0000-0000 + +00-0001-8000 00-0002-0000 00-0002-0000 + +00-0000-8001 00-0001-0001 00-0001-0001 + +00-0001-8001 00-0002-0001 00-0002-0001 + +00-0000-7FFF 00-0000-FFFF 00-0000-FFFF + +00-0001-7FFF 00-0001-FFFF 00-0001- FFFF + + + Unbiased rounding, preferred for most algorithms, yields a zero large-sam- + ple bias, assuming uniformly distributed values. Biased rounding supports + efficient implementation of bit-specified algorithms, such as GSM speech + compression routines. + + + + + ADSP-219x Instruction Set Reference 4-5 + MAC Instructions + + + + +Numeric Format Modes + The multiplier can operate on integers or fractions. The M_MODE bit in the + MSTAT register selects the mode. M_MODE = 0 selects fractional mode, and + M_MODE = 1 selects integer mode. + + The mode determines whether the multiplier shifts the product before + adding or subtracting it from the result register. + • Integer mode 16.0 integer format + The LSB of the 32-bit product is aligned with the LSB of MR0/SR0. + In multiply and accumulate operations, the multiplier sign-extends + the 32-bit product (8 bits) then adds or subtracts that value from the + result register to form the new 40-bit result. + The multiplier sets the MV/SV overflow bit when the result falls out- + side the range of −1 to +1−231. + • Fractional mode 1.15 fraction format + Fractions range from −1 to +1−215. The MSB of the product is + aligned with the MSB of MR1/SR1. MR1-0/SR1-0 hold a 32-bit frac- + tion (1.31 format) in the range of −1 to +1−231, while MR2/SR2 con- + tains the eight sign-extended bits. In total, the MR/SR registers + contains a fraction in 9.31 format. + In multiply and accumulate operations, the multiplier adjusts the + format of the 32-bit product before adding or subtracting it from + the result register. To do so, the multiplier sign-extends the product + (7 bits), shifts it one bit to the left, and then adds or subtracts that + value from the result register to form the new 40-bit result. + The multiplier sets the MV/SV overflow bit when the result falls out- + side the range of −1 to +1−231. + + + + +4-6 ADSP-219x Instruction Set Reference + Status Flags + + + + +Status Flags + Two status flags in the ASTAT register record the status of multiplier opera- + tions. MV = 1 records an overflow or underflow state when MR is the + specified result register, and SV = 1 records an overflow or underflow state + when SR is the specified result register. + + + + + ADSP-219x Instruction Set Reference 4-7 + MAC Instructions + + + + +Multiply + + MR = DREG1 * DREG2 ( RND ) ; + SR SS + SU + US + UU + + + [IF COND] MR = XOP * YOP ( RND ) ; + SR XOP SS + SU + US + UU + + +FUNCTION + + Multiplies the input operands and stores the result in the specified result + register. Optionally, inputs may be signed or unsigned, and output may be + rounded. For more information on input and output options, see “Data + Format Options” on page 4-3. + If execution is based on a condition, the multiplier performs the multipli- + cation only if the condition evaluates true, and it performs a NOP operation + if the condition evaluates false. Omitting the condition forces uncondi- + tional execution of the instruction. + + + + +4-8 ADSP-219x Instruction Set Reference + Multiply + + + + +INPUT + + For the unconditional form of this instruction, you can use any of these + data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + + For the conditional form of this instruction, the input operands are + restricted. Valid XOP and YOP registers are: + +Xops Yops + + AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1 MY0, MY1, SR1, 0 + + +OUTPUT + + MR Multiplier result register. Results are directly available for x input + only in the next conditional ALU, MAC, or shifter operation or as + either x or y input in the next unconditional ALU, MAC, or shifter + operation. + SR Multiplier feedback register. Results are directly available for either + x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU, + MAC, or shifter operation or as either x or y input in the next + unconditional ALU, MAC, or shifter operation. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + + + + ADSP-219x Instruction Set Reference 4-9 + MAC Instructions + + + + +DETAILS + + This instruction provides a squaring operation (XOP*XOP and DREG1*DREG1) + that performs single-cycle X2 and ΣX2 functions. In squaring operations, + you must use the same register for both x-input operands. + You cannot use DREG form of the multiply instruction in multifunction + instructions. +EXAMPLES + + MR = AY0 * SI (RND); /* mult DREGs, round result */ + SR = AX0 * MX1 (SS); /* mult DREGs, signed inputs */ + + IF MV MR = MX0 * MY0 (SU); /* mult signed X, unsigned Y */ + CCODE = 0x09; NOP; /* set CCODE for SV condition */ + IF SWCOND SR = MR0 * SR1 (UU); /* mult unsigned X and Y */ + +SEE ALSO + + • “Type 9: Compute” on page 9-27 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + +4-10 ADSP-219x Instruction Set Reference + Multiply with Cumulative Add + + + + +Multiply with Cumulative Add + + MR = MR + DREG1 * DREG2 ( RND ) ; + SR = SR SS + SU + US + UU + + + [IF COND] MR = MR + XOP * YOP ( RND ) ; + SR = SR YOP XOP SS + SU + US + UU + + +FUNCTION + + Multiplies the input operands, adds the product to the current contents of + the MR or SR register, and then stores the sum in the corresponding result + register. Optionally, inputs may be signed or unsigned, and output may be + rounded. For more information on input and output options, see “Data + Format Options” on page 4-3. + If execution is based on a condition, the multiplier performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. + + + + + ADSP-219x Instruction Set Reference 4-11 + MAC Instructions + + + + +INPUT + + For the unconditional form of this instruction, you can use any of these + data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + + For the conditional form of this instruction, the input operands are + restricted. Valid XOP and YOP registers are: + +Xops Yops + + AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1 MY0, MY1, SR1, 0 + + +OUTPUT + + MR Multiplier result register. Results are directly available for x input + only in the next conditional ALU, MAC, or shifter operation or as + either x or y input in the next unconditional ALU, MAC, or shifter + operation. + SR Multiplier feedback register. Results are directly available for either + x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU, + MAC, or shifter operation or as either x or y input in the next + unconditional ALU, MAC, or shifter operation. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + + + +4-12 ADSP-219x Instruction Set Reference + Multiply with Cumulative Add + + + + +DETAILS + + This instruction provides a squaring operation (xop*xop and DREG*DREG) + that performs single-cycle X2 and ΣX2 functions. In squaring operations, + you must use the same register for both x-input operands. + You cannot use unconditional (Dreg) form of the multiply instruction in + multifunction instructions. +EXAMPLES + + MR = MR + AX0 * SI (RND); /* mult DREGs, rnd output, sum */ + SR = SR + AX1 * MX0 (SS); /* mult DREGs, sign input, sum */ + + IF MV MR = MR + MR0 * MY0 (SU); + /* mult X/Yops, un/sign in, sum */ + IF MV MR = MR + MR2 * MX1 (UU); + /* mult X/Yops, unsign in, sum */ + CCODE = 0x09; NOP; /* set CCODE for SV condition */ + IF SWCOND SR=SR+SR0*MY0 (US); + /* mult X/Yops, un/sign in, sum */ + +SEE ALSO + + • “Type 9: Compute” on page 9-27 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + + ADSP-219x Instruction Set Reference 4-13 + MAC Instructions + + + + +Multiply with Cumulative Subtract + + MR = MR − DREG1 * DREG2 ( RND ) ; + SR = SR SS + SU + US + UU + + + [IF COND] MR = MR − XOP * YOP ( RND ) ; + SR = SR YOP XOP SS + SU + US + UU + + +FUNCTION + + Multiplies the input operands, subtracts the product from the current + contents of the MR or SR register, and then stores the result in the corre- + sponding destination register. Optionally, inputs may be signed or + unsigned, and output may be rounded. For more information on input + and output options, see “Data Format Options” on page 4-3. + If execution is based on a condition, the multiplier performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. + + + + +4-14 ADSP-219x Instruction Set Reference + Multiply with Cumulative Subtract + + + + +INPUT + + For the unconditional form of this instruction, you can use any of these + data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + + For the conditional form of this instruction, the input operands are + restricted. Valid XOP and YOP registers are: + +Xops Yops + + AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1 MY0, MY1, SR1, 0 + + +OUTPUT + + MR Multiplier result register. Results are directly available for x input + only in the next conditional ALU, MAC, or shifter operation or as + either x or y input in the next unconditional ALU, MAC, or shifter + operation. + SR Multiplier feedback register. Results are directly available for either + x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU, + MAC, or shifter operation or as either x or y input in the next + unconditional ALU, MAC, or shifter operation. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + + + + ADSP-219x Instruction Set Reference 4-15 + MAC Instructions + + + + +DETAILS + + This instruction provides a squaring operation (xop*xop and DREG*DREG) + that performs single-cycle X2 and ΣX2 functions. In squaring operations, + you must use the same register for both x input operands. + You cannot use unconditional (Dreg) form of the multiply instruction in + multifunction instructions. +EXAMPLES + + MR = MR - AX0 * SI (RND); /* mult DREGs, rnd output, sub */ + SR = SR - AX1 * MX0 (SS); /* mult DREGs, sign input, sub */ + + IF MV MR = MR - MR0 * MY0 (SU); + /* mult X/Yops, un/sign in, sub */ + IF MV MR = MR - MR2 * MX1 (UU); + /* mult X/Yops, unsign in, sub */ + CCODE = 0x09; NOP; /* set CCODE for SV condition */ + IF SWCOND SR=SR-SR0*MY0 (US); + /* mult X/Yops, un/sign in, sub */ + +SEE ALSO + + • “Type 9: Compute” on page 9-27 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + +4-16 ADSP-219x Instruction Set Reference + MAC Clear + + + + +MAC Clear + + [IF COND] MR = 0 ; + SR + + +FUNCTION + + Sets the specified register to 0. + If execution is based on a condition, the multiplier performs the operation + only if the condition evaluates true, and it performs a NOP operation if + the condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. +INPUT + + This instruction is a special case of xop * yop with the y-input operand set + to 0. +OUTPUT + + MR Multiplier result register. Results are directly available for x input + only in the next conditional ALU, MAC, or shifter operation or as + either x or y input in the next unconditional ALU, MAC, or shifter + operation. + SR Multiplier feedback register. Results are directly available for either + x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU, + MAC, or shifter operation or as either x or y input in the next + unconditional ALU, MAC, or shifter operation. + + + + + ADSP-219x Instruction Set Reference 4-17 + MAC Instructions + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +MV (cleared if MR used), SV (cleared if SR used) AZ, AN, AV, AC, AS, AQ, SS + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + See description in “function” on page 4-17. +EXAMPLES + + MR = 0; /* clears MR */ + SR = 0; /* clears SR */ + +SEE ALSO + + • “Type 9: Compute” on page 9-27 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + +4-18 ADSP-219x Instruction Set Reference + MAC Round/Transfer + + + + +MAC Round/Transfer + + [IF COND] MR = MR (RND) ; + + + [IF COND] SR = SR (RND) ; + + +FUNCTION + + Performs a multiply with cumulative add operation in which the y-input + operand is 0 and the zero-product is added to the specified result register. + Rounding (RND) directs the multiplier to round the entire 40-bit value + stored in the result register, MR or SR. + If execution is based on a condition, the multiplier performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. +INPUT + + This instruction is a special case of MR|SR + xop * yop with the y-input + operand set to 0. +OUTPUT + + MR Multiplier result register. Results are directly available for x input + only in the next conditional ALU, MAC, or shifter operation or as + either x or y input in the next unconditional ALU, MAC, or shifter + operation. + SR Multiplier feedback register. Results are directly available for either + x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU, + MAC, or shifter operation or as either x or y input in the next + unconditional ALU, MAC, or shifter operation. + + + + + ADSP-219x Instruction Set Reference 4-19 + MAC Instructions + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + The BIASRND bit in the ICNTL register determines the rounding mode. + Refer to the section “Rounding Modes” on page 4-4 for more informa- + tion. For a complete description of the MAC Round/ Transfer + instruction, see the section “function” on page 4-19. +EXAMPLES + + MR = MR (RND); /* round MR */ + IF EQ SR = SR (RND); /* round SR */ + +SEE ALSO + + • “Type 9: Compute” on page 9-27 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + +4-20 ADSP-219x Instruction Set Reference + MAC Saturate + + + + +MAC Saturate + + SAT MR ; + + + SAT SR ; + + +FUNCTION + + Tests the MV (MAC overflow) or SV (shifter overflow) bit in the ASTAT reg- + ister. If set ( 1), the multiplier saturates the low-order (31:0) bits of the + 40-bit MR or SR register; otherwise, the multiplier performs a NOP + operation. +INPUT + + None. +OUTPUT + + MR Multiplier result register. Results are directly available for x input + only in the next conditional ALU, MAC, or shifter operation or as + either x or y input in the next unconditional ALU, MAC, or shifter + operation. + SR Multiplier feedback register. Results are directly available for either + x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU, + MAC, or shifter operation or as either x or y input in the next + unconditional ALU, MAC, or shifter operation. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + AZ, AN, AV, AC, AS, AQ, SS, MV, SV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + + + + ADSP-219x Instruction Set Reference 4-21 + MAC Instructions + + + + +DETAILS + + The MAC saturation instruction provides control over a multiplication + result that has overflowed or underflowed. It saturates the value in the + specified register only for the cycle in which it executes. It does not enable + a mode that continuously saturates results until disabled, like the ALU. + Used at the end of a series of multiply and accumulate operations, the sat- + uration instruction prevents the accumulator from overflowing. + For every operation it performs, the multiplier generates an overflow sta- + tus signal MV (SV when SR is the specified result register), which is recorded + in the ASTAT status register. MV = 1 when the accumulator result, inter- + preted as a signed (twos complement) number, crosses the 32-bit + boundary, spilling over from MR1 into MR2. That is, the multiplier sets + MV = 1 when the upper nine bits in MR are anything other than all 0s or all + 1s. Otherwise, it sets MV = 0. + + The operation invoked by the saturation instruction depends on the over- + flow status bit MV (or SV) and the MSB of MR2, which appear in Table 4-2. + If MV/SV = 0, no saturation occurs. When MV/SV = 1, the multiplier exam- + ines the MSB of MR2 to determine whether the result has overflowed or + underflowed. If the MSB = 0, the result has overflowed, and the multiplier + saturates the MR register, setting it to the maximum positive value. If the + MSB = 1, the result has underflowed, and the multiplier saturates the MR + register, setting it to the maximum negative value. + + Table 4-2. Saturation Status Bits & Result Registers + +MV/SV MSB of MR2/SR2 MR/SR Results + + 0 0 No change. + + 0 1 No change. + + 1 0 00000000 0111111111111111 1111111111111111 + + 1 1 11111111 1000000000000000 0000000000000000 + + + + +4-22 ADSP-219x Instruction Set Reference + MAC Saturate + + + + + Do not permit the result to overflow beyond the MSB of MR2. Otherwise, + the true sign bit of the result is irretrievably lost, and saturation may not + produce a correct result. To reach this state, however, takes more than 255 + overflows (MV type). +EXAMPLES + + SAT MR; /* saturate MR */ + SAT SR; /* saturate SR */ + +SEE ALSO + + • “Type 9: Compute” on page 9-27 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + + ADSP-219x Instruction Set Reference 4-23 + MAC Instructions + + + + +Generate MAC Status Only: NONE + + [NONE =] ; + + +FUNCTION + + Performs the indicated unconditional MAC operation but does not load + the results into the MR or SR result registers. Generates MAC status flags + only. You can use this instruction to set MAC status without disturbing + the contents of the MR and SR result registers. +INPUT + + XOP Limits the registers for the x input operand. Valid XOP registers are: + +Xops + + AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1 + + + YOP Limits the registers for the x input operand. Valid YOP registers are: + +Yops + + MY0, MY1, SR1, 0 + + +OUTPUT + + None. Generates MAC status flags only. + + + + +4-24 ADSP-219x Instruction Set Reference + Generate MAC Status Only: NONE + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +MV AZ, AN, AV, AC, AS, AQ, SS, SV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + You can use any unconditional MAC operation to generate MAC status + flags. +EXAMPLES + + MX0 * MY0; /* generate status from mult */ + +SEE ALSO + + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26. + + + + + ADSP-219x Instruction Set Reference 4-25 + MAC Instructions + + + + +4-26 ADSP-219x Instruction Set Reference + \ No newline at end of file diff --git a/docs/9x_moveops.pdf b/docs/9x_moveops.pdf new file mode 100644 index 0000000..aff1469 Binary files /dev/null and b/docs/9x_moveops.pdf differ diff --git a/docs/9x_moveops.txt b/docs/9x_moveops.txt new file mode 100644 index 0000000..44670dc --- /dev/null +++ b/docs/9x_moveops.txt @@ -0,0 +1,2598 @@ +7 DATA MOVE INSTRUCTIONS + Figure 7-0. + Table 7-0. + Listing 7-0. + + + + The instruction set provides move instructions for transferring data + between the DSP’s data registers, memory, I/O registers, and system con- + trol registers. Transfer operations include reading, writing, loading, and + storing data from one location to another. Data move operations include: + • “Register to Register Move” on page 7-22 + • “Direct Memory Read/Write—Immediate Address” on page 7-24 + • “Direct Register Load” on page 7-27 + • “Indirect 16-bit Memory Read/Write—postmodify” on page 7-30 + • “Indirect 16-bit Memory Read/Write—premodify” on page 7-34 + • “Indirect 24-bit Memory Read/Write—postmodify” on page 7-37 + • “Indirect 24-bit Memory Read/Write—premodify” on page 7-41 + • “Indirect DAG Register Write (premodify or postmodify), with + DAG Register Move” on page 7-45 + • “Indirect Memory Read/Write—immediate postmodify” on + page 7-49 + • “Indirect Memory Read/Write—immediate premodify” on + page 7-52 + • “Indirect 16-bit Memory Write—immediate data” on page 7-55 + • “Indirect 24-bit Memory Write—immediate data” on page 7-57 + + + + + ADSP-219x Instruction Set Reference 7-1 + Data Move Instructions + + + + + • “External IO Port Read/Write” on page 7-59 + • “System Control Register Read/Write” on page 7-61 + • “Modify Address Register—indirect” on page 7-63 + • “Modify Address Register—direct” on page 7-65 + This chapter describes each of the move instructions and the following + related topics: + • “Core Registers” on page 7-2 + • “PX Register” on page 7-4 + • “DAG Registers” on page 7-6 + • “Register Load Latencies” on page 7-9 + • “Direct Addressing” on page 7-12 + • “Indirect Addressing” on page 7-12 + • “Circular Data Buffer Addressing” on page 7-15 + • “Bit-Reversed Addressing” on page 7-17 + +Core Registers + Table 7-1 lists the registers that reside in the DSP’s core. Most are 16-bit + registers, but some Reg3 registers are shorter—ASTAT[9], MSTAT[7], + + + + +7-2 ADSP-219x Instruction Set Reference + Core Registers + + + + + SSTAT[8], LPCSTACKP[9], CCODE[4], PX[8], DMPG1[8], DMPG2[8], IOPG[8], + IJPG[8], and STACKP[8]. + + + Table 7-1. Core registers + +Register Groups + +Reg0 (Dreg) Reg1 (G1reg) Reg2 (G2reg) Reg3 (G3reg) + +AX0 I0 I4 ASTAT + +AX1 I1 I5 MSTAT + +MX0 I2 I6 SSTAT + +MX1 I3 I7 LPSTACKP + +AY0 M0 M4 CCODE + +AY1 M1 M5 SE + +MY0 M2 M6 SB + +MY1 M3 M7 PX + +MR2 L0 L4 DMPG1 + +SR2 L1 L5 DMPG2 + +AR L2 L6 IOPG + +SI L3 L7 IJPG + +MR1 IMASK Reserved Reserved + +SR1 IRPTL Reserved Reserved + +MR0 ICNTL CNTR Reserved + +SR0 STACKA LPSTACKA STACKP + + + + + ADSP-219x Instruction Set Reference 7-3 + Data Move Instructions + + + + + As shown, registers are grouped along functional lines: + • Reg0 (Dreg) Consists of data registers. + • Reg1 (G1reg) Consists of DAG1 addressing registers, interrupt + control registers, and the lower part of the PC stack register. + • Reg2 (G2reg) Consists of DAG2 addressing registers, the loop + counter register, and the lower part of the loop PC register. + • Reg3 (G3reg) Consists of status registers, page registers. + +PX Register + The PX register, an 8-bit extension register, enables applications to transfer + 24-bit data between 24-bit memory and 16-bit data registers. Only 24-bit + accesses of 24-bit memory use the PX register. (So, a 16-bit read of 24-bit + memory does not load the PX register, and a 16-bit write fills the lower + eight bits in 24-bit memory with zeros (0).) + On reads, the PX register stores the lower eight bits of the 24-bit data + transferring from memory to a destination register, and on writes, it sup- + plies them for the data written to 24-bit data space. + Only two instructions use the PX register: + • ALU/MAC with dual indirect memory reads (see page “Compute + with Dual Memory Read” on page 6-3) + • Indirect 24-bit memory read or write with pre- or postmodify + addressing option (see page 7-37 and page 7-41) + + + + +7-4 ADSP-219x Instruction Set Reference + PX Register + + + + +To access 24-bit memory, you typically use the PM(Ireg += Mreg) syntax +shown here: + AX1 = PM(I0 += M2); /* Read 24 bits, load 16 MSbits in AX1 */ + /* PX autoloaded w/8 memory LSbits */ + AY1 = PX; /* Load lower 8 bits from PX in AY1 */ + + PX = MR2; /* Load lower 8 bits into PX */ + PM(I4 += M5) = MR1; /* Write all 24 bits from MR1 and PX */ + +On data reads using the PX register, the DSP transfers the upper sixteen +bits of the 24-bit data to the destination data register and the lower eight +bits to the PX register. The data loaded from memory is right-justified in +the destination registers. +On data writes using the PX register, the DSP transfers the upper sixteen +bits of the 24-bit data from the bus and the lower eight bits from the PX +register, except for indirect writes of 24-bit immediate data, in which the +instruction supplies the eight LSBs. The data written is right-justified in +memory. + +! entlytransfers + PX to and from memory occur automatically and transpar- + to the user, but the user must transfer data between the reg- + PX + ister and the data registers. +Because the DSP has a unified memory space, the address, not the syntax, +determines whether the reference accesses 16-bit memory or 24-bit mem- +ory at run time. + • For 24-bit references that read 16-bit memory, the PX register + receives whatever data the memory system outputs for the eight + LSBs. For internal memory, this value is 0x00. + • For 24-bit references that write 16-bit memory, the DSP discards + the data in the PX register. + + + + + ADSP-219x Instruction Set Reference 7-5 + Data Move Instructions + + + + +DAG Registers + The DAGs generate memory addresses for data transfers to and from + memory. To do so, each uses a set of address registers and a page register. + For fast context switching during interrupt servicing, the DAGs provide a + secondary set of address registers. This section describes these registers. + +DAG Address Registers + Each DAG has a set of address registers that it uses to generate memory + addresses for loading or storing data in memory. Each DAG can use its + own set of address registers only. DAG1 uses registers 0 through 3, and + DAG2 uses registers 4 through 7. + The DAG address registers are: + • Index (Ireg) Pointer to the current memory address. DAG1 (I0– + I3); DAG2 ( I4–I7). + + • Modify (Mreg) Offset (from index) value for pre- or post-modify + addressing. DAG1 (M0–M3); DAG2 (M4–M7). + • Length (Lreg) Number of memory locations in a buffer. DAG1 + (L0–L3); DAG2 (L4–L7). For linear buffers, you must + explicitly set Lreg = 0; for circular buffers, you must + explicitly set Lreg to the length of the buffer. + • Base (Breg) Starting address of a circular buffer. DAG1 (B0–B3); + DAG2 (B4–B7).Used with circular buffering only. + Each base (Breg) and length (Lreg) register is associated with its specific + index (Ireg) register—I0/B0/L0, I1/B1/L1, …, and I7/B7/L7. So, + although you can mix and match any of the index (Ireg) and modify + (Mreg) registers within the same DAG group, you must always use the base + (Breg) and length (Lreg) register that is associated with the particular + index (Ireg) register you use. + + + + +7-6 ADSP-219x Instruction Set Reference + DAG Registers + + + + +DAG Page Registers (DMPGx) + The DAGs and their associated page registers generate 24-bit addresses for + accessing the data needed by instructions. For data accesses, the DSP’s + unified memory space is organized into 256 pages, with 64K locations per + page. The page registers provide the eight MSBs of the 24-bit address, + specifying the page on which the data is located. The DAGs provide the + sixteen LSBs of the 24-bit address, specifying the exact location of the data + on the page. + • The DMPG1 page register is associated with DAG1 (registers I0—I3) + indirect memory accesses as well as immediate, direct memory + accesses. It supplies the upper 8 MSBs for direct memory addressed + instructions. + • The DMPG2 page register is associated with DAG2 (registers I4—I7) + indirect memory accesses. + At power up, the DSP initializes both page registers to 0x0. Although ini- + tializing page registers is unneccessary unless the data is located on other + than the current page. For good programming practice, we recommend + that you set the corresponding page register whenever you initialize a + DAG index register (Ireg) to set up a data buffer. + For example, + DMPG1 = 0x12; /* set page register */ + /* or DMPG1 = page(data_buffer); for relative addressing */ + + I2 = 0x3456; /* init data buffer; 24b addr=0x123456 */ + L2 = 0; /* define linear buffer */ + M2 = 1; /* increment address by one */ + /* two stall cycles inserted here */ + DM(I2 += M2) = AX0; /* write data to buffer and update I2 */ + + + ! DAG register ( , , , , ) loads can incur up to + DMPGx Ireg Mreg Lreg Breg + two stall cycles when a memory access based on the initialized reg- + ister immediately follows the initialization. + + + + ADSP-219x Instruction Set Reference 7-7 + Data Move Instructions + + + + + To avoid these unproductive stall cycles, you could code the memory + access sequence like this: + DMPG1 = 0x12; /* set page register */ + /* or DMPG1 = page(data_buffer); for relative addressing */ + + I2 = 0x3456; /* init data buffer; 24b addr=0x123456 */ + L2 = 0; /* define linear buffer */ + M2 = 1; /* increment address by one */ + AX0 = 0xAAAA; + AR = AX0 − 1; + DM(I2 += M2) = AR; /* write data to buffer and update I2 */ + + Typically, you load both page registers with the same page value (0-255), + but you can increase memory flexibility by loading each with a different + page value. For example, loading the page registers with different page val- + ues, you could: + • Separate DMA space from the application’s data space + • Perform high-speed data transfers between pages + This operation is not automatic and requires explicit programming. + +Secondary DAG Registers + The secondary set of DAG address registers (Ireg, Mreg, Lreg, and Breg) + enable single-cycle context-switching to support real-time control func- + tions and to reduce overhead associated with interrupt servicing. + By default, system power-up and reset enable the primary set of DAG + address registers. To enable or disable the secondary address registers, you + must set or clear, respectively, the SEC_DAG bit (bit 6) in MSTAT (for details, + see “Mode Status (MSTAT) Register” on page 2-11). The instruction set + provides three methods for doing so. Each method incurs a latency, which + is the delay between the time the instruction effecting the change executes + and the time the change takes effect and is available to other instructions. + Table 7-2 on page 7-10 shows the latencies associated with each method. + + + + +7-8 ADSP-219x Instruction Set Reference + Register Load Latencies + + + + + When switching between primary and secondary DAG registers, applica- + tions need to account for the latency associated with the method they use. + For example, after the MSTAT = data12; instruction, three cycles of latency + occur before the mode change takes effect. So, you must issue at least three + instructions after MSTAT = 0x20; before attempting to use the new set of + DAG registers. Otherwise, you will overwrite the primary set and lose + data. + The ENA/DIS mode instruction is more efficient for enabling and disabling + DSP modes since it incurs no cycles of effect latency. For example: + CCODE = 0x9; NOP; + If SWCOND JUMP do_data;/* Jump to do_data */ + do_data: + ENA SEC_DAG; /* Switch to 2nd DAGs */ + ENA SEC_REG; /* Switch to 2nd Dregs */ + AX0 = DM(buffer); /* if buffer empty, go */ + AR = PASS AX0; /* right to fill and */ + IF NE JUMP fill; /* get new data */ + RTI; + fill: /* fill routine */ + NOP; + buffer: /* buffer data */ + NOP; + + +Register Load Latencies + An effect latency occurs when some instructions write or load a value into + a register, which changes the value of one or more bits in the register. + Effect latency refers to the time it takes after the write or load instruction + for the effect of the new value to become available for other instructions to + use. + Effect latency values are given in terms of instruction cycles. A 0 latency + means that the effect of the new value is available on the next instruction + following the write or load instruction. For register changes that have an + effect latency greater than 0, make sure you do not try to use the register + right after you write or load a new value to avoid using the old value. + + + + ADSP-219x Instruction Set Reference 7-9 + Data Move Instructions + + + + + Table 7-2 gives the effect latencies for writes or loads of various interrupt + and status registers. + + Table 7-2. Effect latencies for register changes + +Register Bits REG = value ENA/DIS mode POP STS SET/CLR INT + + ASTAT All 1 cycle NA 0 cycles NA + + CCODE All 1 cycle NA NA NA + + CNTR All 1 cycle1 NA NA NA + + ICNTL All 1 cycle NA NA 0 cycles + + IMASK All 1 cycle NA 0 cycles NA + + MSTAT SEC_REG 1 cycle 0 cycles 1 cycle NA + + BIT_REV 3 cycles 0 cycles 3 cycles NA + + AV_LATCH 0 cycles 0 cycles 0 cycles NA + + AR_SAT 1 cycle 0 cycles 1 cycle NA + + M_MODE 1 cycle 0 cycles 1 cycle NA + + TIMER 1 cycle 0 cycles 1 cycle NA + + SEC_DAG 3 cycles 0 cycles 3 cycles NA +1 This latency applies only to IF COND instructions, not to the DO UNTIL instruction. Loading the + CNTR register has 0 effect latency for the DO UNTIL instruction. + + + + ! Abut a or or + PUSH POP PC has one cycle of latency for all SSTAT register bits, + PUSH POP LOOP or STS has one cycle of latency only for the + STKOVERFLOW bit in the SSTAT register. + + When you load some Group 2 and 3 registers (see Table 7-1 on page 7-3), + the effect of the new value is not immediately available to subsequent + + + +7-10 ADSP-219x Instruction Set Reference + Register Load Latencies + + + + +instructions that might use it. For interlocked registers (DAG address and +page registers, IOPG, IJPG), the DSP automatically inserts stall cycles as +needed, but for noninterlocked registers, to accommodate the required +latency, you must insert either the necessary number of NOP instructions or +other instructions that are not dependent upon the effect of the new value. +The noninterlocked registers are: + • Status registers ASTAT and MSTAT + • Condition code register CCODE + • Interrupt control register ICNTL +The number of NOP instructions you must insert is specific to the register +and the load instruction as shown in Table 7-2. A zero (0) latency indi- +cates that the new value is effective on the next cycle after the load +instruction executes. An n latency indicates that the effect of the new value +is available up to n cycles after the load instruction executes. When you +use a modified register before the required latency, you may get the regis- +ter’s old value. +Since unscheduled or unexpected events (interrupts, DMA operations, +etc.) often interrupt normal program flow, do not rely on these load laten- +cies when you structure your program’s flow. A delay in executing a +subsequent instruction based on a newly loaded register could result in +erroneous results—whether the subsequent instruction is based on the +effect of the register’s new or old value. + +! Load latency applies only to the time it takes the loaded value to + effect the change in operation, not to the number of cycles required + to load the new value. A loaded value is always available to a read + access on the next instruction cycle. + + + + + ADSP-219x Instruction Set Reference 7-11 + Data Move Instructions + + + + +Data Addressing Methods + The instruction set supports two addressing methods for accessing mem- + ory data: + • Direct addressing The user supplies an explicit address in the + instruction. + • Indirect addressing The DAG address registers generate + addresses. + +Direct Addressing + Direct addressing is the simplest method to use. An explicit address or a + label included in the instruction specifies the address of a memory access. + A label is a symbolic name that you assign to an address. + You specify an explicit address or label in a data move instruction like this: + DM(I1 += M0) = 0x1234; /* write data 0x1234 and post-modify */ + AX0 = DM(0x3333); /* read location 0x3333, put in AX0 */ + DM(port1) = AY1; /* write value in AY1 to port1 */ + port1: /* port1 address should be in linker ldf */ + NOP; + + When you use a label, you can either specify the address that the label ref- + erences or let the VisualDSP linker assign the label an address. For details + on assigning label addresses, see the VisualDSP User’s Guide for + ADSP-219x Family DSPs. + +Indirect Addressing + Indirect addressing uses a pointer to specify the address of a memory + access. The DAG index (Ireg) and modify (Mreg) registers implement + address pointers for indirect addressing. The Ireg supplies the address + value, and the Mreg supplies the modify (offset) value, which, added to the + address value, forms the address of the next memory location. The instruc- + + + + +7-12 ADSP-219x Instruction Set Reference + Data Addressing Methods + + + + +tion set provides two address modification options—premodify with no +update and postmodify with update. + • Premodify addressing—no update + Premodify addressing does not permanently change the value of the + index register (Ireg). In premodify operations, the sum of the Ireg + and Mreg register values provides the address of the memory access. + After the access, the Ireg register retains its original value. + For example, setting up a DAG1 linear data buffer using the pre- + modify option: + #define buffer1 0x2 + DMPG1 = page(buffer1); + I0 = buffer1; + M0 = 0x0007; + L0 = 0; /* Unless L = 0 buffer is circular */ + AX0 = DM(I0 + M0); /* AX0 receives data @ I0+M0 */ + /* I0 retains original value */ + +or a DAG2 linear data buffer premodified with a constant: + #define buffer2 0x3 + DMPG2 = page(buffer2); + I4 = buffer2; + L4 = 0; /* Unless L = 0 buffer is circular */ + AX0 = DM(I4 + 0x0007); /* AX0 receives data @ I4+0x0007 */ + /* I4 retains original value */ + + • Postmodify addressing—with update + Postmodify addressing permanently changes the value in the index + (Ireg) register. In postmodify operations, the current value in Ireg + is used for the memory access. After the access, the DSP adds the + + + + + ADSP-219x Instruction Set Reference 7-13 + Data Move Instructions + + + + + modify value in Mreg to the address value in Ireg and overwrites the + contents in Ireg with the result. + For example, setting up a DAG1 linear data buffer using the post- + modify option: + #define buffer3 0x2 + DMPG1 = page(buffer3); + I0 = buffer3; + M0 = 0x0007; + L0 = 0; /* Unless L = 0 buffer is circular */ + AX0 = DM(I0 += M0); /* AX0 receives data @ I0+M0 */ + /* updated with sum of (I0+M0) */ + + or a DAG1 linear data buffer postmodified with a constant: + #define buffer4 0x3 + DMPG1 = page(buffer4); + I0 = buffer4; + L0 = 0; /* Unless L = 0 buffer is circular */ + AX0 = DM(I0 += 0x0003); /* AX0 receives data @ I0+0x0003 */ + /* I0 updated w/sum of (I0+0x0003) */ + + + ! Circular buffers work with postmodify addressing only. + To set up data buffers, you can mix and match any of the DAG index + (Ireg) and modify (Mreg) registers within the same DAG group (DAG1 or + DAG2), but not between DAG groups. Length (Lreg) and base address + (Breg) registers, when used, must always match their corresponding Ireg. + For example, the following code is valid, because it uses corresponding + Ireg and Lreg registers: + + DMPG1 = page(data_in); + I3 = data_in; + M1 = 0x0007; + L3 = 0; /* Unless Lreg = 0 buffer is circular */ + AX0 = DM(I3 += M1); + data_in: /* data_in location could elsewhere */ + NOP; + + + + +7-14 ADSP-219x Instruction Set Reference + Data Addressing Methods + + + + +Circular Data Buffer Addressing + Circular data buffers enable applications to reuse the same data buffer; for + example, to store the filter coefficients for a FIR or IIR filter or to act as a + delay line for the convolution of an input signal. + A circular data buffer is a set of memory locations used for storing a set of + data. A circular data buffer is defined by a set of DAG address registers: + • Base ( B0-B7) Starting address. + These registers are off core, so you must use the + data (Dreg) registers and this syntax to access them: + REG(Breg) = Dreg; + + • Index (I0-I7) Current address. + The Ireg points to the current address within the + buffer. After the access, the Ireg is postmodified + with the address of next access. + • Modify (M0-M7) Number of locations offset from the current + address. To calculate the address of the next access, + the offset value in Mreg is added to the current Ireg + value, and the result is written to Ireg. + • Length (L0-L7) Number of memory locations in the buffer. + An index pointer (Ireg) steps through the data buffer, forwards or back- + wards, in programmable increments as determined by a modifier (Mreg) + value. The base address (Breg) and the buffer’s length (Lreg) keep the + pointer within the range of the buffer’s memory locations. When the + index pointer steps outside the buffer’s address range, the logic adds or + subtracts the buffer’s length from the index value to wrap the pointer back + to the top or bottom of the buffer, as appropriate. + For example, the following code sets up a circular data buffer: + .section/dm seg_data; + .VAR coeff_buffer[13] = 0,1,2,3,4,5,6,7,8,9,10,11,12; + + + + + ADSP-219x Instruction Set Reference 7-15 + Data Move Instructions + + + + + .section/pm seg_code; + DMPG2 = page(coeff_buffer); /* Set the memory page */ + I4 = coeff_buffer; /* Set the current addr */ + M5 = 5; /* Set the modify value */ + L4 = LENGTH(coeff_buffer); /* If L = 0 buffer is linear */ + AX0 = I4; /* Copy the base addr into AX0 */ + REG(B4) = AX0; /* Set the buffer’s base addr */ + AR = AX1 AND AY0; + AR = DM(I4 += M5); /* Read 1st buffer location */ + + Figure 7-1, using this code example, demonstrates how the index pointer + steps through the circular buffer. + Modify = 5 Length = 13 + 0 1 0 0 0 + 1 1 1 1 9 + 2 2 4 2 2 + 3 3 3 3 + 4 4 4 7 4 + 5 2 5 5 5 + 6 6 6 6 10 + 7 7 5 7 7 + 8 8 8 8 + 9 9 9 8 9 + 10 3 10 10 10 + 11 11 11 11 11 + 12 12 6 12 12 + + Figure 7-1. Stepping through a circular data buffer + + Circular data buffers work with the postmodify addressing option only. + You must initialize the length (Lreg) register to the length of the buffer. + Positive modify values increment the index register, and negative modify + values decrement it. + + + + +7-16 ADSP-219x Instruction Set Reference + Data Addressing Methods + + + + + " Do not place the index pointer for a circular buffer such that it + crosses a memory page boundary during post-modify addressing. All + memory locations in a circular buffer must reside on the same mem- + ory page. + +Bit-Reversed Addressing + Bit-reversed addressing is frequently used in FFT calculations to obtain + results in sequential order. Because FFT operations repeatedly subdivide + data sequences, the data or twiddle factors may be scrambled, loaded or + stored in bit-reversed order. + For performing FFT operations, you can reverse the order in which DAG1 + outputs its address bits. DAG2 always outputs its address bits in normal, + Big Endian format. Since the two DAGs operate independently, you can + use them in tandem, with one generating sequentially ordered addresses + and the other generating bit-reversed addresses, to perform memory reads + and writes of the same FFT data. + To use bit-reversed addressing, you set bit 1 in the MSTAT register (ENA + BIT_REV). When enabled, DAG1 outputs all addresses generated by its + index registers (I0–I3) in bit-reversed order. The reversal applies only to + the address value DAG1 outputs, not to the address value stored in the + index (Ireg) register, so the Ireg value is stored in Big Endian format. + Bit-reversed mode remains in effect until you clear bit 1 in the MSTAT reg- + ister (DIS BIT_REV). + Bit reversal operates on the binary number that represents the position of + a sample within an array of samples. Using 3-bit addresses, Table 7-3 + shows the position of each sample within an array before and after the + bit-reverse operation. For example, sample x4 occupies position 0b100 in + sequential order, but position 0b001 in bit-reversed order. Bit reversing + transposes the bits of a binary number about its midpoint, so 0b001 + becomes 0b100, 0b011 becomes 0b110, and so on. Some numbers, like + + + + + ADSP-219x Instruction Set Reference 7-17 + Data Move Instructions + + + + + 0b000, 0b111, and 0b101, remain unchanged and retain their original posi- + tion within the array. + + Table 7-3. 8-point array sequence before and after bit reversal + +Sequential Order Bit Reversed Order + +Sample Binary Binary Sample + + x0 000 000 x0 + + x1 001 100 x4 + + x2 010 010 x2 + + x3 011 110 x6 + + x4 100 001 x1 + + x5 101 101 x5 + + x6 110 011 x3 + + x7 111 111 x7 + + + Bit-reversing the samples in a sequentially ordered array scrambles their + positions within the array. Bit-reversing the samples in a scrambled array + restores their sequential order within the array. + In full 16-bit reversed addressing, bits 7 and 8 of the 16-bit address are the + pivot points for the reversal: + + Normal 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + Bit-reversed 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + + + FFT operations often need only a few address bits reversed; for example, a + a 16-point sequence requires four reversed bits, and a 1024-bit sequence + + + +7-18 ADSP-219x Instruction Set Reference + Data Addressing Methods + + + + +requires ten reversed bits. You can bit-reverse address values less than +16-bits—which reverses a specified number of LSBs only. Bit-reversing +less than the full 16-bit index register value requires that you add the cor- +rect modify value to the index pointer after each memory access to +generate the correct bit-reversed addresses. +To set up bit-reversed addressing for address values < 16 bits, you need to +determine: + • The number of bits to reverse (N) + You use this value to calculate the modify value. + • The starting address of the linear data buffer + The starting address of an array that the program accesses with + bit-reversed addressing must be zero or an integer multiple of the + number of bits to reverse (starting address = 0, N, 2N, …). + • The first bit-reversed address that the DAG will output + This value is the buffer’s starting address, but with the N LSBs + bit-reversed. + • The initialization value for the index (Ireg) + You initialize the index (Ireg) register with the bit-reversed value of + the first bit-reversed address the DAG will output. + • The correct modify value (Mreg) with which to update the index + pointer after each memory access + Use this formula to calculate the modify value: Mreg = 2(16-N). +As an example, we’ll set up bit-reversed addressing that reverses the eight +address LSBs (N = 8) of a data buffer with a starting address of 0x0020 +(4N). + + + + + ADSP-219x Instruction Set Reference 7-19 + Data Move Instructions + + + + + We need to determine the: + • First bit-reversed address that DAG1 will output + This value is the buffer’s starting address (0x0020) with bits[7:0] + reversed: 0x0004. + + 0x0020 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 + + 0x0004 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 + + + • Initialization value for the index (Ireg) register + This is first bit-reversed address DAG1 will output (0x0004) with + bits[15:0] reversed: 0x2000. + + 0x0004 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 + + 0x2000 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 + + + • Correct modify value for Mreg + This is 216-N which evaluates to 28 or 0x0100. + Listing 7-1 shows the code for this example. + + Listing 7-1. Bit-reversed addressing, 8 LSBs + + br_adds: I4=read_in; /* DAG2 pointer to input samples */ + I0=0x0200; /* Base address of bit_rev output */ + M4=1; /* DAG2 increment by 1 */ + M0=0x0100; /* DAG1 increment for 8-bit rev. */ + L4=0; /* Linear data buffer */ + L0=0; /* Linear data buffer */ + CNTR=8; /* 8 samples */ + ENA BIT_REV; /* Enable DAG1 bit reverse mode */ + DO brev UNTIL CE; + AY1=DM(I4+=M4); /* Read samples sequentially */ + + + + +7-20 ADSP-219x Instruction Set Reference + Data Addressing Methods + + + + + brev: DM(I0+=M0)=AY1; /* Write results nonsequentially */ + DIS BIT_REV; /* Disable DAG1 bit reverse mode */ + RTS; /* Return to calling routine */ +read_in: /* input buffer, could be .extern */ + NOP; + + + + + ADSP-219x Instruction Set Reference 7-21 + Data Move Instructions + + + + +Register to Register Move + + Dreg1 = Dreg2 ; + G1reg1 G1reg2 + G2reg1 G2reg2 + G3reg1 G3reg2 + + +FUNCTION + + Moves the contents in the source register to the destination register. The + contents in the source register are right-justified in the destination + register. +SOURCE + + REG2 can be any core register, which are listed in Table 7-1 on page 7-3. + +DESTINATION + + REG1 can be any core register, which are listed in Table 7-1 on page 7-3. + +DETAILS + + For transfers in which the destination register is MR1 or SR1, this operation: + • Sign extends into MR2 or SR2, respectively, the value stored in MR1 or + SR1 if the source is a signed value. + + • Zero-fills MR2 or SR2, respectively, the value stored in MR1 or SR1 if + the source is an unsigned value. + For transfers in which the destination register is smaller than the source + register, this operation right-justifies the value in the destination register, + such that bit 0 maps to bit 0, and truncates the extraneous high-order bits. + When you load the CCODE, ASTAT, or MSTAT register, the effect of the new + value is not available immediately to subsequent instructions that are + + + + +7-22 ADSP-219x Instruction Set Reference + Register to Register Move + + + + + based on it. You must insert the required number of NOP instructions + before using the modified register, or your instruction may execute based + the old value. For more information, see “Register Load Latencies” on + page 7-9). + SSTAT is a read-only register, so SSTAT = reg; is invalid instruction syntax. + +EXAMPLES + + I0 = I4; /* load I0 from I4 */ + CCODE = AY0; /* load CCODE from AY0 */ + DMPG1 = DMPG2; /* load DMPG1 from DMPG2 */ + +SEE ALSO + + • “Type 17: Any Reg «··· Any Reg” on page 9-39 + • “Core Registers” on page 7-2 + • “PX Register” on page 7-4 + • “DAG Registers” on page 7-6 + • “Register Load Latencies” on page 7-9 + • “Direct Register Load” on page 7-27. + + + + + ADSP-219x Instruction Set Reference 7-23 + Data Move Instructions + + + + +Direct Memory Read/Write—Immediate Address + + Dreg = DM() ; + Ireg + Mreg + + + DM() = Dreg ; + Ireg + Mreg + + +FUNCTION + + The memory read operation moves the contents of the memory location + specified by an immediate 16-bit value or label into the destination + register. + The memory write operation moves the contents of the source register + into the memory location specified by an immediate 16-bit value or label. +SOURCE + + Reads The data comes from the memory location specified by an immedi- + ate 16-bit value or label. + Writes The data comes from any register file data (Dreg) register or DAG + Index (Ireg) or DAG Modify (Mreg) register: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + + +DAG1/DAG2 Index and Modify Registers + + I0, I1, I2, I3, I3, I4, I6, I7, M0, M1, M2, M3, M4, M5, M6, M7 + + + + +7-24 ADSP-219x Instruction Set Reference + Direct Memory Read/Write—Immediate Address + + + + +DESTINATION + + Reads The data goes to any register file data (Dreg) register or DAG Index + (Ireg) or DAG Modify (Mreg) register. + Writes The data goes to the memory location specified by an immediate + 16-bit value or label. +DETAILS + + This instruction is typically used by memory-intensive applications that + must make highly efficient use of memory. Applications that use absolute + memory locations need to configure and use them with care. For informa- + tion on using absolute memory locations, see the Linker & Utilities + Manual for ADSP-219x Family DSPs and Assembler Manual for + ADSP-219x Family DSPs. + This instruction transfers 16-bit data only over the DM bus. It does not + write or read from the PX register. + When you load 16-bit data into MR1 or SR1, it is sign-extended into MR2 or + SR2, respectively. + + DMPG1 provides the eight MSBs of the address. For details, see “DAG Page + Registers (DMPGx)” on page 7-7. + When you load a DAG address or page register, the new value is not avail- + able immediately to subsequent instructions that use the register for a + memory access. The DAG address registers have a two-cycle latency. + + ! Because the DAG registers are interlocked, the DSP automatically + inserts up to two stall cycles, as needed, to ensure that subsequent + instructions use the new address value. + For efficient programming, insert two instructions that do not use the + modified register in the two instruction lines immediately following the + + + + + ADSP-219x Instruction Set Reference 7-25 + Data Move Instructions + + + + + load instruction. For example, separate the DMPG1 load and the memory + access with two other DAG register loads: + I0 = buffer; /* Ireg load, data_in defined on page 7-14 */ + NOP; /* any two non-DAG1 instructions */ + NOP; /* can execute here without latencies */ + AX0 = DM(I0 + 0); /* memory access */ + +EXAMPLES + + SI = DM(data_in); /* Dreg load, label defined on page 7-14 */ + I4 = DM(coeff_buffer); + /* Ireg load, label defined on page 7-15 */ + M5 = DM(coeff_buffer); + /* Mreg load, label defined on page 7-15 */ + + DM(coeff_buffer) = AX1; + /* Dreg load, label defined on page 7-15 */ + DM(data_in) = I0; /* Ireg load, label defined on page 7-14 */ + DM(data_in) = M1; /* Mreg load, label defined on page 7-14 */ + +SEE ALSO + + • “Type 3: Dreg/Ireg/Mreg «···» DM/PM” on page 9-22 + • “Direct Addressing” on page 7-12 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + +7-26 ADSP-219x Instruction Set Reference + Direct Register Load + + + + +Direct Register Load + + Dreg = ; + G1reg + G2reg + + + G3reg = ; + + +FUNCTION + + Loads the destination register with immediate data supplied in the instruc- + tion. The data is right-justified in the destination register. + You use the instruction to load a value into the data registers, to + initialize the DAG address registers, to enable or disable interrupts, and to + load certain stack registers. + You use the instruction to load G3reg registers that are less than + 16-bits wide. You load the short registers to set or clear one or more bits in + the status registers, to set up flag conditions, to set the various page regis- + ters, and to load certain stack registers. For a list of the core registers, see + Table 7-1 on page 7-3. +SOURCE + + The instruction accepts a 16-bit immediate value, a pointer to a + 16-bit variable, or LENGTH(16-bit variable). + The instruction accepts only an immediate value ≤12 bits. + + + + + ADSP-219x Instruction Set Reference 7-27 + Data Move Instructions + + + + +DESTINATION + + The instruction places the data in any register group 0, 1, or 2 + register: + +Register Group 0 (Dreg), 1 (G1reg), & 2 (G2reg) Registers + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI, I0, I1, + I2, I3, I3, I4, I6, I7, M0, M1, M2, M3, M4, M5, M6, M7, L0, L1, L2, L3, L4, L5, L6, L7, IMASK, + IRPTL, ICNTL, STACKA, CNTR, LPCSTACKA, SB, SE + + + The instruction places the data in any register group 3 register: + +Register Group 3 (G3reg) Registers (writable) + + ASTAT, MSTAT, LPCSTACKP, CCODE, SE, SB, PX, DMPG1, DMPG2, IOPG, IJPG, STACKP + + + + ! SSTAT is a read-only register. + + + +DETAILS + + When you load 16-bit data into MR1 or SR1, it is sign-extended into MR2 or + SR2, respectively. + + When you use the instruction to load a 16-bit register (SE, or + SB), the destination register’s MSBs are filled with zeros ( 0). + + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + + + + +7-28 ADSP-219x Instruction Set Reference + Direct Register Load + + + + +EXAMPLES + + /* Loading 16-bit registers with 16-bit values: */ + AR = 0x5409; /* Dreg put data */ + I2 = coeff_buffer; + /* Ireg put addr, label defined on page 7-15 */ + M0 = 0x1234; /* Mreg put data */ + L3 = LENGTH(coeff_buffer); + /* put leng, label def’d on page 7-15 */ + + /* Loading 12-bit Reg3 registers with short constants: */ + STACKP = 0; + MSTAT = 0x4; /* Enable AV_latch */ + +SEE ALSO + + • “Type 6: Dreg «··· Data16” on page 9-24 + • “Type 7: Reg1/2 «··· Data16” on page 9-25 + • “Type 33: Reg3 «··· Data12” on page 9-56 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + • “System Control Register Read/Write” on page 7-61 + + + + + ADSP-219x Instruction Set Reference 7-29 + Data Move Instructions + + + + +Indirect 16-bit Memory Read/Write—postmodify + + Dreg = DM(Ireg += Mreg) ; ; + G1reg + G2reg + G3reg + + + DM(Ireg += Mreg) = Dreg ; + G1reg + G2reg + G3reg + + +FUNCTION + + Transfers 16-bit data between memory and any of the core registers (Dreg, + G1reg, G2reg, or G3reg) over the DM bus. The current value in Ireg pro- + vides the address for the memory access. After the access, Ireg is updated + with the sum of its current value and the value in Mreg. +SOURCE + + Reads The 16-bit data comes from the memory location pointed to by the + address in the Ireg, which is modified after the access by the value + in the Mreg: + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + + + + +7-30 ADSP-219x Instruction Set Reference + Indirect 16-bit Memory Read/Write—postmodify + + + + + Writes The 16-bit data comes from any core register, except SSTAT, which + is a read-only register. For information on core registers, see + Table 7-1 on page 7-3. +DESTINATION + + Reads The 16-bit data goes to any core register. For information on core + registers, see Table 7-1 on page 7-3. + Writes The 16-bit data goes to the memory location pointed to by the + address in the Ireg, which is modified after the access by the value + in the Mreg. +DETAILS + + On reads and writes, the data is right-justified in the destination location + (bit0 of the transfer data maps to bit0 of the destination). If the width of + the destination register is less than sixteen bits, the extraneous MSBs of + the data are discarded. On writes from source registers less than sixteen + bits, the missing high-order bits are zero-filled in the memory location. + As shown in Figure 7-2, if this instruction actually references 24-bit data + space at runtime, a read operation loads bits 23:8 from the memory + location into bits 15:0 of a 16-bit register (or bits 23:16 into bits 7:0 of an + 8-bit register, and so on). The low-order bits of the memory location are + ignored. Conversely, a write operation stores bits 15:0 from a 16-bit + source register into bits 23:8 of the 24-bit memory location and zero-fills + the low-order bits 7:0. + To implement a linear data buffer, you must initialize the Ireg’s + corresponding Lreg to 0. For details, see “DAG Registers” on page 7-6. + To implement circular buffer addressing, you must initialize the Ireg’s + corresponding Lreg to the length of the buffer and its corresponding Breg + with the base address of the buffer. For details, see “Circular Data Buffer + Addressing” on page 7-15. + + + + + ADSP-219x Instruction Set Reference 7-31 + Data Move Instructions + + + + + 23 8 7 0 + X W V U T S R Q P O N M L K J I H G F E D C B A Memory + 23:8 + Ignored on reads, + zero-filled on writes + + + + 15 0 + Register X W V U T S R Q P O N M L K J I + 15:0 + + + + + Figure 7-2. 24-bit DM bus transactions + + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. +EXAMPLES + + /* This code segment demonstrates Indirect 16-bit Memory Reads + and Writes with postmodify and incurs no stall cycles: */ + + #define taps 10 + .SECTION/DM seg_data; + .VAR signal_buffer[taps]; + .VAR coeffs[taps]; + .SECTION/PM seg_code; + init: + I0 = coeff_buffer; + + + + +7-32 ADSP-219x Instruction Set Reference + Indirect 16-bit Memory Read/Write—postmodify + + + + + /* Ireg put addr, label def’d on page 7-15 */ + I5 = coeffs; + M0 = 1; + M5 = 1; + L0 = LENGTH(coeff_buffer); + L5 = LENGTH(coeffs); + AX0 = I0; + AX1 = I5; + REG(B0) = AX0; + REG(B5) = AX1; + DMPG1 = 0x0; + DMPG2 = 0x0; + CNTR = taps; + DO clear UNTIL CE; + DM(I5 += M5) = 0; + clear: + DM(I0 += M0) = 0; + +SEE ALSO + + • “Type 32: Any Reg «···» PM/DM” on page 9-54 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + + ADSP-219x Instruction Set Reference 7-33 + Data Move Instructions + + + + +Indirect 16-bit Memory Read/Write—premodify + + Dreg = DM(Ireg + Mreg) ; ; + G1reg + G2reg + G3reg + + + DM(Ireg + Mreg) = Dreg ; + G1reg + G2reg + G3reg + + +FUNCTION + + Transfers 16-bit data between memory and any of the core registers (Dreg, + G1reg, G2reg, or G3reg) over the DM bus. The value in Mreg added to the + value in Ireg provides the address for the memory access. No update + occurs after the access, so Ireg retains its original value. +SOURCE + + Reads The 16-bit data comes from the memory location addressed by the + Ireg plus Mreg; the Ireg retains its original value: + + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + + + + +7-34 ADSP-219x Instruction Set Reference + Indirect 16-bit Memory Read/Write—premodify + + + + + Writes The 16-bit data comes from any core register, except SSTAT, which + is a read-only register. For information on core registers, see + Table 7-1 on page 7-3. +DESTINATION + + Reads The 16-bit data goes to any core register. For information on core + registers, see Table 7-1 on page 7-3. + Writes The 16-bit data goes to the memory location addressed by the Ireg + plus Mreg; the Ireg retains its original value +DETAILS + + On reads and writes, the data is right-justified in the destination location + (bit0 of the transfer data maps to bit0 of the destination). If the width of + the destination register is less than sixteen bits, the overflow MSBs of the + data are discarded. On writes from source registers less than sixteen bits, + the missing high-order bits are zero-filled in the memory location. + If this instruction actually references 24-bit data space at runtime, a read + operation loads bits 23:8 from the memory location into bits 15:0 of a + 16-bit register (or bits 23:16 into bits 7:0 of an 8-bit register, and so on). + The low-order bits of the memory location are ignored. Conversely, a + write operation stores bits 15:0 from a 16-bit source register into bits 23:8 + of the 24-bit memory location and zero-fills the low-order bits 7:0. For + details, see Figure 7-2 on page 7-32. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + + + + + ADSP-219x Instruction Set Reference 7-35 + Data Move Instructions + + + + + You cannot use circular buffering with this instruction, so you must + initialize the Ireg’s corresponding Lreg to 0. For details, see “Indirect + Addressing” on page 7-12. + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. +EXAMPLES + + .SECTION/DM seg_data; + .VAR look_tbl[3] = 0x0, 0x1, 0x2; + + .SECTION/PM seg_code; + cases: + DMPG1 = 0x1; + I0 = look_tbl; + M0 = 0; + M1 = 1; + M2 = 2; + L0 = 0; + AR = AX0 + AX1; + IF EQ JUMP cases_end; + case1: + AY0 = DM(I0 + M0); /* read from premodified location */ + IF GT JUMP cases_end; + case2: + DM(I0 + M1) = AY0; /* write to premodified location */ + cases_end: + NOP; + +SEE ALSO + + • “Type 32: Any Reg «···» PM/DM” on page 9-54 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + +7-36 ADSP-219x Instruction Set Reference + Indirect 24-bit Memory Read/Write—postmodify + + + + +Indirect 24-bit Memory Read/Write—postmodify + + Dreg = PM(Ireg += Mreg) ; ; + G1reg + G2reg + G3reg + + + PM(Ireg += Mreg) = Dreg ; + G1reg + G2reg + G3reg + + +FUNCTION + + Transfers 24-bit data between memory and any of the core registers (Dreg, + G1reg, G2reg, or G3reg) over the PM bus. Employs the PX register to hold + the low-order bits 7:0 while it transfers the high-order bits 23:8 directly + between memory and the destination register. + The current value in Ireg provides the address for the memory access. + After the access, Ireg is updated with the sum of its current value and the + value in Mreg. +SOURCE + + Reads The 24-bit data comes from the memory location pointed to by the + address in the Ireg, which is modified after the access by the value + in the Mreg: + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + + + ADSP-219x Instruction Set Reference 7-37 + Data Move Instructions + + + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + Writes The 24-bit data comes from any core register, except SSTAT, which + is a read-only register. For information on core registers, see + Table 7-1 on page 7-3. +DESTINATION + + Reads The 24-bit data goes to any core register. For information on core + registers, see Table 7-1 on page 7-3. + Writes The 24-bit data goes to the memory location pointed to by the + address in the Ireg, which is modified after the access by the value + in the Mreg. +DETAILS + + Unless this instruction is already in the instruction cache, it causes a + one-cycle stall. + The 8-bit PX register holds the eight low-order bits of 24-bit data + transferring between memory and a register. On reads, it automatically + stores these bits, and on writes, it supplies them. On reads, you must + explicitly move the contents of PX into a data register, and on writes, you + must explicitly load the PX register with the value of the low-order bits. + For details, see “PX Register” on page 7-4. + On reads, the high-order bits 23:8 of the memory location are + right-justified in the destination register (bit8 of the transfer data maps to + bit0 of the destination register). If the width of the destination register is + less than sixteen bits, the overflow MSBs of the data are discarded. For + details, see Figure 7-2 on page 7-32. + On writes, bits 15:0 of the source register are right-justified in the + memory location (bit0 of the transfer data maps to bit8 of the memory + location). If the width of the source register is less than sixteen bits, the + missing high-order bits of the memory location are zero-filled. + + + +7-38 ADSP-219x Instruction Set Reference + Indirect 24-bit Memory Read/Write—postmodify + + + + + If this instruction actually references 16-bit data space at runtime, the PX + register receives eight bits of the adjacent data. On writes, the contents of + the PX register are ignored. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + To implement a linear data buffer, you must initialize the Ireg’s + corresponding Lreg to 0. For details, see “Indirect Addressing” on + page 7-12. + To implement circular buffer addressing, you must initialize the Ireg’s + corresponding Lreg to the length of the buffer and its corresponding Breg + with the base address of the buffer. For details, see “Circular Data Buffer + Addressing” on page 7-15. + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. +EXAMPLES + + #define more_taps 10 + .SECTION/DM seg_dmda; + .VAR dmdata_buffer[more_taps]; + .SECTION/PM seg_pmda; + .VAR pmdata_coeffs[more_taps]; + .SECTION/PM seg_code; + more_init: + I0 = dmdata_buffer; /* dmdag Ireg write/output address */ + I5 = pmdata_coeffs; /* pmdag Ireg read/input address */ + M0 = 1; + M5 = 1; + L0 = LENGTH(dmdata_buffer); + L5 = LENGTH(pmdata_coeffs); + + + + + ADSP-219x Instruction Set Reference 7-39 + Data Move Instructions + + + + + AX0 = I0; + AX1 = I5; + REG(B0) = AX0; + REG(B5) = AX1; + DMPG1 = 0x0; + DMPG2 = 0x0; + CNTR = taps; + SI = 0xB6A3; /* shifter input word */ + DO clear UNTIL CE; + SR1 = PM(I5 += M5); /* read upper 16-bits and post modify */ + SR0 = PX; /* read lower 8-bits from PX */ + SR = SR OR ASHIFT SI BY 3 (HI); /* ashift upper word */ + more_clear: + DM(I0 += M0) = SR0; + /* 16-bit write SR0 & post modify address */ + +SEE ALSO + + • “Type 32: Any Reg «···» PM/DM” on page 9-54 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + +7-40 ADSP-219x Instruction Set Reference + Indirect 24-bit Memory Read/Write—premodify + + + + +Indirect 24-bit Memory Read/Write—premodify + + Dreg = PM(Ireg + Mreg) ; ; + G1reg + G2reg + G3reg + + + PM(Ireg + Mreg) = Dreg ; + G1reg + G2reg + G3reg + + +FUNCTION + + Transfers 24-bit data between memory and any of the core registers (Dreg, + G1reg, G2reg, or G3reg) over the PM bus. Employs the PX register to hold + the low-order bits 7:0 while it transfers the high-order bits 23:8 directly + between memory and the destination register. The value in Mreg added to + the value in Ireg provides the address for the memory access. No update + occurs after the access, so Ireg retains its original value. +SOURCE + + Reads The 24-bit data comes from the memory location addressed by the + Ireg plus Mreg; the Ireg retains its original value: + + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + + + + + ADSP-219x Instruction Set Reference 7-41 + Data Move Instructions + + + + + Writes The 24-bit data comes from any core register, except SSTAT, which + is a read-only register. For information on core registers, see + Table 7-1 on page 7-3. +DESTINATION + + Reads The 24-bit data goes to any core register. For information on core + registers, see Table 7-1 on page 7-3. + Writes The 24-bit data goes to the memory location addressed by the Ireg + plus Mreg; the Ireg retains its original value +DETAILS + + Unless this instruction is already in the instruction cache, it causes a + one-cycle stall. + The 8-bit PX register holds the eight low-order bits of 24-bit data + transferring between memory and a register. On reads, it automatically + stores these bits, and on writes, it supplies them. On reads, you must + explicitly move the contents of PX into a data register, and on writes, you + must explicitly load the PX register with the value of the low-order bits. + For details, see “PX Register” on page 7-4. + On reads, the high-order bits 23:8 of the memory location are + right-justified in the destination register (bit8 of the transfer data maps to + bit0 of the destination register). If the width of the destination register is + less than sixteen bits, the overflow MSBs of the data are discarded. For + details, see Figure 7-2 on page 7-32. + On writes, bits 15:0 of the source register are right-justified in the + memory location (bit0 of the transfer data maps to bit8 of the memory + location). If the width of the source register is less than sixteen bits, the + missing high-order bits of the memory location are zero-filled. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + + + +7-42 ADSP-219x Instruction Set Reference + Indirect 24-bit Memory Read/Write—premodify + + + + + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + You cannot use circular buffering with this instruction, so you must + initialize the Ireg’s corresponding Lreg to 0. For details, see “Indirect + Addressing” on page 7-12. + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. +EXAMPLES + + .SECTION/DM seg_data; + .VAR lookup_tbl[3] = 0x0, 0x1, 0x2; + + .SECTION/PM seg_code; + pmrw_cases: + DMPG1 = 0x1; + I0 = lookup_tbl; + M0 = 0; + M1 = 1; + M2 = 2; + L0 = 0; + AR = AX0 + AX1; + IF EQ JUMP cases_end; + pmrw_case1: + SR1 = PM(I0 + M1); /* pre modify and read upper 16-bits */ + SR0 = PX; /* read lower 8-bits from PX */ + SR = SR OR ASHIFT SI BY 3 (HI); /* ashift upper word */ + IF GT JUMP cases_end; + pmrw_case2: + PX = SR1; /* Load lower 8 bits into PX */ + PM(I0 + M2) = SR0; /* Write all 24 bits from SR0 and PX */ + pmrw_cases_end: + NOP; + + + + + ADSP-219x Instruction Set Reference 7-43 + Data Move Instructions + + + + +SEE ALSO + + • “Type 32: Any Reg «···» PM/DM” on page 9-54 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + +7-44 ADSP-219x Instruction Set Reference + Indirect DAG Register Write (premodify or postmodify), with + DAG Register Move + + + +Indirect DAG Register Write (premodify or +postmodify), with DAG Register Move + + DM(Ireg1 + Mreg1) = Ireg2 , Ireg2 = Ireg1 ; + += Mreg2 Mreg2 + Lreg2 Lreg2 + + +FUNCTION + + Writes the contents of a source address register to memory and loads the + same source address register with a new value—the effective address writ- + ten to memory. Register usage within this instruction has the following + restrictions (shown below graphically): + • The Ireg1 registers must be the same register. + • The Mreg1 register must come from the same DAG as Ireg1. + • The Ireg2, Mreg2, or Lreg2 registers be the same register. + • The Ireg2, Mreg2, or Lreg2 registers must come from the same DAG + as Ireg1, but may not be Ireg1 (Ireg1≠Ireg2). + + All registers + from the Same register + same DAG + Same register + + DM(Ireg1 +/+= Mreg1) = , = Ireg1 ; + + + + NOT the same register + + If the premodify (+) addressing option is used, after the memory access, + the instruction loads the source address register with the modified value of + Ireg (Ireg + Mreg). If the postmodify (+=) addressing option is used, the + + + + + ADSP-219x Instruction Set Reference 7-45 + Data Move Instructions + + + + + instruction loads the source address register with the unmodified value of + Ireg. For details on the indirect addressing options, see “Indirect Address- + ing” on page 7-12. +SOURCE + + Memory write The 16-bit data comes from any DAG (Ireg, Mreg, or + Lreg) register in the same DAG as Ireg1. The source regis- + ter may not be the Ireg1 register. For information on core + registers, see Table 7-1 on page 7-3. + Register load The 16-bit data comes from the Ireg1 register. +DESTINATION + + Memory write For the post-modified access (+=), the 16-bit data goes to + the memory location pointed to by the address in the Ireg, + which is modified after the access by the value in the Mreg. + + For the pre-modified access (+), the 16-bit data goes to the + memory location addressed by the Ireg plus Mreg; the Ireg + retains its original value: + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + Register load The 16-bit data goes to any DAG (Ireg, Mreg, or Lreg) reg- + ister in the same DAG as Ireg1. The destination register + may not be the Ireg1 register. For information on core reg- + isters, see Table 7-1 on page 7-3. + + + + +7-46 ADSP-219x Instruction Set Reference + Indirect DAG Register Write (premodify or postmodify), with + DAG Register Move + + + +DETAILS + + On reads and writes, the data is right-justified in the destination location + (bit0 of the transfer data maps to bit0 of the destination). If the width of + the destination register is less than sixteen bits, the overflow MSBs of the + data are discarded. On writes from source registers less than sixteen bits, + the missing high-order bits are zero-filled in the memory location. + If this instruction actually references 24-bit data space at runtime, a read + operation loads bits 23:8 from the memory location into bits 15:0 of a + 16-bit register (or bits 23:16 into bits 7:0 of an 8-bit register, and so on). + The low-order bits of the memory location are ignored. Conversely, a + write operation stores bits 15:0 from a 16-bit source register into bits 23:8 + of the 24-bit memory location and zero-fills the low-order bits 7:0. For + details, see Figure 7-2 on page 7-32. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + You cannot use circular buffering with the pre-modify addressing (+) form + of this instruction, so you must initialize the Ireg’s corresponding Lreg to + 0. For details, see “Indirect Addressing” on page 7-12. + + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. + + + + + ADSP-219x Instruction Set Reference 7-47 + Data Move Instructions + + + + +EXAMPLES + + /* This routine uses the type 32a instruction to save the + previous frame pointer and allocate a new frame pointer, before + calling C-callable subroutine. */ + + _memalloc: + DM(I4 += M5)=I5, I5=I4; /* save old FP and allocate new FP */ + AX1 = DM(I5 + 1); /* read a 16 bit parameter from stack */ + I2=0xFFFF; /* load preserved register I2 */ + I6=0xFFFF; /* load scratch register I6 */ + DM(I4 += M5) = AX1; /* put argument on stack for call */ + I7=I6; /* save scratch register I6 */ + CALL _malloc; /* call C function malloc */ + + _malloc: + NOP; /* _malloc code here */ + +SEE ALSO + + • “Type 32a: DM«···DAG Reg | DAG Reg«···Ireg” on page 9-55 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + +7-48 ADSP-219x Instruction Set Reference + Indirect Memory Read/Write—immediate postmodify + + + + +Indirect Memory Read/Write—immediate +postmodify + + Dreg = DM(Ireg += ) ; + + + DM(Ireg += ) = Dreg ; + + +FUNCTION + + Transfers 16-bit data between memory and a data register over the DM + bus. The current value in Ireg provides the address for the memory access. + After the access, Ireg is updated with the sum of its current value and the + immediate 8-bit, two’s-complement value supplied in the instruction. +SOURCE + + Reads The contents of a memory location in data space pointed to by + Ireg (I0-I7). + + Writes Any of these data registers: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +DESTINATION + + Reads A data register (same as data registers—write). + Writes The contents of a memory location in data space pointed to by + Ireg (same as read source registers). + +DETAILS + + The immediate value supplied in the instruction is an 8-bit + two’s-complement number. Valid values range from −128 through 127. + + + + ADSP-219x Instruction Set Reference 7-49 + Data Move Instructions + + + + + On reads and writes, the data is right-justified in the destination location + (bit0 of the transfer data maps to bit0 of the destination). + If this instruction actually references 24-bit data space at runtime, a read + operation loads bits 23:8 from the memory location into bits 15:0 of a + 16-bit register (or bits 23:16 into bits 7:0 of an 8-bit register, and so on). + The low-order bits of the memory location are ignored. Conversely, a + write operation stores bits 15:0 from a 16-bit source register into bits 23:8 + of the 24-bit memory location and zero-fills the low-order bits 7:0. For + details, see Figure 7-2 on page 7-32. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + To implement a linear data buffer, you must initialize the Ireg’s + corresponding Lreg to 0. For details, see “Indirect Addressing” on + page 7-12. + To implement circular buffer addressing, you must initialize the Ireg’s + corresponding Lreg with the length of the buffer and its corresponding + Breg with the base address of the buffer. For details, see “Circular Data + Buffer Addressing” on page 7-15. + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. +EXAMPLES + + AX0 = DM(I0 += 0x11); + DM(I6 += 0x08) = MR1; + DM(I2 += −3) = SI; + + + + +7-50 ADSP-219x Instruction Set Reference + Indirect Memory Read/Write—immediate postmodify + + + + +SEE ALSO + + • “Type 29: Dreg «···» DM” on page 9-51 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + + ADSP-219x Instruction Set Reference 7-51 + Data Move Instructions + + + + +Indirect Memory Read/Write—immediate +premodify + + Dreg = DM(Ireg + ) ; + + + DM(Ireg + ) = Dreg ; + + +FUNCTION + + Transfers 16-bit data between memory and a data register over the DM + bus. The immediate 8-bit, two’s-complement value supplied in the + instruction added to the current value in Ireg provides the address for the + memory access. No update occurs after the access, so Ireg retains its orig- + inal value. +SOURCE + + Reads The contents of a memory location in data space, accessed indi- + rectly using an Ireg (I0-I7) and an immediate 8-bit, + two’s-complement value supplied in the instruction. + Writes Any of these data registers: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +DESTINATION + + Reads A data register (same as source data registers). + Writes The contents of a memory location in data space, accessed indi- + rectly with an Ireg (same as source address registers) and + immediate 8-bit, two’s-complement value supplied in the + instruction. + + + + +7-52 ADSP-219x Instruction Set Reference + Indirect Memory Read/Write—immediate premodify + + + + +DETAILS + + The immediate value supplied in the instruction is an 8-bit + twos-complement number. Valid values range from −128 through 127. + On reads and writes, the data is right-justified in the destination location + (bit0 of the transfer data maps to bit0 of the destination). + If this instruction actually references 24-bit data space at runtime, a read + operation loads bits 23:8 from the memory location into bits 15:0 of a + 16-bit register (or bits 23:16 into bits 7:0 of an 8-bit register, and so on). + The low-order bits of the memory location are ignored. Conversely, a + write operation stores bits 15:0 from a 16-bit source register into bits 23:8 + of the 24-bit memory location and zero-fills the low-order bits 7:0. For + details, see Figure 7-2 on page 7-32. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + You cannot use circular buffering with this instruction, so you must + initialize the Ireg’s corresponding Lreg to 0. For details, see “Indirect + Addressing” on page 7-12. + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. +EXAMPLES + + AX0 = DM(I0 + 0x11); + DM(I6 + 0x08) = MR1; + DM(I2 + −3) = SI; + + + + + ADSP-219x Instruction Set Reference 7-53 + Data Move Instructions + + + + +SEE ALSO + + • “Type 29: Dreg «···» DM” on page 9-51 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + • “Secondary DAG Registers” on page 7-8 + • “Register Load Latencies” on page 7-9 + + + + +7-54 ADSP-219x Instruction Set Reference + Indirect 16-bit Memory Write—immediate data + + + + +Indirect 16-bit Memory Write—immediate data + + DM(Ireg += Mreg) = ; + + +FUNCTION + + Writes a 16-bit data value supplied in the instruction to a memory loca- + tion over the DM bus. The current value in Ireg provides the address for + the memory access. After the memory access, Ireg is updated with the + sum of its current value and the value in Mreg. + + ! This instruction is a two-word instruction and requires (at mini- + mum) two cycles to execute. For more information, see “Type 22: + DM/PM «··· Data16” on page 9-45. +SOURCE + + The data comes from a 16-bit number supplied in the + instruction. +DESTINATION + + Memory write The 16-bit data goes to the memory location pointed to by + the address in the Ireg, which is modified after the access + by the value in the Mreg: + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + + + + + ADSP-219x Instruction Set Reference 7-55 + Data Move Instructions + + + + +DETAILS + + The data transferred is right-justified in the memory location (bit0 of the + data maps to bit0 of the location). If this instruction actually accesses + 24-bit data space at runtime, the write operation stores bits 15:0 in bits + 15:0 of the 24-bit memory location and zero-fills the high-order bits + 23:16. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + Setting up a data buffer requires initializing one or more additional + address registers. For details, see “Indirect Addressing” on page 7-12. + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. +EXAMPLES + + DMPG1 = page(0x0); /* selects internal memory */ + I3 = 0x8100; /* selects 16-bit, block 1 */ + M2 = 1; + L3 = 0; + DM(I3 += M2) = 0x7743; /* write data16 to memory */ + +SEE ALSO + + • “Type 22: DM/PM «··· Data16” on page 9-45 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + + + + +7-56 ADSP-219x Instruction Set Reference + Indirect 24-bit Memory Write—immediate data + + + + +Indirect 24-bit Memory Write—immediate data + + PM(Ireg += Mreg) = :24 ; + + +FUNCTION + + Writes a 24-bit data value supplied in the instruction to a memory loca- + tion over the PM bus. The current value in Ireg provides the address for + the memory access. After the memory access, Ireg is updated with the + sum of its current value and the value in Mreg. + + ! This instruction is a two-word instruction and requires (at mini- + mum) two cycles to execute. For more information, see “Type 22: + DM/PM «··· Data16” on page 9-45. +SOURCE + + The 24-bit data comes from a 24-bit number supplied in the + instruction. The :24 after the data directs the assembler to handle + 24-bit data. +DESTINATION + + Memory write The 24-bit data goes to the memory location pointed to by + the address in the Ireg, which is modified after the access + by the value in the Mreg: + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + + + + + ADSP-219x Instruction Set Reference 7-57 + Data Move Instructions + + + + +DETAILS + + The data transferred is right-justified in the memory location (bit0 of the + data maps to bit0 of the location). + If this instruction actually accesses 16-bit data space at runtime, the write + operation stores bits 23:8 in bits 15:0 of the 16-bit memory location and + discards the data’s low-order bits 7:0. For details, see Figure 7-2 on page + 7-32. + A DAG page register, DMPG1 (I3-I0) or DMPG2 (I7-I4), provides the eight + MSBs of the memory address. For details, see “DAG Page Registers + (DMPGx)” on page 7-7. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. + Setting up a data buffer requires initializing one or more additional + address registers. For details, see “Indirect Addressing” on page 7-12. + To perform bit-reversed addressing, you must use DAG1 address registers. + For details, see “Bit-Reversed Addressing” on page 7-17. +EXAMPLES + + DMPG2 = page(0x0); /* selects internal memory */ + I4 = 0x1000; /* selects 24-bit, block 0 */ + M5 = 1; + L4 = 0; + PM(I4 += M5) = 0x3F4512:24; /* write 24-bit data to memory */ + +SEE ALSO + + • “Type 22: DM/PM «··· Data16” on page 9-45 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + + + +7-58 ADSP-219x Instruction Set Reference + External IO Port Read/Write + + + + +External IO Port Read/Write + + Dreg = IO() ; + + + IO() = Dreg ; + + +FUNCTION + + Transfers data between I/O memory space and a data register. +SOURCE + + Reads The contents of a location in I/O memory space specified by the + 10-bit immediate value (or memory-mapped register name) sup- + plied in the instruction. + Writes Any of these data registers: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +DESTINATION + + Reads Any of the data registers (same as write source registers). + Writes The contents of a location in I/O memory space specified by the + 10-bit immediate value (or memory-mapped register name) sup- + plied in the instruction. +DETAILS + + The I/O page register, IOPG, with the 10-bit immediate value supplied in + the instruction generate the 18-bit address required for accessing I/O + memory space. Valid page values (IOPG) are 0-255. Valid location values + + + + + ADSP-219x Instruction Set Reference 7-59 + Data Move Instructions + + + + + (10-bit immediate) are 0-1023. The arrangement of these values to make + an address appears in Figure 7-3. + + 23 16 9 0 + I/O memory space + address bits IOPG Unused 10-bit immediate address + + + + Figure 7-3. Addressing I/O memory space and peripherals + + At power up, the DSP initializes the IOPG register to 0x0. Although initial- + izing the IOPG register is unneccessary unless the data to access is located + on a different page, for good programming practice, we recommend that + you do so whenever you access an external I/O port. To do so, you use the + direct register load instruction (for details, see “Direct Register Load” on + page 7-27). Then you can read or write the external I/O port. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, DMPGx, + or IOPG), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. +EXAMPLES + + #define io_address1 0x1FF /* define 10-bit IO address */ + IOPG = 0x01; /* set IOPG to page 1 */ + AX0 = 0xaaff; /* load AX0 with 16-bit data */ + IO(io_address1) = AX0; /* write data to io_address1 */ + +SEE ALSO + + • “Type 34: Dreg «···» IOreg” on page 9-57 + • The I/O registers are specific to each ADSP-219x DSP. For register + list, see the ADSP-219x/2191 DSP Hardware Reference. + + + + +7-60 ADSP-219x Instruction Set Reference + System Control Register Read/Write + + + + +System Control Register Read/Write + + Dreg = REG() ; + + + REG() = Dreg ; + + +FUNCTION + + Transfers data between an internal system control register and a data + register. +SOURCE + + Reads The contents of a location in system control memory space speci- + fied by the 8-bit immediate value, or register name, supplied in the + instruction: + • DAG Breg B0, B1, B2, or B3 (DAG1 base registers) + B4, B5, B6, or B7 (DAG2 base registers) + + • Sequencer SYSCTL (system control register) + + • Cache control CACTL (cache control register) + + ! Except, thefor system + the DAG base address registers ( – ), + CACTL + B0 B7 , and + SYSCTL + control registers are specific to each ADSP-219x + product. See your ADSP-219x/2191 DSP Hardware Reference for a + complete list of these registers and their addresses. + Writes Any of these data registers: + +Register File + +AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + + + + ADSP-219x Instruction Set Reference 7-61 + Data Move Instructions + + + + +DESTINATION + + Reads Any of the data registers (same as write source registers). + Writes The contents of a location in system control memory space speci- + fied by the 8-bit immediate value, or register mnemonic, supplied + in the instruction (same as source registers). +DETAILS + + System control memory space consists of 256 locations. These locations + are reserved for core-based controls or for peripherals, such as DMA or + serial ports, that interface with the core. For more information, see the + ADSP-219x/2191 DSP Hardware Reference. + You cannot write the system control registers directly. Instead, you must + load a data register, then load the system register from the data register. + When you access a DAG base address register (B0–B7), whether you access + the primary or secondary set depends on bit 6 (SEC_DAG) in the MSTAT reg- + ister. For details, see “Secondary DAG Registers” on page 7-8. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, or + DMPGx), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. +EXAMPLES + + AX0 = 0x0800; /* load data into AX0 */ + REG(B0) = AX0; /* load AX0 into B0 */ + REG(0x0) = AX0; /* same as above */ + +SEE ALSO + + • “Type 35: Dreg «···»Sreg” on page 9-58 + • The system registers are specific to each ADSP-219x DSP. For reg- + ister list, see the ADSP-219x/2191 DSP Hardware Reference. + + + + +7-62 ADSP-219x Instruction Set Reference + Modify Address Register—indirect + + + + +Modify Address Register—indirect + + MODIFY(Ireg += Mreg) ; + + +FUNCTION + + Updates the value of an index register without performing a memory + access. + Sums the value in Ireg with the value in Mreg and writes the result to + Ireg. If you set up circular buffering, this instruction also performs that + logic operation. +SOURCE + + UpdateThe DAG Ireg and Mreg registers specified in the instruction: + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. +DESTINATION + + UpdateThe DAG Ireg specified in the instruction. +DETAILS + + For linear data buffers, you must initialize the Ireg’s corresponding Lreg + to 0. For details, see “Indirect Addressing” on page 7-12. + For circular buffers, you must initialize the Ireg’s corresponding Lreg + with the length of the buffer and its corresponding Breg with the base + + + + + ADSP-219x Instruction Set Reference 7-63 + Data Move Instructions + + + + + address of the buffer. For details, see “Circular Data Buffer Addressing” + on page 7-15. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, DMPGx, + or IOPG), the new value is not available immediately to subsequent instruc- + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. +EXAMPLES + + I2 = 0x2000; + M1 = 1; + L2 =0; + MODIFY(I2 += M1); /* updates I2 with value from M1 */ + /* I2 = 0x2001 */ + +SEE ALSO + + • “Type 21: Modify DagI” on page 9-43 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + + + + +7-64 ADSP-219x Instruction Set Reference + Modify Address Register—direct + + + + +Modify Address Register—direct + + MODIFY(Ireg += ) ; + + +FUNCTION + + Updates the value of an index register without performing a memory + access. + Sums the value in Ireg with the 8-bit, two’s-complement immediate value + supplied in the instruction and writes the result to Ireg. If you set up cir- + cular buffering, this instruction also performs that logic operation. +SOURCE + + The DAG Ireg register and the Imm8 data specified in the + instruction: + • DM/DAG1 I0, I1, I2, or I3 (index registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + +DESTINATION + + The DAG Ireg specified in the instruction. +DETAILS + + For linear data buffers, you must initialize the Ireg’s corresponding Lreg + to 0. For details, see “Indirect Addressing” on page 7-12. + For circular buffers, you must initialize the Ireg’s corresponding Lreg to + the length of the buffer and its corresponding Breg with the base address + of the buffer. For details, see “Circular Data Buffer Addressing” on + page 7-15. + When you load certain registers (CCODE, ASTAT, MSTAT, IJPG, Ireg, DMPGx, + or IOPG), the new value is not available immediately to subsequent instruc- + + + + + ADSP-219x Instruction Set Reference 7-65 + Data Move Instructions + + + + + tions. For information on register latencies, see “Register Load Latencies” + on page 7-9. +EXAMPLES + + I2 = 0x2000; + #define mod_val 0x1 + Nop; + L2 =0; + MODIFY(I2 += mod_val); /* updates I2 with mod_val */ + /* I2 = 0x2001 */ + +SEE ALSO + + • “Type 21a: Modify DagI” on page 9-44 + • “Core Registers” on page 7-2 + • “DAG Registers” on page 7-6 + + + + +7-66 ADSP-219x Instruction Set Reference + \ No newline at end of file diff --git a/docs/9x_multiops.pdf b/docs/9x_multiops.pdf new file mode 100644 index 0000000..e12f156 Binary files /dev/null and b/docs/9x_multiops.pdf differ diff --git a/docs/9x_multiops.txt b/docs/9x_multiops.txt new file mode 100644 index 0000000..51d0d2e --- /dev/null +++ b/docs/9x_multiops.txt @@ -0,0 +1,791 @@ +6 MULTIFUNCTION + INSTRUCTIONS + Figure 6-0. + Table 6-0. + Listing 6-0. + + The instruction set provides multifunction instructions—multiple + instructions within a single instruction cycle. Multifunction instructions + can perform (in a single cycle) computations in parallel with data move + operations. Multifunction instructions are combinations of single instruc- + tions delimited with commas and ended with a semicolon, as in: + AR = AX0 - AY0, AX0 = MR1; /* ALU sub and reg.-to-reg. move */ + + These operations are the basis for all high-performance DSP functions and + take advantage of the DSP’s inherent parallelism. Multifunction opera- + tions include: + • “Compute with Dual Memory Read” on page 6-3 + • “Dual Memory Read” on page 6-7 + • “Compute with Memory Read” on page 6-10 + • “Compute with Memory Write” on page 6-14 + • “Compute with Register to Register Move” on page 6-18 + This chapter describes each of the multifunction instructions and the + order of execution of multifunction operations. + Multifunction instructions combine compute operations with data move + operations. The multifunction combinations have no status flags specifi- + cally associated with them, but the DSP does update the status flags for + the computations that appear within multifunction instructions. For + details, see “Arithmetic Status (ASTAT) Register” on page 2-5. + + + + + ADSP-219x Instruction Set Reference 6-1 + Multifunction Instructions + + + + +Order of Execution of Multifunction Operations + The DSP reads registers and memory at the beginning of the processor + pipeline and writes them at the end of it. Normal instruction syntax, read + from left to right, implies this functional ordering. For example: + a. MR = MR + MX0 * MY0(UU), MX0 = DM(I0 += M0), MY0 = PM(I4 += M4); + b. DM(I0 += M0) = AR, AR = AX0 + AY0; + c. AR = AX0 - AY0, AX0 = MR1; + + This means that, for memory reads, the DSP executes the computation + first, using the current value of the input data registers, and then transfers + new data from memory or from another data register, overwriting the con- + tents of the data registers (a and c). For memory writes, the DSP transfers + the current value from the data register to memory first, and then over- + writes the data register with the result of the computation (b). + Even if you alter the order of the operations in your code, execution + occurs in the correct order; the assembler issues a warning (if enabled), but + results are correct at the opcode level. For example: + MX0 = DM(I0 += M0), MY0 = PM(I4 += M4), MR = MR + MX0 * MY0(UU); + + The altered order of operations appears to reverse the order in which the + DSP executes the operations, but the DSP always executes instructions + using read-first/write-last logic. + The DSP’s read-first/write-last logic enables you to use the same data reg- + ister in more than one multifunction operation. The same data register + can serve as an input operand into the computation and as the destination + or source register for a data move operation. However, except for the com- + pute with memory write instruction, the same register cannot serve as + destination for more than one multifunction operation. Doing so gener- + ates unpredictable and erroneous results. + + + + +6-2 ADSP-219x Instruction Set Reference + Compute with Dual Memory Read + + + + +Compute with Dual Memory Read + + , AX0 = DM( I0 += M0 ), AY0 = PM( I4 += M4 ); + AX1 I1 M1 AY1 I5 M5 + MX0 I2 M2 MY0 I6 M6 + MX1 I3 M3 MY1 I7 M7 + + +FUNCTION + + Combines an ALU or MAC operation with a read from memory over the + 16-bit DM data bus and another read from memory over the 24-bit PM + data bus. The restricted register forms—using XOP and YOP registers, not the + DREG register file—of all ALU or MAC instructions are supported, except + for the MAC saturate instruction and the divide primitives DIVS and DIVQ. + Also, the multifunction ALU and MAC instructions may not use condi- + tional (IF) options. + The compute operation executes first, using the current contents of the + data registers as input operands. Then the memory read operations exe- + cute, overwriting the contents of the destination data registers with new + data from memory. + The destination of both memory read operations is an ALU or MAC data + register. The DM bus read loads an ALU or MAC XOP register, and the + PM bus read loads an ALU or MAC YOP register. The memory data is + always right-justified in the destination data register. +INPUT + + The input operands for the compute operation are specific to the particu- + lar operation. For details, see the compute instruction’s individual + description. + • For MAC operations, see “MAC Instructions” on page 4-1. + • For ALU operations, see “ALU Instructions” on page 3-1. + + + + + ADSP-219x Instruction Set Reference 6-3 + Multifunction Instructions + + + + + Both data move operations use two DAG registers, index (Ireg) and mod- + ify (Mreg), to generate memory addresses—DAG1 registers for the DM bus + access, and DAG2 registers for the PM bus access. For details on DAG reg- + isters and data addressing, see “Data Move Instructions” on page 7-1. + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. +OUTPUT + + The result register for the compute operation is always the computation + unit’s result registers. + AR ALU operations + MR MAC operations + + ! instruction. + is not a MAC result register for this multifunction + SR + + + + The destination register for both data move operations is an ALU or MAC + data register—an XOP register for the DM bus access and a YOP register for + the PM bus access. + XOP register: AX0, AX1, MX0, or MX1 + + YOP register: AY0, AY1, MY0, or MY1 + +STATUS FLAGS + + The status flags generated as a result of the computation depends on the + compute operation the instruction performs.For more information, see + the status flags section of the computation’s reference page. + + + +6-4 ADSP-219x Instruction Set Reference + Compute with Dual Memory Read + + + + +DETAILS + + The memory read operations use register indirect addressing with post- + modify (Ireg += Mreg). For linear indirect addressing, you must initialize + the Lx register of the corresponding Ireg register to 0. For circular indirect + addressing, you must set the buffer’s length and base address with the cor- + responding Lreg and Breg registers. For more information on addressing, + see the ADSP-219x/2191 DSP Hardware Reference. + The DM() reference uses the 16-bit DM data bus, and the PM() reference uses + the 24-bit PM data bus. For PM data moves, the destination data register + receives the sixteen MSBs from 24-bit memory, and the PX register catches + the eight LSBs. To use all twenty-four bits of the memory data, you must + transfer the eight LSBs from PX to another data register. Otherwise, the + eight LSBs will be lost. + The address of the access, not the PM() or DM() reference, selects the mem- + ory bank. So, the DM reference could access 24-bit memory, and the PM + reference could access 16-bit memory. DM reads of 24-bit memory result in + the specified data register receiving bits 23:8 from memory. PM reads of + 16-bit memory result in the specified data register receiving bits 23:8 from + memory. When the PX register is loaded using a 16-bit memory access (PM + reference to 16-bit memory or DM reference to 24-bit memory), the DSP + clears (=0)the 8-LSBs of PX. + This multifunction instruction requires the DSP to fetch three items from + memory: the instruction and two data words. The number of cycles + required to execute it depends on whether the instruction generates bus + conflicts: + +Execution Conditions + + 1 cycle If the instruction is already cached and the data are from different memory banks + + + + + ADSP-219x Instruction Set Reference 6-5 + Multifunction Instructions + + + + +Execution Conditions + + 2 cycles If only one bus conflict occurs—data vs. data or instruction vs. data + + 3 cycles If two bus conflicts occur—instruction vs. data vs. data + + +EXAMPLES + + AR = AX0 - AY0, + MX1 = DM(I3 += M0), + MY1 = PM(I5 += M4); /* sub and dual read */ + + AR = AX0 + AY0, + MX0 = DM(I1 += M0), + MY0 = PM(I4 += M4); /* add and dual read */ + + MR = MX0 * MY0 (SS), + MX0 = DM(I2 += M2), + MY0 = PM(I7 += M7); /* mult and dual read */ + +SEE ALSO + + • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21 + • “ALU Instructions” on page 3-1. + • “MAC Instructions” on page 4-1. + • “Arithmetic Status (ASTAT) Register” on page 2-5 + + + + +6-6 ADSP-219x Instruction Set Reference + Dual Memory Read + + + + +Dual Memory Read + + AX0 = DM( I0 += M0 ) , AY0 = PM( I4 += M4 ) ; + AX1 I1 M1 AY1 I5 M5 + MX0 I2 M2 MY0 I6 M6 + MX1 I3 M3 MY1 I7 M7 + + +FUNCTION + + Performs two memory read operations, one over the 16-bit DM data bus + and the other over the 24-bit PM data bus. + Each read operation moves the contents of the specified memory location + to its respective destination register. The destination of both memory read + operations is an ALU or MAC data register. The DM bus read loads an ALU + or MAC DREGx register, and the PM bus read loads an ALU or MAC DREGy + register. The memory data is always right-justified in the destination data + register. +INPUT + + Both data move operations use two DAG registers, index (Ireg) and mod- + ify (Mreg), to generate memory addresses—DAG1 registers for the DM bus + access, and DAG2 registers for the PM bus access. For details on DAG reg- + isters and data addressing, see “Data Move Instructions” on page 7-1. + • DM/DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • PM/DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. + + + + + ADSP-219x Instruction Set Reference 6-7 + Multifunction Instructions + + + + +OUTPUT + + The destination register for both data move operations is an ALU or MAC + data register—an XOP register for the DM bus access and a YOP register for + the PM bus access. + XOP AX0, AX1, MX0, or MX1 + + YOP AY0, AY1, MY0, or MY1 + +STATUS FLAGS + + None affected. +DETAILS + + The memory read operations use register indirect addressing with post- + modify (Ireg += Mreg). For linear indirect addressing, you must initialize + the Lreg register of the corresponding Ireg register to 0. For circular indi- + rect addressing, you must set the buffer’s length and base address with the + corresponding Lreg and Breg registers. For more information on address- + ing, see the ADSP-219x/2191 DSP Hardware Reference. + The DM reference uses the 16-bit DM data bus, and the PM reference uses the + 24-bit PM data bus. For PM data moves, the destination data register + receives the sixteen MSBs from 24-bit memory, and the PX register catches + the eight LSBs. To use all twenty-four bits of the memory data, you must + transfer the eight LSBs from PX to another data register. Otherwise, the + eight LSBs will be lost. + The address of the access, not the PM() or DM() reference, selects the mem- + ory bank. So, the DM() reference could access 24-bit memory, and the PM() + reference could access 16-bit memory. DM reads of 24-bit memory result in + the specified data register receiving bits 23:8 from memory. PM reads of + 16-bit memory result in the specified data register receiving bits 23:8 from + memory. When the PX register is loaded using a 16-bit memory access (PM + reference to 16-bit memory or DM reference to 24-bit memory), the DSP + clears (=0)the 8-LSBs of PX. + + + +6-8 ADSP-219x Instruction Set Reference + Dual Memory Read + + + + + This multifunction instruction requires the DSP to fetch three items from + memory: the instruction and two data words. The number of cycles + required to execute it depends on whether the instruction generates bus + conflicts: + +Execution Conditions + +1 cycle If the instruction is already cached and the data are from different memory banks + +2 cycles If only one bus conflict occurs—data vs. data or instruction vs. data + +3 cycles If two bus conflicts occur—instruction vs. data vs. data + + +EXAMPLES + + MX0 = DM(I0 += M0), + MY0 = PM(I5 += M4); /* dual read */ + + AX1 = DM(I3 += M0), + AY1 = PM(I6 += M4); /* dual read */ + +SEE ALSO + + • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21 + + + + + ADSP-219x Instruction Set Reference 6-9 + Multifunction Instructions + + + + +Compute with Memory Read + + , DREG = DM ( I0 += M0 ) ; + I1 M1 + PM + I2 M2 + I3 M3 + I4 M4 + I5 M5 + I6 M6 + I7 M7 + + +FUNCTION + + Combines an ALU, MAC, or shifter operation with a 16-bit read from + memory over the DM (data memory) bus. The restricted register forms— + using XOP and YOP registers, not the DREG register file—of all ALU, MAC, or + Shifter instructions are supported, except for the MAC saturate instruc- + tion, the divide primitives DIVS and DIVQ, and Shift immediate. Also, the + multifunction ALU, MAC, and Shifter instructions may not use condi- + tional (IF) options. + The compute operation executes first, using the current contents of the + data registers as input operands. Then the memory read operation exe- + cutes, overwriting the contents of the destination data register with new + data from memory. + The read operation moves the contents of the memory location to the + specified destination register. The destination of the memory read opera- + tion is an ALU, MAC, or shifter data register. The memory data is always + right-justified in the destination data register. +INPUT + + Valid input operands for the compute depend on the operation’s compu- + tation unit. For more information, see the input descriptions in “ALU + Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter + Instructions” on page 5-1. + + + + +6-10 ADSP-219x Instruction Set Reference + Compute with Memory Read + + + + + The data move operation uses two DAG registers, index (Ireg) and mod- + ify (Mreg), to generate memory addresses. Regardless of which DAG + registers are used, all accesses occur over the DM bus. For details on DAG + registers and data addressing, see “Data Move Instructions” on page 7-1. + • DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. +OUTPUT + + The result register for the compute operation is always the computation + unit’s result or feedback register. + AR/AF ALU operations + MR/SR MAC operations + SR/SE Shifter operations + The destination register for the data move operation is any register file + data register. You can use any of these data registers for the DREG + destination: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +STATUS FLAGS + + The status flags generated as a result of the computation depends on the + compute operation the instruction performs.For more information, see + the status flags section of the computation’s reference page. + + + + ADSP-219x Instruction Set Reference 6-11 + Multifunction Instructions + + + + +DETAILS + + The memory read operation uses indirect addressing with postmodify + (Ireg += Mreg) and always accesses 16-bit data over the DM bus. For linear + indirect addressing, you must initialize the Lx register of the correspond- + ing Ireg register to 0. For circular indirect addressing, you must set the + buffer’s length and base address with the corresponding Lreg and Breg + registers. For more information on addressing, see the ADSP-219x/2191 + DSP Hardware Reference. + Since the data accesses occur over the DM data bus only, the PM() and DM() + references are semantically identical in this instruction. The address of the + access selects the memory bank, so this instruction could access 24-bit + memory. If so, the specified data register receives bits 23:8 from memory. + Since the PM() reference does not activate the PM data bus, the PX register is + not filled with any data. + This multifunction instruction requires the DSP to fetch two items from + memory: the instruction and one data word. The number of cycles + required to execute this instruction depends on whether it generates a bus + conflict: + +Execution Conditions + + 1 cycle If no bus conflict occurs. + + 2 cycles If an instruction vs. data conflict occurs on the bus + + +EXAMPLES + + AR = AX0 - AY1 + C - 1, + AX0 = DM(I1 += M0); /* ALU operation and mem read */ + + MR = MX1 * MY0 (SS), + SR1 = PM(I4 += M4); /* MAC operation and mem read */ + + AR = 3; SE = AR; /* shift code, lshift 3 bits */ + + + + +6-12 ADSP-219x Instruction Set Reference + Compute with Memory Read + + + + + SI = 0xB6A3; /* value of hi word of input */ + SR = ASHIFT SI (HI), + SI = DM(I0 += M0); /* ashift hi word and mem read */ + + AR = 3; SE = AR; /* shift code lshift 3 bits */ + SI = 0x765D; /* value of lo word of input */ + SR = SR OR LSHIFT SI (LO), + SI = DM(I0 += M0); /* lshift lo word and mem read */ + +SEE ALSO + + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “ALU Instructions” on page 3-1 + • “MAC Instructions” on page 4-1 + • “Shifter Instructions” on page 5-1 + • “Arithmetic Status (ASTAT) Register” on page 2-5 + + + + + ADSP-219x Instruction Set Reference 6-13 + Multifunction Instructions + + + + +Compute with Memory Write + + DM ( I0 += M0 ) = DREG , ; + I1 M1 + PM + I2 M2 + I3 M3 + I4 M4 + I5 M5 + I6 M6 + I7 M7 + + +FUNCTION + + Combines an ALU, MAC, or shifter operation with a 16-bit write to + memory over the DM (data memory) bus. The restricted register forms— + using XOP and YOP registers, not the DREG register file—of all ALU, MAC, + and Shifter instructions are supported, except for the MAC saturate + instruction, the divide primitives DIVS and DIVQ, and Shift immediate. + Also, the multifunction ALU, MAC, and Shifter instructions may not use + conditional (IF) options. + The write operation executes first, transferring the current contents of the + data register to the specified memory location. Then the compute opera- + tion executes, overwriting the contents of the destination data register + with the result. + The source of data for the memory write operation is an ALU, MAC, or + shifter result or feedback register. The data is always right-justified in the + destination memory location. +INPUT + + Valid input operands for the compute depend on the operation’s compu- + tation unit. For more information, see the input descriptions in “ALU + Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter + Instructions” on page 5-1. + + + + +6-14 ADSP-219x Instruction Set Reference + Compute with Memory Write + + + + + The data move operation uses two DAG registers, index (Ireg) and mod- + ify (Mreg), to generate memory addresses. Regardless of which DAG + registers are used, all accesses occur over the DM bus. For details on DAG + registers and data addressing, see “Data Move Instructions” on page 7-1. + • DAG1 I0, I1, I2, or I3 (index registers) + M0, M1, M2, or M3 (modify registers) + + • DAG2 I4, I5, I6, or I7 (index registers) + M4, M5, M6, or M7 (modify registers) + + + ! You can use any index register with any modify register from the + same DAG. You cannot pair a DAG1 register with a DAG2 register. +OUTPUT + + The destination register for the compute operation is always the computa- + tion unit’s result or feedback register. + AR/AF ALU operations + MR/SR MAC operations + SR/SE Shifter operations + The source register for the data move operation is any register file data + register. You can use any of these data registers for the DREG source: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +STATUS FLAGS + + The status flags generated as a result of the computation depends on the + compute operation the instruction performs.For more information, see + the status flags section of the computation’s reference page. + + + + + ADSP-219x Instruction Set Reference 6-15 + Multifunction Instructions + + + + +DETAILS + + The memory write operation uses indirect addressing with postmodify + (Ireg += Mreg) and always transfers 16-bit data over the DM bus. For linear + indirect addressing, you must initialize the Lreg register of the corre- + sponding Ireg register to 0. For circular indirect addressing, you must set + the buffer’s length and base address with the corresponding Lreg and Breg + registers. For more information on addressing, see the ADSP-219x/2191 + DSP Hardware Reference. + Since transfers occur over the DM data bus only, the PM() and DM() refer- + ences are semantically identical in this instruction. The address of the + access selects the memory bank, so this instruction could access 24-bit + memory. If so, the operation writes bits 15:0 from the specified data regis- + ter to bits 23:8 of the specified memory location. Since the PM() reference + does not activate the PM data bus, the PX register does not supply any data. + This multifunction instruction requires the DSP to fetch one item from + memory and write one item to memory: the instruction and one data + word. The number of cycles required to execute the instruction depends + on whether it generates a bus conflict: + +Execution Conditions + + 1 cycle If no bus conflict occurs. + + 2 cycles If an instruction vs. data conflict occurs on the bus + + + Except for SR2, you can use the same data register in both the compute + and memory write operations—as the result register for the computation + and as the source register for the data move operation. +EXAMPLES + + DM(I1 += M0) = AX0, + AR = AX0 - AY1 + C - 1; /* mem write and ALU operation */ + + + + +6-16 ADSP-219x Instruction Set Reference + Compute with Memory Write + + + + + PM(I4 += M4) = SR1, + MR = MX1 * MY0 (SS); /* mem write and MAC operation */ + + AR = 3; SE = AR; /* shift code, lshift 3 bits */ + SI = 0xB6A3; /* value of hi word of input */ + DM(I0 += M0) = SI, + SR = ASHIFT SI (HI); /* mem write and ashift hi word */ + + AR = 3; SE = AR; /* shift code lshift 3 bits */ + SI = 0x765D; /* value of lo word of input */ + DM(I0 += M0) = SI, + SR = SR OR LSHIFT SI (LO); /* mem write and lshift lo word */ + +SEE ALSO + + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “ALU Instructions” on page 3-1 + • “MAC Instructions” on page 4-1 + • “Shifter Instructions” on page 5-1 + • “Arithmetic Status (ASTAT) Register” on page 2-5 + + + + + ADSP-219x Instruction Set Reference 6-17 + Multifunction Instructions + + + + +Compute with Register to Register Move + + , DREG1 = DREG2 ; + + + + +FUNCTION + + Combines an ALU, MAC, or shifter operation with a register to register + move. The restricted register forms—using XOP and YOP registers, not the + DREG register file—of all ALU, MAC, and Shifter instructions are sup- + ported, except for the MAC saturate instruction, the divide primitives + DIVS and DIVQ, and Shift immediate. Also, the multifunction ALU, MAC, + and Shifter instructions may not use conditional (IF) options. + The compute operation executes first, using the current contents of the + data register. Then the data move executes, overwriting the contents of the + destination data register with the contents of the source register. + The source and destination of the data move operation is an ALU, MAC, + or shifter data register. The transferred data is always right-justified in the + destination data register. +INPUT + + Valid input operands for the compute depend on the operation’s compu- + tation unit. For more information, see the input descriptions in “ALU + Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter + Instructions” on page 5-1. + + + + +6-18 ADSP-219x Instruction Set Reference + Compute with Register to Register Move + + + + +OUTPUT + + The result register for the compute operation is always the computation + unit’s result or feedback register. + AR/AF ALU operations + MR/SR MAC operations + SR/SE Shifter operations + The source (DREG2) and destination (DREG1) registers for the data move + operation are any register file data registers. You can use any of these data + registers for the DREG source and destination: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +STATUS FLAGS + + The status flags generated as a result of the computation depends on the + compute operation the instruction performs. For more information, see + the status flags section of the computation’s reference page. +DETAILS + + Except for SR2, you can use the same data register in both the compute + and data move operations—as the result register for the computation and + as the source register for the data move operation. + If you use AR as the source and destination in the data move operation + (AR = AR), the compute operation generates status only—no computation + results. For more information, see “Generate ALU Status Only: NONE” + on page 3-44. + + + + + ADSP-219x Instruction Set Reference 6-19 + Multifunction Instructions + + + + +EXAMPLES + + AR = AX1 + AY1, MX0 = AR; /* add and reg.-to-reg. move */ + + MR = MX1 * MY0 (US), MY0 = AR; /* mult and reg.-to-reg. move */ + + AR = 3; SE = AR; /* shift code, lshift 3 bits */ + SI = 0xB6A3; /* value of hi word of input */ + SR = ASHIFT SI (HI), + SI = MR0; /* ashift hi word reg move */ + +SEE ALSO + + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26 + • “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36 + • “ALU Instructions” on page 3-1 + • “MAC Instructions” on page 4-1 + • “Shifter Instructions” on page 5-1 + • “Arithmetic Status (ASTAT) Register” on page 2-5 + + + + +6-20 ADSP-219x Instruction Set Reference + \ No newline at end of file diff --git a/docs/9x_opcodes.pdf b/docs/9x_opcodes.pdf new file mode 100644 index 0000000..c994f03 Binary files /dev/null and b/docs/9x_opcodes.pdf differ diff --git a/docs/9x_opcodes.txt b/docs/9x_opcodes.txt new file mode 100644 index 0000000..725970e --- /dev/null +++ b/docs/9x_opcodes.txt @@ -0,0 +1,2178 @@ +9 INSTRUCTION OPCODES + Figure 9-0. + Table 9-0. + Listing 9-0. + + + + This chapter lists and describes the opcodes that defines each of the + instructions in the ADSP-219x’s instruction set. This information is use- + ful for debugging programs. + This chapter covers the following topics: + • “Opcode Mnemonics” on page 9-1 + • “Opcode Definitions” on page 9-20 + + +Opcode Mnemonics + This section lists, describes, and gives the numeric value for each opcode + mnemonic. + + Table 9-1. Opcode mnemonics + +Mnemonic Description Details + +AMF Specifies an ALU or multiplier operation. page 9-8 + +AS Specifies whether ALU saturation mode is page 9-40 + 0 = disabled + 1 = enabled + +B Specifies whether branch is page 9-32 + page 9-41 + 0 = immediate + page 9-42 + 1 = delayed + + + + + ADSP-219x Instruction Set Reference 9-1 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +BIT Specifies which interrupt to enable or disable (0–15). page 9-60 + +BO Specifies whether the supplied 4-bit constant in a type 9 instruction is page 9-12 + page 9-27 + 01 = as is + 11 = negated + +BR Specifies whether bit-reverse addressing on DAG1 is page 9-40 + 0 = disabled + 1 = enabled + +BSR Specifies whether the secondary DAG address registers are page 9-40 + 0 = disabled + 1 = enabled + +C Specifies whether a software interrupt is page 9-60 + 0 = set + 1 = cleared + +CC Specifies the two LSBs of a 4-bit constant value in a type 9 instruction. page 9-12 + page 9-27 + +CF Specifies whether to flush the instruction cache page 9-50 + 0 = No flush + 1 = flush + +COND Specifies one of the condition codes on which to base execution of the page 9-11 + instruction. + + + + +9-2 ADSP-219x Instruction Set Reference + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +D Specifies the direction of a data move. page 9-22 + page 9-35 + 0 = read + page 9-51 + 1 = write page 9-54 + page 9-57 + page 9-58 + +DD Specifies a destination data register for a DM bus transfer. page 9-21 + 00 = AX0 + 01 = AX1 + 10 = MX0 + 11 = MX1 + +DDREG Specifies a destination register for a register-to-register move operation. page 9-13 + +DREG Specifies an unrestricted data register (REG0 only). page 9-13 + +DMI Specifies a DAG index address register (I0–I3) for a DM bus transfer. page 9-18 + page 9-21 + +DMM Specifies a DAG modify address register (M0–M3) for a DM bus trans- page 9-18 + fer. page 9-21 + +DRGP Specifies a destination register group. page 9-39 + 00 = REG0 + 01 = REG1 + 10 = REG2 + 11 = REG3 + +DRL Specifies two MSBs of DREG data register address. page 9-13 + +DRU Specifies two LSBs of DREG data register address. page 9-13 + +Exponent Specifies an 8-bit, two’s-complement shift value. page 9-37 + + + + + ADSP-219x Instruction Set Reference 9-3 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +G Specifies a DAG register group. page 9-17 + 0 = DAG1 + 1 = DAG2 + +IREG/MREG Specifies DAG index and modify registers (I0–I7, M0–M7). page 9-18 + +I Specifies DAG index register (I0–I7). page 9-17 + +Idle Value Specifies a 4-bit value that defines an internal clock divisor. page 9-53 + +INT Specifies whether interrupts are globally page 9-40 + 0 = disabled + 1 = enabled + +LPP Specifies push/pop of the loop stacks. page 9-50 + 0 = disabled + 1 = enabled + +M Specifies a DAG modify register. page 9-17 + +MM Specifies whether MAC integer mode is page 9-40 + 0 = disabled + 1 = enabled + +MOD DATA Specifies an 8-bit, two’s-complement immediate data value. page 9-44 + page 9-51 + +MS Specifies memory bus for a memory data transfer page 9-54 + 0 = 16-bit DM bus + 1 = 24-bit PM bus + + + + +9-4 ADSP-219x Instruction Set Reference + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +OL Specifies whether ALU overflow mode is page 9-40 + 0 = disabled + 1 = enabled + +PD Specifies a destination data register for a PM bus transfer. page 9-21 + 00 = AY0 + 01 = AY1 + 10 = MY0 + 11 = MY1 + +PMI Specifies a DAG index address register (I4–I7) for a PM bus transfer. page 9-18 + +PMM Specifies a DAG modify address register (M4–M7) for a PM bus trans- page 9-18 + fer. + +PPP Specifies push/pop of the PC stack. page 9-50 + 0 = disabled + 1 = enabled + +Q Specifies the RTI mode. page 9-42 + 0 = normal + 1 = single-step + +R Specifies a result register. page 9-49 + 0 = MR register + 1 = SR register + +REG Specifies a core register of RGPx. page 9-13 + +REG1 Specifies a register group 1 register page 9-13 + page 9-25 + + + + + ADSP-219x Instruction Set Reference 9-5 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +REG2 Specifies a register group 2 register page 9-13 + page 9-25 + +REG3 Specifies a register group 3 register page 9-13 + page 9-56 + +RGP Specifies a register group. page 9-13 + 00 = REG0 + 01 = REG1 + 10 = REG2 + 11 = REG3. + +S Specifies the branch type. page 9-32 + page 9-41 + 0 = jump + 1 = call + +SDREG Specifies the source data register for a data move operation. page 9-13 + +SF Specifies a shift function. page 9-15 + +SPP Specifies push/pop of the status stack. page 9-50 + 0 = disabled + 1 = enabled + +SR Specifies whether the secondary data registers are page 9-40 + 0 = disabled + 1 = enabled + + + + +9-6 ADSP-219x Instruction Set Reference + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +SRGP Specifies a source register group for a data move operation. page 9-39 + 00 = REG0 + 01 = REG1 + 10 = REG2 + 11 = REG3 + +SWCD Specifies a 4-bit nonfunctional value used by ADI tools only. page 9-52 + +T Specifies the return type. page 9-42 + 0 = RTS + 1 = RTI + +TERM Specifies the terminating condition for the type 11 instruction. page 9-34 + 1110 = NOT CE + 1111 = TRUE + +TI Specifies whether the timer is page 9-40 + 0 = disabled + 1 = enabled + +U Specifies whether the DAG index register is page 9-54 + 0 = premodified with no update + 1 = postmodified with update + +XOP Specifies a restricted data register used to supply the x operand value in page 9-19 + a multifunction or conditional instruction. + +XREG Specifies the source register (REG0) in a shift function. page 9-13 + + + + + ADSP-219x Instruction Set Reference 9-7 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +Y0 Specifies whether the source of the x-operand is page 9-11 + 0 = data register + 1 = 0 (explicit value) + +YOP Specifies a restricted data register used to supply the y operand value in page 9-19 + a multifunction or conditional instruction. + +YREG Specifies the destination register (REG0) in a shift function. page 9-13 + page 9-11 + +YY Specifies the two MSBs of a 4-bit constant value in a type 9 instruc- page 9-12 + tion. page 9-27 + +Z Specifies a result or feedback register page 9-23 + page 9-26 + 0 = result register + page 9-27 + 1 = feedback register page 9-11 + + +ALU or Multiplier Function (AMF) Codes + Table 9-2 on page 9-9 lists the AMF codes used by these instruction types: + • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21 + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26 + • “Type 9: Compute” on page 9-27 + + + + +9-8 ADSP-219x Instruction Set Reference + Table 9-2. ALU/multiplier function (AMF) codes + +Code Function Description + +Multiplier functions + +00000 NOP No operation + +00001 X * Y (RND) Multiply + +00010 MR + X * Y (RND) Multiply and accumulate + +00011 MR – X * Y (RND) Multiply and subtract + +00100 X * Y (SS) Multiply + +00101 X * Y (SU) Multiply + +00110 X * Y (US) Multiply + +00111 X * Y (UU) Multiply + +01000 MR + X * Y (SS) Multiply and accumulate + +01001 MR + X * Y (SU) Multiply and accumulate + +01010 MR + X * Y (US) Multiply and accumulate + +01011 MR + X * Y (UU) Multiply and accumulate + +01100 MR – X * Y (SS) Multiply and subtract + +01101 MR – X * Y (SU) Multiply and subtract + +01110 MR – X * Y (US) Multiply and subtract + +01111 MR – X * Y (UU) Multiply and subtract + +(RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned; +(US) =x operand unsigned, y operand signed; (UU) = both operands unsigned + + + + + ADSP-219x Instruction Set Reference 9-9 + Instruction Opcodes + + + + + Table 9-2. ALU/multiplier function (AMF) codes (Cont’d) + +Code Function Description + +ALU functions + +10000 Y PASS/CLEAR + +10001 Y+1 PASS + +10010 X+Y+C Add with carry + +10011 X+Y Add + +10100 NOT Y Negate + +10101 –Y PASS + +10110 X–Y+C–1 Subtract (X–Y) with borrow + +10111 X–Y Subtract + +11000 Y–1 PASS + +11001 Y–X Subtract + +11010 Y–X+C–1 Subtract (Y–X) with borrow + +11011 NOT X Negate + +11100 X AND Y AND/test bit,clear bit + +11101 X OR Y OR/set bit + +11110 X XOR Y XOR/toggle bit + +11111 ABS X Absolute value + + (RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned; + (US) =x operand unsigned, y operand signed; (UU) = both operands unsigned + + + + +9-10 ADSP-219x Instruction Set Reference + Condition Codes + Table 9-3 on page 9-11 lists the condition codes used by these instruction + types: + • “Type 9: Compute” on page 9-27 + • “Type 10: Direct Jump” on page 9-32 + • “Type 16: Shift Reg0” on page 9-38 + • “Type 19: Indirect Jump/Call” on page 9-41 + • “Type 20: Return” on page 9-42 + • “Type 36: Long Jump/Call” on page 9-59 + • “Type 11: Do ··· Until” on page 9-34 + uses NOT CE and TRUE only for the terminating condition. + + Table 9-3. Condition codes + +Code Condition Description + +0000 EQ Equal to 0 (= 0) + +0001 NE Not equal to 0 (≠ 0) + +0010 GT Greater than 0 (>0) + +0011 LE Less than or equal to 0 (≤0) + +0100 LT Less than 0 (<0) + +0101 GE Greater than or equal to 0 (≥0) + +0110 AV ALU overflow + +0111 NOT AV Not ALU overflow + + + + + ADSP-219x Instruction Set Reference 9-11 + Instruction Opcodes + + + + + Table 9-3. Condition codes (Cont’d) + +Code Condition Description + +1000 AC ALU carry + +1001 NOT AC Not ALU carry + +1010 SWCOND CCODE register condition + +1011 NOT SWCOND Not CCODE register condition + +1100 MV MAC overflow + +1101 NOT MV Not MAC overflow + +1110 NOT CE Counter not expired + +1111 TRUE Always true + + +Constant Codes + Table 9-4 lists the valid constants used by “Type 9: Compute” on + page 9-27. As shown, the YY/CC bits determine the constant value and the + BO bits determine the sign of the value. + + + Table 9-4. Constants + +Code Decimal / Hex Decimal / Hex + +YY CC BO = 01 BO = 11 + + 00 00 1 / 0x0001 −2 / 0xFFFE + + 00 01 2 / 0x0002 −3 / 0xFFFD + + 00 10 4 / 0x0004 −5 / 0xFFFB + + 00 11 8 / 0x0008 −9 / 0xFFF7 + + + + +9-12 ADSP-219x Instruction Set Reference + Table 9-4. Constants (Cont’d) + +Code Decimal / Hex Decimal / Hex + +YY CC BO = 01 BO = 11 + + 01 00 16 / 0x0010 −17 / 0xFFEF + + 01 01 32 / 0x0020 −33 / 0xFFDF + + 01 10 64 / 0x0040 −65 / 0xFFBF + + 01 11 128 / 0x0080 −129 / 0xFF7F + + 10 00 256 / 0x0100 −257 / 0xFEFF + + 10 01 512 / 0x0200 −513 / 0xFDFF + + 10 10 1024 / 0x0400 −1025 / 0xFBFF + + 10 11 2048 / 0x0800 −2049 / 0xF7FF + + 11 00 4096 / 0x1000 −4097 / 0xEFFF + + 11 01 8192 / 0x2000 −8193 / 0xDFFF + + 11 10 16384 / 0x4000 −16385 / 0xBFFF + + 11 11 −32768 / 0x8000 +32767 / 0x7FFF + + +Core Register Codes + Table 9-5 on page 9-14 list the core registers and their addresses. The + complete address of any individual register is formed by appending the + register’s address bits to its RGP bits, so, for example, the address of the I2 + register is 010010. The opcode mnemonics DREG, DDREG, SDREG, XREG, and + YREG and the following instruction types reference these registers by their + address bits: + • “Type 3: Dreg/Ireg/Mreg «···» DM/PM” on page 9-22 + + + + ADSP-219x Instruction Set Reference 9-13 + Instruction Opcodes + + + + + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 6: Dreg «··· Data16” on page 9-24 + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26 + • “Type 9: Compute” on page 9-27 + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36 + • “Type 15: Shift Data8” on page 9-37 + • “Type 16: Shift Reg0” on page 9-38 + • “Type 17: Any Reg «··· Any Reg” on page 9-39 + • “Type 34: Dreg «···» IOreg” on page 9-57 + • “Type 35: Dreg «···»Sreg” on page 9-58 + + Table 9-5. Core registers + +RGP/Address Register Groups (RGP) + +Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3) + +0000 AX0 I0 I4 ASTAT + +0001 AX1 I1 I5 MSTAT + +0010 MX0 I2 I6 SSTAT + +0011 MX1 I3 I7 LPSTACKP + +0100 AY0 M0 M4 CCODE + +0101 AY1 M1 M5 SE + +0110 MY0 M2 M6 SB + + + + +9-14 ADSP-219x Instruction Set Reference + Table 9-5. Core registers (Cont’d) + +RGP/Address Register Groups (RGP) + +Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3) + +0111 MY1 M3 M7 PX + +1000 MR2 L0 L4 DMPG1 + +1001 SR2 L1 L5 DMPG2 + +1010 AR L2 L6 IOPG + +1011 SI L3 L7 IJPG + +1100 MR1 IMASK Reserved Reserved + +1101 SR1 IRPTL Reserved Reserved + +1110 MR0 ICNTL CNTR Reserved + +1111 SR0 STACKA LPSTACKA STACKP + + +SF Function Codes + Table 9-6 list the shift function (SF) codes used by these instruction types: + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36 + • “Type 15: Shift Data8” on page 9-37 + —shift functions (codes 0000–0111) only + • “Type 16: Shift Reg0” on page 9-38 + + + + + ADSP-219x Instruction Set Reference 9-15 + Instruction Opcodes + + + + + Table 9-6. SF codes + +Code Function + + 0000 LSHIFT (HI) + + 0001 LSHIFT (HI, OR) + + 0010 LSHIFT (LO) + + 0011 LSHIFT (LO, OR) + + 0100 ASHIFT (HI) + + 0101 ASHIFT (HI, OR) + + 0110 ASHIFT (LO) + + 0111 ASHIFT (LO, OR) + + 1000 NORM (HI) + + 1001 NORM (HI, OR) + + 1010 NORM (LO) + + 1011 NORM (LO, OR) + + 1100 EXP (HI) + + 1101 EXP (HIX) + + 1110 EXP (LO) + + 1111 Derive Block Exponent + + + + +9-16 ADSP-219x Instruction Set Reference + I and M Codes + Table 9-7 on page 9-17 lists the DAG index and modify register codes + used by the following instruction types. The G bit (DAG1/DAG2) determines + which group of I (index) and M (modify) registers. + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23. + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 19: Indirect Jump/Call” on page 9-41 + • “Type 21: Modify DagI” on page 9-43 + • “Type 21a: Modify DagI” on page 9-44 + • “Type 22: DM/PM «··· Data16” on page 9-45 + • “Type 29: Dreg «···» DM” on page 9-51 + • “Type 32: Any Reg «···» PM/DM” on page 9-54 + + Table 9-7. I and M codes + + DAG1 (G=0) DAG2 (G=1) + +Code I M I M + +00 I0 M0 I4 M4 + +01 I1 M1 I5 M5 + +10 I2 M2 I6 M6 + +11 I3 M3 I7 M7 + + + + + ADSP-219x Instruction Set Reference 9-17 + Instruction Opcodes + + + + +DMI, DMM, PMI, and PMM Codes + Table 9-8 lists the DAG index and modify register codes used by “Type 1: + Compute | DregX«···DM | DregY«···PM” on page 9-21. + + Table 9-8. DMI, DMM, PMI, PMM codes + +Code DMI DMM PMI PMM + + 00 I0 M0 I4 M4 + + 01 I1 M1 I5 M5 + + 10 I2 M2 I6 M6 + + 11 I3 M3 I7 M7 + + +IREG/MREG Codes + Table 9-9 lists the Ireg and Mreg codes used by “Type 3: Dreg/Ireg/Mreg + «···» DM/PM” on page 9-22 to specify a DAG index or modify register. + + Table 9-9. Ireg, Mreg codes + +Code Register Code Register + + 0000 I0 1000 M0 + + 0001 I1 1001 M1 + + 0010 I2 1010 M2 + + 0011 I3 1011 M3 + + 0100 I4 1100 M4 + + 0101 I5 1101 M5 + + + + +9-18 ADSP-219x Instruction Set Reference + Table 9-9. Ireg, Mreg codes (Cont’d) + +Code Register Code Register + +0110 I6 1110 M6 + +0111 I7 1111 M7 + + +XOP and YOP Codes + Table 9-10 on page 9-19 lists the XOP and YOP codes used by these + instructions: + • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21 + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26 + • “Type 9: Compute” on page 9-27 + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 23: Divide primitive, DIVQ” on page 9-47 + • “Type 24: Divide primitive, DIVS” on page 9-48 + + Table 9-10. XOP/YOP codes + + XOP YOP + +Code ALU MAC Shift Code ALU MAC + + 000 AX0 MX0 SI 00 AY0 MY0 + + 001 AX1 MX1 SR2 01 AY1 MY1 + + 010 AR AR AR 10 AF SR1 + + + + + ADSP-219x Instruction Set Reference 9-19 + Instruction Opcodes + + + + + Table 9-10. XOP/YOP codes + + XOP YOP + + Code ALU MAC Shift Code ALU MAC + + 011 MR0 MR0 MR0 11 0 0 + + 100 MR1 MR1 MR1 + + 101 MR2 MR2 MR2 + + 110 SR0 SR0 SR0 + + 111 SR1 SR1 SR1 + + + +Opcode Definitions + For each instruction opcode, this section provides the following + information: + • Opcode bits + • Syntax + • See also (related instruction reference pages) + For mnemonics definitions, see “Opcode Mnemonics” on page 9-1. + + + + +9-20 ADSP-219x Instruction Set Reference + Type 1: Compute | DregX«···DM | DregY«···PM + Multifunction ALU/MAC with DM and PM dual read with DAG1 and + DAG2 postmodify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 1 PD DD AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP PMI PMM DMI DMM + + + or for NOP only: + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 1 PD DD 0 0 0 0 0 + + + 10 9 8 7 6 5 4 3 2 1 0 + PMI PMM DMI DMM + + +SYNTAX + + |, |, Xop = DM(Ia += Mb), Yop = PM(Ic += Md); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Dual Memory Read” on page 6-3 + • “Dual Memory Read” on page 6-7 + + + + + ADSP-219x Instruction Set Reference 9-21 + Instruction Opcodes + + + + +Type 3: Dreg/Ireg/Mreg «···» DM/PM + Register read/write to immediate 16-bit address +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 0 1 D 16-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit address IREG/MREG + + + or: + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 0 0 D 16-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit address DREG + + +SYNTAX + + |DM(| = |Dreg, Ireg, Mreg|; + + |Dreg, Ireg, Mreg| = |DM()|; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Memory Read/Write—Immediate Address” on page 7-24 + + + + +9-22 ADSP-219x Instruction Set Reference + Type 4: Compute | Dreg «···» DM/PM + Multifunction ALU/MAC with memory read or write using DAG + postmodify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 1 1 G D Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP DREG I M + + +SYNTAX + + |, |, Dreg = |DM(Ia += Mb), PM(Ic += Md)|; + + |, |, |DM(Ia += Mb), PM(Ic += Md)| = Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Memory Read” on page 6-10 + • “Compute with Memory Write” on page 6-14 + + + + + ADSP-219x Instruction Set Reference 9-23 + Instruction Opcodes + + + + +Type 6: Dreg «··· Data16 + Immediate register group 0 (Dreg) register load +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 1 0 0 16-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit data DREG + + +SYNTAX + + = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Register Load” on page 7-27 + + + + +9-24 ADSP-219x Instruction Set Reference + Type 7: Reg1/2 «··· Data16 + Immediate register group 1 or 2 (Ireg, Mreg, Lreg, IMASK, IRPTL, ICNTL, + CNTR, STACKA, LPCSTACKA) register load + +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 1 0 1 16-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit data REG1 + + + or: + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 1 16-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit data REG2 + + +SYNTAX + + | , | = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Register Load” on page 7-27 + + + + + ADSP-219x Instruction Set Reference 9-25 + Instruction Opcodes + + + + +Type 8: Compute | Dreg1 «··· Dreg2 + ALU/MAC with data register move +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 1 Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP DDREG SDREG + + + or, generate ALU/MAC status only + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 1 Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 1 0 1 0 1 0 1 0 + + +SYNTAX + + | , |, Dreg = Dreg; + + NONE = ALU (Xop, Yop); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Register to Register Move” on page 6-18 + • “Generate ALU Status Only: NONE” on page 3-44 + + + + +9-26 ADSP-219x Instruction Set Reference + Type 9: Compute + Conditional ALU/MAC +OPCODE + + Conditional ALU/MAC + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 0 0 0 0 COND + + + Conditional ALU/MAC operations using constant YOP + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF YY + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP CC BO COND + + + Conditional ALU/MAC operations with YOP=0 + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF 1 1 + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 0 0 0 0 COND + + + + + ADSP-219x Instruction Set Reference 9-27 + Instruction Opcodes + + + + + Conditional MAC squaring operations only + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF 0 0 + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 0 0 0 1 COND + + +SYNTAX + + [IF Cond] |AR, AF| = Xop + |Yop, Yop + C, C, Const, Const + C|; + [IF Cond] |AR, AF| = Xop − |Yop,Yop+C−1,+C−1,Const, Const+C−1|; + [IF Cond] |AR, AF| = Yop − |Xop, Xop+C−1|; + [IF Cond] |AR, AF| = − |Xop+C−1, Xop+Const, Xop+Const+C−1|; + [IF Cond] |AR, AF| = Xop |AND, OR, XOR| |Yop, Const|; + [IF Cond] |AR, AF| = PASS |Xop, Yop, Const|; + [IF Cond] |AR, AF| = NOT |Xop, Yop|; + [IF Cond] |AR, AF| = ABS Xop; + [IF Cond] |AR, AF| = Yop +1; + [IF Cond] |AR, AF| = Yop −1; + [IF Cond] |MR, SR| = Xop * Yop [(|RND, SS, SU, US, UU|)]; + [IF Cond] |MR, SR| = Yop * Xop [(|RND, SS, SU, US, UU|)]; + [IF Cond]|MR, SR| = |MR, SR| + Xop * Yop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = |MR, SR| + Yop * Xop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = |MR, SR| − Xop * Yop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = |MR, SR| − Yop * Xop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = 0; + [IF Cond] MR = MR [(RND)]; + [IF Cond] SR = SR [(RND)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Add/Add with Carry” on page 3-5 + • “Subtract X-Y/Subtract X-Y with Borrow” on page 3-8 + • “Subtract Y-X/Subtract Y-X with Borrow” on page 3-12 + + + + +9-28 ADSP-219x Instruction Set Reference + • “Bitwise Logic: AND, OR, XOR” on page 3-15 +• “Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT” on + page 3-18 +• “Clear: PASS” on page 3-20 +• “Negate: NOT” on page 3-23 +• “Absolute Value: ABS” on page 3-26 +• “Increment” on page 3-29 +• “Decrement” on page 3-32 +• “Multiply” on page 4-8 +• “Multiply with Cumulative Add” on page 4-11 +• “Multiply with Cumulative Subtract” on page 4-14 +• “MAC Clear” on page 4-17 +• “MAC Round/Transfer” on page 4-19 + + + + + ADSP-219x Instruction Set Reference 9-29 + Instruction Opcodes + + + + +Type 9a: Compute + Unconditional ALU/MAC +OPCODE + + Register file ALU/MAC + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 1 0 0 Z AMF Y0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG 1 0 YREG + + + Register file ALU/MAC with XREG=0 + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 1 0 0 Z AMF Y0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 1 0 YREG + + +SYNTAX + + |AR, AF| = Dreg1 + |Dreg2, Dreg2 + C, C |; + |AR, AF| = Dreg1 − |Dreg2, Dreg2 + C −1, +C −1|; + |AR, AF| = Dreg2 − |Dreg1, Dreg1 + C −1|; + |AR, AF| = Dreg1 |AND, OR, XOR| Dreg2; + |AR, AF| = PASS |Dreg1, Dreg2, Const|; + |AR, AF| = PASS 0; + |AR, AF| = NOT |Dreg|; + |AR, AF| = ABS Dreg; + |AR, AF| = Dreg +1; + |AR, AF| = Dreg −1; + |MR, SR| = Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; + |MR, SR| = |MR, SR| + Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; + |MR, SR| = |MR, SR| − Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; + + + + +9-30 ADSP-219x Instruction Set Reference + SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Add/Add with Carry” on page 3-5 + • “Subtract X-Y/Subtract X-Y with Borrow” on page 3-8 + • “Subtract Y-X/Subtract Y-X with Borrow” on page 3-12 + • “Bitwise Logic: AND, OR, XOR” on page 3-15 + • “Clear: PASS” on page 3-20 + • “Negate: NOT” on page 3-23 + • “Absolute Value: ABS” on page 3-26 + • “Increment” on page 3-29 + • “Decrement” on page 3-32 + • “Multiply” on page 4-8 + • “Multiply with Cumulative Add” on page 4-11 + • “Multiply with Cumulative Subtract” on page 4-14 + + + + + ADSP-219x Instruction Set Reference 9-31 + Instruction Opcodes + + + + +Type 10: Direct Jump + 13-bit relative conditional/unconditional jump with delayed branch + option +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 1 0 B 13-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 13-bit address COND + + +SYNTAX + + [IF Cond] JUMP [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct JUMP (PC relative)” on page 8-27 + + + + +9-32 ADSP-219x Instruction Set Reference + Type 10a: Direct Jump/Call + 16-bit relative conditional/unconditional jump with delayed branch + option +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 1 1 14-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 14-bit address B S 2MSBs + + +SYNTAX + + CALL [(DB)]; + + JUMP [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “CALL (PC relative)” on page 8-30 + • “JUMP (PC relative)” on page 8-34 + + + + + ADSP-219x Instruction Set Reference 9-33 + Instruction Opcodes + + + + +Type 11: Do ··· Until + 12-bit relative conditional DO +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 1 1 0 12-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 12-bit address TERM + + +SYNTAX + + DO UNTIL [CE, FOREVER]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “DO UNTIL (PC relative)” on page 8-22 + + + + +9-34 ADSP-219x Instruction Set Reference + Type 12: Shift | Dreg «···» DM/PM + Shift with memory read/write using DAG postmodify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 0 1 G SF D + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP DREG I M + + +SYNTAX + + , Dreg = |DM(Ia += Mb), PM(Ic += Md)|; + + , |DM(Ia += Mb), PM(Ic += Md)| = Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Memory Read” on page 6-10 + • “Compute with Memory Write” on page 6-14 + • “XOP/YOP codes” on page 9-19 + + + + + ADSP-219x Instruction Set Reference 9-35 + Instruction Opcodes + + + + +Type 14: Shift | Dreg1 «··· Dreg2 + Register file shift with data register move +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 1 0 1 0 0 SF + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG DDREG SDREG + + +SYNTAX + + , Dreg = Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Register to Register Move” on page 6-18 + + + + +9-36 ADSP-219x Instruction Set Reference + Type 15: Shift Data8 + Immediate register file shift +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 1 1 SF + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG Exponent + + +SYNTAX + + SR = [SR OR] ASHIFT BY [(|HI, LO|)]; + + SR = [SR OR] LSHIFT BY [(|HI, LO|)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Arithmetic Shift Immediate” on page 5-8 + • “Logical Shift Immediate” on page 5-12 + + + + + ADSP-219x Instruction Set Reference 9-37 + Instruction Opcodes + + + + +Type 16: Shift Reg0 + Conditional register file shift +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 1 0 SF + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG COND + + +SYNTAX + + [IF Cond] SR = [SR OR] ASHIFT Dreg [(|HI, LO|)]; + + [IF Cond] SR = [SR OR] LSHIFT Dreg [(|HI, LO|)]; + + [IF Cond] SR = [SR OR] NORM Dreg [(|HI, LO|)]; + + [IF Cond] SE = [SR OR] EXP Dreg [(|HIX, HI, LO|)]; + + [IF Cond] SB = [SR OR] EXPADJ Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Arithmetic Shift” on page 5-6 + • “Logical Shift” on page 5-10 + • “Normalize” on page 5-14 + • “Exponent Derive” on page 5-20 + • “Exponent (Block) Adjust” on page 5-23 + + + + +9-38 ADSP-219x Instruction Set Reference + Type 17: Any Reg «··· Any Reg + General register move +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 0 1 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + DRGP SRGP DDREG SDREG + + +SYNTAX + + Reg = Reg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Register to Register Move” on page 7-22 + + + + + ADSP-219x Instruction Set Reference 9-39 + Instruction Opcodes + + + + +Type 18: Mode Change + Mode control +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 0 0 TI MM + + + 11 10 9 8 7 6 5 4 3 2 1 0 + AS OL BR SR SD INT + + +SYNTAX + + ENA | TI, MM, AS, OL, BR, SR, SD, INT | ; + + DIS | TI, MM, AS, OL, BR, SR, SD, INT |; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Mode Control” on page 8-69 + + + + +9-40 ADSP-219x Instruction Set Reference + Type 19: Indirect Jump/Call + Conditional indirect jump/call with delayed branch option +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 0 1 1 B S G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + COND I + + +SYNTAX + + [IF Cond] CALL [(DB)]; + + [IF Cond] JUMP [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect CALL” on page 8-42 + • “Indirect JUMP” on page 8-45 + + + + + ADSP-219x Instruction Set Reference 9-41 + Instruction Opcodes + + + + +Type 20: Return + Conditional return from interrupt/return from subroutine with delayed + branch option +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 0 1 0 B T Q + + + 11 10 9 8 7 6 5 4 3 2 1 0 + COND + + +SYNTAX + + [IF Cond] RTI [(DB)]; + + [IF Cond] RTS [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Return from Interrupt” on page 8-48 + • “Return from Subroutine” on page 8-52 + + + + +9-42 ADSP-219x Instruction Set Reference + Type 21: Modify DagI + DAG modify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 0 1 1 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + I M + + +SYNTAX + + |MODIFY (Ia += Mb), MODIFY (Ic += Md)|; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Modify Address Register—indirect” on page 7-63 + + + + + ADSP-219x Instruction Set Reference 9-43 + Instruction Opcodes + + + + +Type 21a: Modify DagI + DAG modify immediate value +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 0 1 0 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + MOD DATA I + + +SYNTAX + + MODIFY (Ireg += ); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Modify Address Register—direct” on page 7-65 + + + + +9-44 ADSP-219x Instruction Set Reference + Type 22: DM/PM «··· Data16 + 16-bit immediate data indirect memory write (two-word instruction) + using DAG postmodify addressing +OPCODE + + First word: 16-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 1 1 0 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 DATA LSBs I M + + + Second word: 16-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 8 DATA MSBs + + + 11 10 9 8 7 6 5 4 3 2 1 0 + + + + +SYNTAX + + |DM(Ia += Mb), DM (Ic += Md)| = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect 16-bit Memory Write—immediate data” on page 7-55 + + + + + ADSP-219x Instruction Set Reference 9-45 + Instruction Opcodes + + + + +Type 22a: DM/PM «··· Data24 + 24-bit immediate data indirect memory write (two-word instruction) + using DAG postmodify addressing +OPCODE + + First word: 24-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 1 1 1 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 DATA MidSBs I M + + + Second word: 24-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 8 DATA MSBs + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 DATA LSBs + + +SYNTAX + + |PM (Ia += Mb), PM (Ic += Md)| = :24; + + + ! The syntax at the end of the line is required for 24-bit data. If + :24 + omitted, 24-bit data is truncated by the assembler. +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect 24-bit Memory Write—immediate data” on page 7-57 + + + + +9-46 ADSP-219x Instruction Set Reference + Type 23: Divide primitive, DIVQ + DIVQ divide primitive +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 1 1 1 1 0 1 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 0 XOP + + +SYNTAX + + DIVQ Xop; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Divide Primitives: DIVS and DIVQ” on page 3-35 + + + + + ADSP-219x Instruction Set Reference 9-47 + Instruction Opcodes + + + + +Type 24: Divide primitive, DIVS + DIVS divide primitive +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 0 0 0 1 1 1 0 0 YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP + + +SYNTAX + + DIVS Yop, Xop; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Divide Primitives: DIVS and DIVQ” on page 3-35 + + + + +9-48 ADSP-219x Instruction Set Reference + Type 25: Saturate + Saturate MR/SR on overflow +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 1 1 0 R + + + 11 10 9 8 7 6 5 4 3 2 1 0 + + + + +SYNTAX + + SAT MR; + + SAT SR; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “MAC Saturate” on page 4-21 + + + + + ADSP-219x Instruction Set Reference 9-49 + Instruction Opcodes + + + + +Type 26:Push/Pop/Cache + Stack control +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 0 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + CF PPP LPP SPP + + +SYNTAX + + PUSH |PC, LOOP, STS|; + + POP |PC, LOOP, STS|; + + FLUSH CACHE; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “PUSH or POP Stacks” on page 8-55 + • “FLUSH CACHE” on page 8-61 + + + + +9-50 ADSP-219x Instruction Set Reference + Type 29: Dreg «···» DM + Memory read/write with immediate modify (postmodify with update or + premodify offset) +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 0 0 U DRU G D + + + 11 10 9 8 7 6 5 4 3 2 1 0 + MOD DATA I DRL + + +SYNTAX + + Dreg = DM(Ireg += ); /* postmodify read */ + + DM(Ireg += ) = Dreg; /* postmodify write */ + + Dreg = DM(Ireg + ); /* premodify read */ + + DM(Ireg + ) = Dreg; /* premodify write */ + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect Memory Read/Write—immediate postmodify” on + page 7-49 + • “Indirect Memory Read/Write—immediate premodify” on + page 7-52 + + + + + ADSP-219x Instruction Set Reference 9-51 + Instruction Opcodes + + + + +Type 30: NOP + No operation +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 0 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + SWCD + + +SYNTAX + + NOP; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “No Operation” on page 8-66 + + + + +9-52 ADSP-219x Instruction Set Reference + Type 31: Idle + Idle +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 1 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + IDLE VALUE + + +SYNTAX + + IDLE; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Idle” on page 8-67 + + + + + ADSP-219x Instruction Set Reference 9-53 + Instruction Opcodes + + + + +Type 32: Any Reg «···» PM/DM + DAG memory read/write with premodify offset or postmodify update +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 1 0 1 MS U G D 0 + + + 10 9 8 7 6 5 4 3 2 1 0 + RGP REG I M + + +SYNTAX + + |DM(Ia += Mb), DM(Ic += Md)| = Reg; /*postmodify write,16-bit*/ + + Reg = |DM(Ia += Mb), DM(Ic += Md)|; /*premodify read,16-bit*/ + + |DM(Ia + Mb), DM(Ic + Md)| = Reg; /*premodify write,16-bit*/ + + Reg = |DM (Ia + Mb), DM (Ic + Md)|; /*postmodify read,16-bit */ + + |PM(Ia += Mb), PM(Ic += Md)| = Reg; /*postmodify write,24-bit*/ + + Reg = |PM(Ia += Mb), PM(Ic += Md)|; /*premodify read,24-bit*/ + + |PM(Ia + Mb), PM(Ic + Md)| = Reg; /*premodify write,24-bit*/ + + Reg = |PM(Ia + Mb), PM(Ic + Md)|; /*postmodify read,24-bit*/ + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect 16-bit Memory Read/Write—postmodify” on page 7-30 + • “Indirect 16-bit Memory Read/Write—premodify” on page 7-34 + • “Indirect 24-bit Memory Read/Write—postmodify” on page 7-37 + • “Indirect 24-bit Memory Read/Write—premodify” on page 7-41 + + + +9-54 ADSP-219x Instruction Set Reference + Type 32a: DM«···DAG Reg | DAG Reg«···Ireg + DAG register store with register transfer +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 1 0 1 0 U G 1 1 + + + 10 9 8 7 6 5 4 3 2 1 0 + 0 RGP DAG REG I M + + +SYNTAX + + DM(Ireg1 += Mreg1) = |Ireg2, Mreg2, Lreg2|, + |Ireg2, Mreg2, Lreg2|= Ireg1 ; + + DM(Ireg1 += Mreg1) = |Ireg2, Mreg2, Lreg2|, + |Ireg2, Mreg2, Lreg2| = Ireg1 ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect DAG Register Write (premodify or postmodify), with + DAG Register Move” on page 7-45 + + + + + ADSP-219x Instruction Set Reference 9-55 + Instruction Opcodes + + + + +Type 33: Reg3 «··· Data12 + Load short constants +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 0 0 0 12-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 12-bit data REG3 + + +SYNTAX + + Reg3 = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Register Load” on page 7-27 + + + + +9-56 ADSP-219x Instruction Set Reference + Type 34: Dreg «···» IOreg + I/O register read/write +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 0 1 2MSBs addr D + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8-bit Address DREG + + +SYNTAX + + IO() = Dreg; + + Dreg = IO (); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “External IO Port Read/Write” on page 7-59 + + + + + ADSP-219x Instruction Set Reference 9-57 + Instruction Opcodes + + + + +Type 35: Dreg «···»Sreg + System control register read/write +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 0 0 D + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8-bit Address DREG + + +SYNTAX + + REG() = Dreg; + + Dreg = REG(); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “System Control Register Read/Write” on page 7-61 + + + + +9-58 ADSP-219x Instruction Set Reference + Type 36: Long Jump/Call + Conditional long jump/call (two-word instruction) +OPCODE BITS + + • First word + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 0 1 S + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 Address MSBs COND + + + • Second word + + 23 22 21 20 19 18 17 16 15 14 13 12 + 16 Address LSBs + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 16 Address LSBs + + +SYNTAX + + [IF Cond] LJUMP ; + + [IF Cond] LCALL ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Long CALL” on page 8-37 + • “Long JUMP” on page 8-40 + + + + + ADSP-219x Instruction Set Reference 9-59 + Instruction Opcodes + + + + +Type 37: Interrupt + Software interrupt +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 1 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + C BIT + + +SYNTAX + + SETINT ; + + CLRINT ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Set Interrupt” on page 8-62 + • “Clear Interrupt” on page 8-64 + + + + +9-60 ADSP-219x Instruction Set Reference + ADSP-219x Instruction Set Reference 9-61 + Instruction Opcodes + + + + +9-62 ADSP-219x Instruction Set Reference + \ No newline at end of file diff --git a/docs/9x_shftops.pdf b/docs/9x_shftops.pdf new file mode 100644 index 0000000..f1bf31d Binary files /dev/null and b/docs/9x_shftops.pdf differ diff --git a/docs/9x_shftops.txt b/docs/9x_shftops.txt new file mode 100644 index 0000000..1842420 --- /dev/null +++ b/docs/9x_shftops.txt @@ -0,0 +1,985 @@ +5 SHIFTER INSTRUCTIONS + Figure 5-0. + Table 5-0. + Listing 5-0. + + + + The instruction set provides shifter instructions for performing shift oper- + ations on 16-bit input to yield 40-bit output. Combining these functions, + programs can efficiently implement numeric format control, including + full floating-point representation. Shifter operations include: + • “Arithmetic Shift” on page 5-6 + • “Arithmetic Shift Immediate” on page 5-8 + • “Logical Shift” on page 5-10 + • “Logical Shift Immediate” on page 5-12 + • “Normalize” on page 5-14 + • “Normalize Immediate” on page 5-17 + • “Exponent Derive” on page 5-20 + • “Exponent (Block) Adjust” on page 5-23 + This chapter describes the individual shifter instructions and the following + related topics: + • “Shifter Registers” on page 5-2 + • “Shifter Instruction Options” on page 5-3 + • “Shifter Status Flags” on page 5-5 + • “Denormalization” on page 5-26 + + + + + ADSP-219x Instruction Set Reference 5-1 + Shifter Instructions + + + + + For details on condition codes, see “Condition Code (CCODE) Register” + on page 2-6. + +Shifter Registers + As shown in Table 5-1, the shifter has five registers. + + Table 5-1. Summary of shifter registers + +Name Size Description + + SR0 16 bits Shifter Result register (low word). SR denotes SR0, SR1, and SR2 combined, + which hold the 40-bit shifter result. + + SR1 16 bits Shifter Result register (middle word). This register also functions as the mul- + tiplier’s y-input feedback register. SR denotes SR0, SR1, and SR2 combined, + which hold the 40-bit shifter result. + + SR2 16/8 bits Shifter Result register (high byte). SR denotes SR0, SR1, and SR2 combined, + which hold the 40-bit shifter result. Although this register is 16 bits wide, for + shifter operations, only the lower eight bits are used. + + SB 16/5 bits Shifter Block exponent register. Although this register is 16 bits wide, for + shifter operations, only the lower five bits are used. + Contains the effective exponent derived from the number with greatest mag- + nitude in a block of numbers. This value provides the shift code for all num- + bers in the block in subsequent NORM or xSHIFT instructions. + The value in this register is sign-extended to form a 16-bit value when trans- + ferred to memory or to other data registers. + Nonshifter instructions can use SB for a 16-bit scratch register. + + + + +5-2 ADSP-219x Instruction Set Reference + Shifter Instruction Options + + + + + Table 5-1. Summary of shifter registers (Cont’d) + +Name Size Description + +SE 16/8 bits Shifter Exponent register. Although this register is 16 bits wide, for shifter + operations, only the lower eight bits are used. + Contains the effective exponent derived from the input data. This value pro- + vides the shift code for a subsequent NORM or xSHIFT instruction. + The value in this register is sign-extended to form a 16-bit value when trans- + ferred to memory or to other data registers. + Nonshifter instructions can use SE for a 16-bit scratch register. + +SI 16 bits Shifter Input register. Provides single-precision twos-complement input to + shifter instructions. + + + When a shifter operation writes data to SR1, it sign extends the value into + SR2, overwriting the previous contents of SR2. + + The SB and SE registers are the result registers for the block exponent + adjust (EXPADJ) operation and derive exponent (EXP) operation, respec- + tively. The shifter input register SI supplies single-precision input data to + any shifter operation, except EXPADJ. To input the result from an ALU or + MAC operation directly, you use the appropriate result register—SR, AR, + or MR. + +Shifter Instruction Options + Almost all shifter instructions have two to three options: (HI), (LO), and + (HIX). Each option enables a different exponent detector mode that oper- + ates only while the instruction executes. The shifter interprets and handles + the input data according to the selected mode. + For the derive exponent (EXP) and block exponent adjust ( EXPADJ) opera- + tions, the shifter calculates the shift code—the direction and number of + bits to shift—then stores that value in the SE register. For the ASHIFT, + LSHIFT, and NORM operations, the user can supply the value of the shift + + + + + ADSP-219x Instruction Set Reference 5-3 + Shifter Instructions + + + + + code directly to the SE or SB registers or use the result of a previous EXP or + EXPADJ operation. + + For the ASHIFT, LSHIFT, and NORM operations: + (HI) Operation references the upper half of the output field. + (LO) Operation references the lower half of the output field. + For the exponent derive (EXP) operation: + (HIX) Use this mode for shifts and normalization of results from ALU + operations. + Input data is the result of an add or subtract operation that may + have overflowed. The shifter examines the ALU overflow bit AV. If + AV=1, the effective exponent of the input is +1 (this value indicates + that overflowed occurred before the EXP operation executed). If + AV=0, no overflow occurred and the shifter performs the same oper- + ations as the (HI) mode. + (HI) Input data is a single-precision signed number or the upper half of + a double-precision signed number. The number of leading sign bits + in the input operand, which equals the number of sign bits minus + one, determines the shift code. + (By default, the EXPADJ operation always operates in this mode.) + (LO) Input data is the lower half of a double-precision signed number. + To derive the exponent on a double-precision number, you must + perform the EXP operation twice, once on the upper half of the + input, and once on the lower half. For details, “Exponent Derive” + on page 5-20. + + + + +5-4 ADSP-219x Instruction Set Reference + Shifter Status Flags + + + + +Shifter Status Flags + Two status flags in the ASTAT register, SS and SV, record the status of + shifter operations. + SS Records the sign of the shifter input operand + SS = 0 positive (+) input + SS = 1 negative (−) input + + SV Records overflow or underflow status + SV = 0 no overflow or underflow occurred + SV = 1 overflow or underflow occurred + + + + + ADSP-219x Instruction Set Reference 5-5 + Shifter Instructions + + + + +Arithmetic Shift + + [IF COND] SR = [SR OR] ASHIFT DREG ( HI ) ; + LO + + +FUNCTION + + Arithmetically shifts the bits of the operand by the amount (number of + bits) and direction specified by the shift code (value) in the SE register. A + positive value produces a left (up) shift, and a negative value produces a + right (down) shift. Optionally, the shift can be based on a half of the + 32-bit output field being shifted. For more information on output + options, see “Shifter Instruction Options” on page 5-3. + If execution is based on a condition, the shifter performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. + With the SR OR option selected, the shifter ORs the shifted output with + the current contents of the SR register and stores that value in SR. Other- + wise, it overwrites the current contents of the SR register with the shifted + output. +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SR Shifter result register contains 40-bit result. + + + +5-6 ADSP-219x Instruction Set Reference + Arithmetic Shift + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + SV AZ, AN, AV, AC, AS, AQ, SS, MV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + The shifter sign-extends the 40-bit result to the left, replicating the MSB + of the input, and it zero-fills the 40-bit result from the right. Bits shifted + out past either boundary (SR39 or SR0) are dropped. + To shift a double-precision number, you shift both halves of the input + data separately, using the same shift code value for both halves. You + ASHIFT the upper half of the input data but LSHIFT the lower half. The + first cycle, you ASHIFT the upper half of the input using the (HI) option. + The second cycle, you LSHIFT the lower half using both the (LO) and SR OR + options. Using these options prevents the shifter from sign-extending the + MSB of the low word and from overwriting the output (upper word) from + the previous ASHIFT operation. +EXAMPLES + + AR = 3; SE = AR; /* shift code, left shift 3 bits */ + SI = 0xB6A3; /* value of upper word of input data */ + SR = ASHIFT SI (HI); /* arithmetically shift high word */ + +SEE ALSO + + • “Type 16: Shift Reg0” on page 9-38 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + + ADSP-219x Instruction Set Reference 5-7 + Shifter Instructions + + + + +Arithmetic Shift Immediate + + SR = [SR OR] ASHIFT DREG BY ( HI ) ; + LO + + +FUNCTION + + Arithmetically shifts the bits of the operand by the amount (number of + bits) and direction specified by the immediate value. Valid immediate val- + ues range from −128 to 127. A positive value produces a left (up) shift, and + a negative value produces a right (down) shift. Optionally, the shift can be + based on a half of the 32-bit output field being shifted. For more informa- + tion on output options, see “Shifter Instruction Options” on page 5-3. + With the SR OR option selected, the shifter ORs the shifted output with + the current contents of the SR register and stores that value in SR. Other- + wise, it overwrites the current contents of the SR register with the shifted + output. +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SR Shifter result register contains 40-bit result. + + + + +5-8 ADSP-219x Instruction Set Reference + Arithmetic Shift Immediate + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + SV AZ, AN, AV, AC, AS, AQ, SS, MV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + The shifter sign-extends the 40-bit result to the left, replicating the MSB + of the input, and it zero-fills the 40-bit result from the right. Bits shifted + out past either boundary (SR39 or SR0) are dropped. + To shift a double-precision number, you shift both halves of the input + data separately, using the same immediate value for both halves. You ASH- + IFT the upper half of the input data but LSHIFT the lower half. The first + cycle, you ASHIFT the upper half of the input using the (HI) option. The + second cycle, you LSHIFT the lower half using both the (LO) and SR OR + options. Using these options prevents the shifter from sign-extending the + MSB of the low word and from overwriting the output (upper word) from + the previous ASHIFT operation. +EXAMPLES + + SI = 0xB6A3; /* value of upper word of input data */ + SR = ASHIFT SI BY 3 (HI);/* arithmetically shift upper word */ + +SEE ALSO + + • “Type 15: Shift Data8” on page 9-37 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + + ADSP-219x Instruction Set Reference 5-9 + Shifter Instructions + + + + +Logical Shift + + [IF COND] SR = [SR OR] LSHIFT DREG ( HI ) ; + LO + + +FUNCTION + + Logically shifts the bits of the operand by the amount (number of bits) + and direction specified by the shift code (value) in the SE register. A posi- + tive value produces a left (up) shift, and a negative value produces a right + (down) shift. Optionally, the shift can be based on a half of the 32-bit + output field being shifted. For more information on output options, see + “Shifter Instruction Options” on page 5-3. + If execution is based on a condition, the shifter performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. + With the SR OR option selected, the shifter ORs the shifted output with + the current contents of the SR register and stores that value in SR. Other- + wise, it overwrites the current contents of the SR register with the shifted + output. +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SR Shifter result register contains 40-bit result. + + + +5-10 ADSP-219x Instruction Set Reference + Logical Shift + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + SV AZ, AN, AV, AC, AS, AQ, SS, MV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + For left shifts (positive shift code), the shifter zero-fills the 40-bit result + from the right. Bits shifted out past the high-order boundary (SR39) are + dropped. + For right shifts (negative shift code), the shifter zero-fills the 40-bit result + from the left. Bits shifted out past the low-order boundary (SR0) are + dropped. + To shift a double-precision number, you shift both halves of the input + data separately, using the same shift code value for both halves. The first + cycle, you LSHIFT the upper half of the input using the (HI) option. The + second cycle, you LSHIFT the lower half using both the (LO) and SR OR + options. Using these options prevents the shifter from overwriting the + result (upper word) from the previous LSHIFT operation. +EXAMPLES + + AR = 3; SE = AR; /* shift code left shift 3 bits */ + AX0 = 0x765D; /* value of lower word of input data */ + SR = SR OR LSHIFT AX0(LO);/* logically shift low word */ + +SEE ALSO + + • “Type 16: Shift Reg0” on page 9-38 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + ADSP-219x Instruction Set Reference 5-11 + Shifter Instructions + + + + +Logical Shift Immediate + + SR = [SR OR] LSHIFT BY ( HI ) ; + LO + + +FUNCTION + + Logically shifts the bits of the operand by the amount (number of bits) + and direction specified by the immediate value. Valid immediate values + range from −128 to 127. A positive value produces a left (up) shift, and a + negative value produces a right (down) shift. Optionally, the shift can be + based on a half of the 32-bit output field being shifted. For more informa- + tion on output options, see “Shifter Instruction Options” on page 5-3. + With the SR OR option selected, the shifter ORs the shifted output with + the current contents of the SR register and stores that value in SR. Other- + wise, it overwrites the current contents of the SR register with the shifted + output. +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SR Shifter result register contains 40-bit result. + + + + +5-12 ADSP-219x Instruction Set Reference + Logical Shift Immediate + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + SV AZ, AN, AV, AC, AS, AQ, SS, MV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + For left shifts (positive shift code), the shifter zero-fills the 40-bit result + from the right. Bits shifted out past the high-order boundary (SR39) are + dropped. + For right shifts (negative shift code), the shifter zero-fills the 40-bit result + from the left. Bits shifted out past the low-order boundary (SR0) are + dropped. + To shift a double-precision number, you shift both halves of the input + data separately, using the same shift code value for both halves. The first + cycle, you LSHIFT the upper half of the input using the (HI) option. The + second cycle, you LSHIFT the lower half using both the (LO) and SR OR + options. Using these options prevents the shifter from overwriting the + result (upper word) from the previous LSHIFT operation. +EXAMPLES + + SI = 0xFF6A; /* single-precision input */ + SR = SR OR LSHIFT SI BY 3 (LO); /* logically shift low word */ + +SEE ALSO + + • “Type 15: Shift Data8” on page 9-37 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + + ADSP-219x Instruction Set Reference 5-13 + Shifter Instructions + + + + +Normalize + + [IF COND] SR = [SR OR] NORM DREG ( HI ) ; + LO + + +FUNCTION + + Normalization, in essence, is a fixed- to floating-point conversion opera- + tion that produces an exponent and a mantissa. Optionally, the operation + can be based on a half of the 32-bit output field being shifted. For more + information on output options, see “Shifter Instruction Options” on page + 5-3. + Normalization using this instruction is a two step process that requires: + • The EXP instruction to derive the exponent for the shift code. + • The NORM instruction to shift the twos-complement input by the cal- + culated shift code, removing its redundant sign bits and aligning its + true sign bit to the high-order bit of the output field. + The EXP operation calculates the number of redundant sign bits in the + input and stores the negative of that value in SE. The NORM operation + negates the value in SE again to generate a positive shift code, ensuring + that the input is shifted left. + If execution is based on a condition, the shifter performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. + With the SR OR option selected, the shifter ORs the shifted output with + the current contents of the SR register and stores that value in SR. Other- + wise, it overwrites the current contents of the SR register with the shifted + output. + + + + +5-14 ADSP-219x Instruction Set Reference + Normalize + + + + +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SR Shifter result register contains 40-bit result. +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + SV AZ, AN, AV, AC, AS, AQ, SS, MV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + The (HI) and (LO) options determine how unused bits in the 40-bit out- + put are filled. When the (HI) option is selected, the shifter zero-fills the + 40-bit result from the right. When the (LO) option is selected, the shifter + zero-fills the 40-bit result to the left. Bits shifted out past the high-order + boundary (SR39) are dropped. + To normalize a double-precision number, you normalize both halves of + the input data separately, using the same shift code value for both halves. + First, you use the EXP instruction to derive the exponent to use for the + shift code. Then, in the first normalization cycle, you NORM the upper half + of the input using the (HI) option. The next cycle, you NORM the lower half + using both the (LO) and SR OR options. Using these options prevents the + + + + + ADSP-219x Instruction Set Reference 5-15 + Shifter Instructions + + + + + shifter from overwriting the result (upper word) from the previous NORM + operation. +EXAMPLES + + /* Normalize double-precision twos complement data: */ + AX1 = 0xF6D4; /* load hi 2s comp data in dreg */ + AX0 = 0x04A2; /* load lo 2s comp data in dreg */ + SE = EXP AX1 (HI); /* derive exponent on hi word */ + SE = EXP AX0 (LO); /* derive exponent on lo word */ + SR = NORM AX1 (HI); /* normalize hi word */ + SR = SR OR NORM AX0 (LO); /* normalize lo word */ + +SEE ALSO + + • “Type 16: Shift Reg0” on page 9-38 + • “Denormalization” on page 5-26 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + +5-16 ADSP-219x Instruction Set Reference + Normalize Immediate + + + + +Normalize Immediate + + SR = [SR OR] NORM DREG BY ( HI ) ; + LO + + +FUNCTION + + Normalization, in essence, is a fixed- to floating-point conversion opera- + tion that produces an exponent and a mantissa. Using a positive constant + for the shift code, it is a one step process that shifts the twos-complement + input left by the specified amount, removing its redundant sign bits and + aligning its true sign bit to the high-order bit of the output field. Option- + ally, the operation can be based on a half of the 32-bit output field being + shifted. For more information on output options, see “Shifter Instruction + Options” on page 5-3. + With the SR OR option selected, the shifter ORs the shifted output with + the current contents of the SR register and stores that value in SR. Other- + wise, it overwrites the current contents of the SR register with the shifted + output. +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SR Shifter result register contains 40-bit result. + + + + + ADSP-219x Instruction Set Reference 5-17 + Shifter Instructions + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + SV AZ, AN, AV, AC, AS, AQ, SS, MV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + The (HI) and (LO) options determine how unused bits in the 40-bit out- + put are filled. When the (HI) option is selected, the shifter zero-fills the + 40-bit result from the right. When the (LO) option is selected, the shifter + zero-fills the 40-bit result to the left. Bits shifted out past the high-order + boundary (SR39) are dropped. + To normalize a double-precision number, you normalize both halves of + the input data separately, using the immediate value for both halves. In + the first normalization cycle, you NORM the upper half of the input using + the (HI) option. The next cycle, you NORM the lower half using both the + (LO) and SR OR options. Using these options prevents the shifter from + overwriting the result (upper word) from the previous NORM operation. +EXAMPLES + + /* Normalize a double-precision, twos-complement data: */ + AX1 = 0xF6D4; /* load hi 2s comp data in dreg */ + AX0 = 0x04A2; /* load lo 2s comp data in dreg */ + SR = NORM AX1 BY 2 (HI); /* normalize hi word */ + SR = SR OR NORM AX0 BY 2 (LO);/* normalize lo word */ + +SEE ALSO + + • “Type 15: Shift Data8” on page 9-37 + • “Denormalization” on page 5-26 + + + + +5-18 ADSP-219x Instruction Set Reference + Normalize Immediate + + + + +• “Condition Code (CCODE) Register” on page 2-6 +• “Mode Status (MSTAT) Register” on page 2-11 + + + + + ADSP-219x Instruction Set Reference 5-19 + Shifter Instructions + + + + +Exponent Derive + + [IF COND] SE = EXP DREG ( HIX ) ; + HI + LO + + +FUNCTION + + Derives the effective exponent of the input operand to generate the shift + code value for use in a subsequent normalization operation. The instruc- + tion option, (HIX), (HI), or (LO), determines the resulting shift code. For + more information on output options, see “Shifter Instruction Options” on + page 5-3. + If execution is based on a condition, the shifter performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SE Shifter exponent register contains the 8-bit shift code. + + + + +5-20 ADSP-219x Instruction Set Reference + Exponent Derive + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + +SS (Affected by operations using the (HI) and AZ, AN, AV, AC, AS, AQ, MV, SV +(HIX) options only. Set by the MSB of the input +data when AV = 0. In (HIX) mode only, set by the +inverted MSB of the input data when AV = 1.) + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + You use the (LO) option only to derive the exponent for the low word in a + double-precision twos-complement number. But before you do, you must + derive the exponent on the high word using either the (HI) or the (HIX) + option. The result of the EXP operation on the upper half determines the + shift code of the lower half. Unless the upper half contains all sign bits, + the SE register contains the correct shift code to use for both EXP (HI/HIX) + and (LO) operations. If the upper half does contain all sign bits, EXP (LO) + totals the number of sign bits in the double-precision word and stores that + value in SE. +EXAMPLES + + /* Normalize double-precision twos complement data: */ + AX1 = 0xF6D4; /* load hi 2s comp data in dreg */ + AX0 = 0x04A2; /* load lo 2s comp data in dreg */ + SE = EXP AX1 (HI); /* derive exponent on hi word */ + SE = EXP AX0 (LO); /* derive exponent on lo word */ + SR = NORM AX1 (HI); /* normalize hi word */ + SR = SR OR NORM AX0 (LO); /* normalize lo word */ + + + + + ADSP-219x Instruction Set Reference 5-21 + Shifter Instructions + + + + +SEE ALSO + + • “Type 16: Shift Reg0” on page 9-38 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + +5-22 ADSP-219x Instruction Set Reference + Exponent (Block) Adjust + + + + +Exponent (Block) Adjust + + [IF COND] SB = EXPADJ DREG ; + + +FUNCTION + + Derives the effective exponent of the number of largest magnitude in a + block of numbers. Using this value for the shift code in subsequent NORM + instructions, you can normalize each number in the block. + If execution is based on a condition, the shifter performs the operation + only if the condition evaluates true, and it performs a NOP operation if the + condition evaluates false. Omitting the condition forces unconditional + execution of the instruction. +INPUT + + The input operand, the value to shift, is supplied in a data register. You + can use any of these data registers for the DREG inputs: + +Register File + + AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI + + +OUTPUT + + SB Shifter block exponent register contains the 5-bit exponent value. + You must initialize SB to −16 before issuing the first EXPADJ instruc- + tion in the series. + + + + + ADSP-219x Instruction Set Reference 5-23 + Shifter Instructions + + + + +STATUS FLAGS + + +Affected Flags–set or cleared by the operation Unaffected Flags + + AZ, AN, AV, AC, AS, AQ, SS, MV, SV + +For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5. + + +DETAILS + + This instruction operates in (HI) mode to derive the exponent. It works + on double-precision twos-complement input only. Possible values for the + result of the EXPADJ operation range from −15 to 0. + To derive the effective exponent for a block of numbers, you + 1. Initialize the SB register to −16. + SB = −16; + + This value falls below the range of possible exponent values. + 2. For each number in the block, derive the effective exponent. + SB = EXPADJ DREGx; + + For the first operation, the shifter derives the exponent and stores it + in SB. + For each subsequent operation, the shifter derives the exponent + and compares the new value with the current value of SB. If the + new value is greater than the current value, the shifter stores the + new value in SB, overwriting the old value. Otherwise, the shifter + discards the new value and the contents of SB remain unchanged. + At the end of the last EXPADJ operation, SB contains the exponent + of the number of largest magnitude in the block. + + + + +5-24 ADSP-219x Instruction Set Reference + Exponent (Block) Adjust + + + + + 3. Transfer the contents of SB to SE. + SE = SB; + + SE now contains the shift code to use in subsequent NORM opera- + tions to normalize each of the numbers in the block. For details, + see “Normalize” on page 5-14. + Alternatively, you can save the exponent in a data register for use + later in your program. +EXAMPLES + + /* Normalize double-precision twos complement data: */ + AX1 = 0xF6D4; /* load hi 2s comp data in dreg */ + AX0 = 0x04A2; /* load lo 2s comp data in dreg */ + SB = -16; /* initialize SB */ + SB = EXPADJ AX1; + SB = EXPADJ AX0; + SE = SB; /* load block adjusted exp */ + SR = NORM AX1 (HI); /* normalize hi word */ + SR = SR OR NORM AX0 (LO); /* normalize lo word */ + +SEE ALSO + + • “Type 16: Shift Reg0” on page 9-38 + • “Condition Code (CCODE) Register” on page 2-6 + • “Mode Status (MSTAT) Register” on page 2-11 + + + + + ADSP-219x Instruction Set Reference 5-25 + Shifter Instructions + + + + +Denormalization +FUNCTION + + Denormalization is a shift function in which a predefined exponent + defines the amount and direction of the shift. In essence, denormalization + is a floating- to fixed-point conversion operation. It requires a series of + shifter operations: + • The EXP instruction to derive the exponent used for the shift code, + or SE explicitly loaded with the exponent value. SE must contain the + shift value; for denormalization, you cannot use ASHIFT/LSHIFT + with an immediate value. + • The ASHIFT instruction to shift a single-precision number or the + high word of a double-precision number. + • When denormalizing a double-precision number, the LSHIFT + instruction to shift the low word. + Denormalize a double-precision, twos-complement number: + MX1 = −3; /* generate shift code */ + SE = MX1; /* load value in SE register */ + AX1 = 0xB6A3; /* load high word of input */ + AX0 = 0x765D; /* load low word of input */ + SR = ASHIFT AX1(HI); /* arith shift high word */ + SR = SR OR LSHIFT AX0(LO); /* logically shift low word */ + + You can reverse shift order, but you must always arithmetically shift the + high word of a double-precision number: + MX1 = −3; /* generate shift code */ + SE = MX1; /* load value in SE register */ + AX1 = 0xB6A3; /* load high word of input */ + AX0 = 0x765D; /* load low word of input */ + SR = LSHIFT AX0(LO); /* logically shift low word */ + SR = SR OR ASHIFT AX1(HI); /* arith shift high word */ + + + + +5-26 ADSP-219x Instruction Set Reference + \ No newline at end of file diff --git a/docs/ARCHITECTURE.md b/docs/ARCHITECTURE.md new file mode 100644 index 0000000..8b997cc --- /dev/null +++ b/docs/ARCHITECTURE.md @@ -0,0 +1,34 @@ +# ADSP-219x Architecture Reference ⚙️ + +## Core Features +The ADSP-219x family consists of a 16-bit fixed-point DSP core with a 24-bit instruction word. + +- **Harvard Architecture**: Separate Program Memory (PM) and Data Memory (DM) buses. +- **Instruction Width**: Exactly 24 bits. Padded often with a leading 0x00 or trailing zero byte if stored in 32-bit words, or packed as 3 bytes. +- **Memory Model**: + - PM Adressraum (24-bit Wörter): 16-bit to 24-bit depending on the model. + - DM Adressraum (16-bit Wörter): Up to 64K words. + +## Register Set 🗳️ + +| Group | Registry | Purpose | +|-------|----------|---------| +| **REG0** | AX0, AX1, MX0, MX1, AY0, AY1, MY0, MY1, MR2, SR2, AR, SI, MR1, SR1, MR0, SR0 | ALU, Multiplier, MAC, and Shifter registers. | +| **REG1** | I0-I3, M0-M3, L0-L3, IMASK, IRPTL, ICNTL, STACKA | DAG1 (Data Address Generator) indices, modifies, lengths, and interrupt control. | +| **REG2** | I4-I7, M4-M7, L4-L7, Reserved, CNTR, LPSTACKA | DAG2 indices, modifies, lengths, and hardware loop structures. | +| **REG3** | ASTAT, MSTAT, SSTAT, LPSTACKP, CCODE, SE, SB, PX, DMPG1, DMPG2, IOPG, IJPG, Reserved, STACKP | Status registers, page registers, and control stacks. | + +## Arithmetic Elements +- **ALU**: 16-bit with overflow and saturation logic. +- **Multiplier/MAC**: 16x16 → 40-bit accumulation (MR). +- **Barrel Shifter**: 32-bit with 16-bit input and bit-manipulation capabilities. + +## Instruction Types 🕹️ +There are ~37 distinct instruction types, distinguished by their MSB encoding. + +- **Type 1**: Compute + Dual Memory Read (Multifunction). +- **Type 3**: Direct Register Read/Write. +- **Type 4**: Compute + Single Memory Read/Write. +- **Type 6/7**: Load Immediate 16-bit to Register. +- **Type 10/10a/19/36**: Jumps and Calls (Relative/Indirect/Long). +- **Type 15/16**: Shifter operations. diff --git a/docs/GETTING_STARTED.md b/docs/GETTING_STARTED.md new file mode 100644 index 0000000..d832dbc --- /dev/null +++ b/docs/GETTING_STARTED.md @@ -0,0 +1,26 @@ +# ADSP-219x Analysis Workflow (Air-Gapped 🛡️) + +## Phase 1: Preparation (Online) +1. **Download and Copy**: Ensure the entire `adsp219x-re/` folder is on the air-gapped machine. +2. **Setup Dependencies**: Ensure Python 3.8+ is installed. Radare2 must be on $PATH. +3. **Verify Python**: `python3 -m pip install r2pipe` (if not already part of your r2 install). + +## Phase 2: Loading ROMs +Use raw loading for ADSP-2191 ROMs: +`r2 -a adsp2 -b 24 -m 0x0 my_rom.bin` +(Note: `-a` and `-b` are placeholders until a native plugin exists. We use raw mode.) + +## Phase 3: Automated Disassembly +Run the standalone disassembler first to get a quick overview: +`python3 disassembler/adsp219x_disasm.py my_rom.bin 3 > disassembly.txt` + +## Phase 4: Radare2 + Iaito Integration +To use our custom Python disassembly inside radare2: +1. Open the ROM in radare2. +2. Run the analysis script via r2pipe: + `#!python analysis/analyze_rom.py` (Inside r2: `#!pipe python3 ...`) +3. Use `iaito` to browse the memory with the comments generated by the script. + +## Phase 5: Debugging/Validation +Compare your proprietary ROM against our test ROMs in `testrom/test_roms/`. +If you find a new instruction type, add it to `disassembler/adsp219x_disasm.py` and submit! diff --git a/docs/opcode_definitions.txt b/docs/opcode_definitions.txt new file mode 100644 index 0000000..89a5617 --- /dev/null +++ b/docs/opcode_definitions.txt @@ -0,0 +1,1366 @@ +Opcode Definitions + For each instruction opcode, this section provides the following + information: + • Opcode bits + • Syntax + • See also (related instruction reference pages) + For mnemonics definitions, see “Opcode Mnemonics” on page 9-1. + + + + +9-20 ADSP-219x Instruction Set Reference + Type 1: Compute | DregX«···DM | DregY«···PM + Multifunction ALU/MAC with DM and PM dual read with DAG1 and + DAG2 postmodify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 1 PD DD AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP PMI PMM DMI DMM + + + or for NOP only: + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 1 PD DD 0 0 0 0 0 + + + 10 9 8 7 6 5 4 3 2 1 0 + PMI PMM DMI DMM + + +SYNTAX + + |, |, Xop = DM(Ia += Mb), Yop = PM(Ic += Md); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Dual Memory Read” on page 6-3 + • “Dual Memory Read” on page 6-7 + + + + + ADSP-219x Instruction Set Reference 9-21 + Instruction Opcodes + + + + +Type 3: Dreg/Ireg/Mreg «···» DM/PM + Register read/write to immediate 16-bit address +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 0 1 D 16-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit address IREG/MREG + + + or: + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 1 0 0 D 16-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit address DREG + + +SYNTAX + + |DM(| = |Dreg, Ireg, Mreg|; + + |Dreg, Ireg, Mreg| = |DM()|; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Memory Read/Write—Immediate Address” on page 7-24 + + + + +9-22 ADSP-219x Instruction Set Reference + Type 4: Compute | Dreg «···» DM/PM + Multifunction ALU/MAC with memory read or write using DAG + postmodify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 1 1 G D Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP DREG I M + + +SYNTAX + + |, |, Dreg = |DM(Ia += Mb), PM(Ic += Md)|; + + |, |, |DM(Ia += Mb), PM(Ic += Md)| = Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Memory Read” on page 6-10 + • “Compute with Memory Write” on page 6-14 + + + + + ADSP-219x Instruction Set Reference 9-23 + Instruction Opcodes + + + + +Type 6: Dreg «··· Data16 + Immediate register group 0 (Dreg) register load +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 1 0 0 16-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit data DREG + + +SYNTAX + + = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Register Load” on page 7-27 + + + + +9-24 ADSP-219x Instruction Set Reference + Type 7: Reg1/2 «··· Data16 + Immediate register group 1 or 2 (Ireg, Mreg, Lreg, IMASK, IRPTL, ICNTL, + CNTR, STACKA, LPCSTACKA) register load + +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 1 0 1 16-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit data REG1 + + + or: + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 1 16-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 16-bit data REG2 + + +SYNTAX + + | , | = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Register Load” on page 7-27 + + + + + ADSP-219x Instruction Set Reference 9-25 + Instruction Opcodes + + + + +Type 8: Compute | Dreg1 «··· Dreg2 + ALU/MAC with data register move +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 1 Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP DDREG SDREG + + + or, generate ALU/MAC status only + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 1 Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 1 0 1 0 1 0 1 0 + + +SYNTAX + + | , |, Dreg = Dreg; + + NONE = ALU (Xop, Yop); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Register to Register Move” on page 6-18 + • “Generate ALU Status Only: NONE” on page 3-44 + + + + +9-26 ADSP-219x Instruction Set Reference + Type 9: Compute + Conditional ALU/MAC +OPCODE + + Conditional ALU/MAC + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 0 0 0 0 COND + + + Conditional ALU/MAC operations using constant YOP + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF YY + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP CC BO COND + + + Conditional ALU/MAC operations with YOP=0 + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF 1 1 + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 0 0 0 0 COND + + + + + ADSP-219x Instruction Set Reference 9-27 + Instruction Opcodes + + + + + Conditional MAC squaring operations only + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 1 0 0 Z AMF 0 0 + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP 0 0 0 1 COND + + +SYNTAX + + [IF Cond] |AR, AF| = Xop + |Yop, Yop + C, C, Const, Const + C|; + [IF Cond] |AR, AF| = Xop − |Yop,Yop+C−1,+C−1,Const, Const+C−1|; + [IF Cond] |AR, AF| = Yop − |Xop, Xop+C−1|; + [IF Cond] |AR, AF| = − |Xop+C−1, Xop+Const, Xop+Const+C−1|; + [IF Cond] |AR, AF| = Xop |AND, OR, XOR| |Yop, Const|; + [IF Cond] |AR, AF| = PASS |Xop, Yop, Const|; + [IF Cond] |AR, AF| = NOT |Xop, Yop|; + [IF Cond] |AR, AF| = ABS Xop; + [IF Cond] |AR, AF| = Yop +1; + [IF Cond] |AR, AF| = Yop −1; + [IF Cond] |MR, SR| = Xop * Yop [(|RND, SS, SU, US, UU|)]; + [IF Cond] |MR, SR| = Yop * Xop [(|RND, SS, SU, US, UU|)]; + [IF Cond]|MR, SR| = |MR, SR| + Xop * Yop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = |MR, SR| + Yop * Xop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = |MR, SR| − Xop * Yop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = |MR, SR| − Yop * Xop [(|RND,SS,SU,US,UU|)]; + [IF Cond] |MR, SR| = 0; + [IF Cond] MR = MR [(RND)]; + [IF Cond] SR = SR [(RND)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Add/Add with Carry” on page 3-5 + • “Subtract X-Y/Subtract X-Y with Borrow” on page 3-8 + • “Subtract Y-X/Subtract Y-X with Borrow” on page 3-12 + + + + +9-28 ADSP-219x Instruction Set Reference + • “Bitwise Logic: AND, OR, XOR” on page 3-15 +• “Bit Manipulation: TSTBIT, SETBIT, CLRBIT, TGLBIT” on + page 3-18 +• “Clear: PASS” on page 3-20 +• “Negate: NOT” on page 3-23 +• “Absolute Value: ABS” on page 3-26 +• “Increment” on page 3-29 +• “Decrement” on page 3-32 +• “Multiply” on page 4-8 +• “Multiply with Cumulative Add” on page 4-11 +• “Multiply with Cumulative Subtract” on page 4-14 +• “MAC Clear” on page 4-17 +• “MAC Round/Transfer” on page 4-19 + + + + + ADSP-219x Instruction Set Reference 9-29 + Instruction Opcodes + + + + +Type 9a: Compute + Unconditional ALU/MAC +OPCODE + + Register file ALU/MAC + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 1 0 0 Z AMF Y0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG 1 0 YREG + + + Register file ALU/MAC with XREG=0 + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 1 0 0 Z AMF Y0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 1 0 YREG + + +SYNTAX + + |AR, AF| = Dreg1 + |Dreg2, Dreg2 + C, C |; + |AR, AF| = Dreg1 − |Dreg2, Dreg2 + C −1, +C −1|; + |AR, AF| = Dreg2 − |Dreg1, Dreg1 + C −1|; + |AR, AF| = Dreg1 |AND, OR, XOR| Dreg2; + |AR, AF| = PASS |Dreg1, Dreg2, Const|; + |AR, AF| = PASS 0; + |AR, AF| = NOT |Dreg|; + |AR, AF| = ABS Dreg; + |AR, AF| = Dreg +1; + |AR, AF| = Dreg −1; + |MR, SR| = Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; + |MR, SR| = |MR, SR| + Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; + |MR, SR| = |MR, SR| − Dreg1 * Dreg2 [(|RND, SS, SU, US, UU|)]; + + + + +9-30 ADSP-219x Instruction Set Reference + SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Add/Add with Carry” on page 3-5 + • “Subtract X-Y/Subtract X-Y with Borrow” on page 3-8 + • “Subtract Y-X/Subtract Y-X with Borrow” on page 3-12 + • “Bitwise Logic: AND, OR, XOR” on page 3-15 + • “Clear: PASS” on page 3-20 + • “Negate: NOT” on page 3-23 + • “Absolute Value: ABS” on page 3-26 + • “Increment” on page 3-29 + • “Decrement” on page 3-32 + • “Multiply” on page 4-8 + • “Multiply with Cumulative Add” on page 4-11 + • “Multiply with Cumulative Subtract” on page 4-14 + + + + + ADSP-219x Instruction Set Reference 9-31 + Instruction Opcodes + + + + +Type 10: Direct Jump + 13-bit relative conditional/unconditional jump with delayed branch + option +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 1 0 B 13-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 13-bit address COND + + +SYNTAX + + [IF Cond] JUMP [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct JUMP (PC relative)” on page 8-27 + + + + +9-32 ADSP-219x Instruction Set Reference + Type 10a: Direct Jump/Call + 16-bit relative conditional/unconditional jump with delayed branch + option +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 1 1 14-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 14-bit address B S 2MSBs + + +SYNTAX + + CALL [(DB)]; + + JUMP [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “CALL (PC relative)” on page 8-30 + • “JUMP (PC relative)” on page 8-34 + + + + + ADSP-219x Instruction Set Reference 9-33 + Instruction Opcodes + + + + +Type 11: Do ··· Until + 12-bit relative conditional DO +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 1 1 0 12-bit address + + + 10 9 8 7 6 5 4 3 2 1 0 + 12-bit address TERM + + +SYNTAX + + DO UNTIL [CE, FOREVER]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “DO UNTIL (PC relative)” on page 8-22 + + + + +9-34 ADSP-219x Instruction Set Reference + Type 12: Shift | Dreg «···» DM/PM + Shift with memory read/write using DAG postmodify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 0 1 G SF D + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP DREG I M + + +SYNTAX + + , Dreg = |DM(Ia += Mb), PM(Ic += Md)|; + + , |DM(Ia += Mb), PM(Ic += Md)| = Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Memory Read” on page 6-10 + • “Compute with Memory Write” on page 6-14 + • “XOP/YOP codes” on page 9-19 + + + + + ADSP-219x Instruction Set Reference 9-35 + Instruction Opcodes + + + + +Type 14: Shift | Dreg1 «··· Dreg2 + Register file shift with data register move +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 1 0 1 0 0 SF + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG DDREG SDREG + + +SYNTAX + + , Dreg = Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Compute with Register to Register Move” on page 6-18 + + + + +9-36 ADSP-219x Instruction Set Reference + Type 15: Shift Data8 + Immediate register file shift +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 1 1 SF + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG Exponent + + +SYNTAX + + SR = [SR OR] ASHIFT BY [(|HI, LO|)]; + + SR = [SR OR] LSHIFT BY [(|HI, LO|)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Arithmetic Shift Immediate” on page 5-8 + • “Logical Shift Immediate” on page 5-12 + + + + + ADSP-219x Instruction Set Reference 9-37 + Instruction Opcodes + + + + +Type 16: Shift Reg0 + Conditional register file shift +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 1 0 SF + + + 11 10 9 8 7 6 5 4 3 2 1 0 + XREG COND + + +SYNTAX + + [IF Cond] SR = [SR OR] ASHIFT Dreg [(|HI, LO|)]; + + [IF Cond] SR = [SR OR] LSHIFT Dreg [(|HI, LO|)]; + + [IF Cond] SR = [SR OR] NORM Dreg [(|HI, LO|)]; + + [IF Cond] SE = [SR OR] EXP Dreg [(|HIX, HI, LO|)]; + + [IF Cond] SB = [SR OR] EXPADJ Dreg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Arithmetic Shift” on page 5-6 + • “Logical Shift” on page 5-10 + • “Normalize” on page 5-14 + • “Exponent Derive” on page 5-20 + • “Exponent (Block) Adjust” on page 5-23 + + + + +9-38 ADSP-219x Instruction Set Reference + Type 17: Any Reg «··· Any Reg + General register move +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 0 1 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + DRGP SRGP DDREG SDREG + + +SYNTAX + + Reg = Reg; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Register to Register Move” on page 7-22 + + + + + ADSP-219x Instruction Set Reference 9-39 + Instruction Opcodes + + + + +Type 18: Mode Change + Mode control +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 1 0 0 TI MM + + + 11 10 9 8 7 6 5 4 3 2 1 0 + AS OL BR SR SD INT + + +SYNTAX + + ENA | TI, MM, AS, OL, BR, SR, SD, INT | ; + + DIS | TI, MM, AS, OL, BR, SR, SD, INT |; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Mode Control” on page 8-69 + + + + +9-40 ADSP-219x Instruction Set Reference + Type 19: Indirect Jump/Call + Conditional indirect jump/call with delayed branch option +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 0 1 1 B S G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + COND I + + +SYNTAX + + [IF Cond] CALL [(DB)]; + + [IF Cond] JUMP [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect CALL” on page 8-42 + • “Indirect JUMP” on page 8-45 + + + + + ADSP-219x Instruction Set Reference 9-41 + Instruction Opcodes + + + + +Type 20: Return + Conditional return from interrupt/return from subroutine with delayed + branch option +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 0 1 0 B T Q + + + 11 10 9 8 7 6 5 4 3 2 1 0 + COND + + +SYNTAX + + [IF Cond] RTI [(DB)]; + + [IF Cond] RTS [(DB)]; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Return from Interrupt” on page 8-48 + • “Return from Subroutine” on page 8-52 + + + + +9-42 ADSP-219x Instruction Set Reference + Type 21: Modify DagI + DAG modify +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 0 1 1 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + I M + + +SYNTAX + + |MODIFY (Ia += Mb), MODIFY (Ic += Md)|; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Modify Address Register—indirect” on page 7-63 + + + + + ADSP-219x Instruction Set Reference 9-43 + Instruction Opcodes + + + + +Type 21a: Modify DagI + DAG modify immediate value +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 0 1 0 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + MOD DATA I + + +SYNTAX + + MODIFY (Ireg += ); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Modify Address Register—direct” on page 7-65 + + + + +9-44 ADSP-219x Instruction Set Reference + Type 22: DM/PM «··· Data16 + 16-bit immediate data indirect memory write (two-word instruction) + using DAG postmodify addressing +OPCODE + + First word: 16-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 1 1 0 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 DATA LSBs I M + + + Second word: 16-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 8 DATA MSBs + + + 11 10 9 8 7 6 5 4 3 2 1 0 + + + + +SYNTAX + + |DM(Ia += Mb), DM (Ic += Md)| = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect 16-bit Memory Write—immediate data” on page 7-55 + + + + + ADSP-219x Instruction Set Reference 9-45 + Instruction Opcodes + + + + +Type 22a: DM/PM «··· Data24 + 24-bit immediate data indirect memory write (two-word instruction) + using DAG postmodify addressing +OPCODE + + First word: 24-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 1 1 1 G + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 DATA MidSBs I M + + + Second word: 24-bit data write + + 23 22 21 20 19 18 17 16 15 14 13 12 + 8 DATA MSBs + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 DATA LSBs + + +SYNTAX + + |PM (Ia += Mb), PM (Ic += Md)| = :24; + + + ! The syntax at the end of the line is required for 24-bit data. If + :24 + omitted, 24-bit data is truncated by the assembler. +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect 24-bit Memory Write—immediate data” on page 7-57 + + + + +9-46 ADSP-219x Instruction Set Reference + Type 23: Divide primitive, DIVQ + DIVQ divide primitive +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 1 1 1 1 0 1 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 0 XOP + + +SYNTAX + + DIVQ Xop; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Divide Primitives: DIVS and DIVQ” on page 3-35 + + + + + ADSP-219x Instruction Set Reference 9-47 + Instruction Opcodes + + + + +Type 24: Divide primitive, DIVS + DIVS divide primitive +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 0 0 0 1 1 1 0 0 YOP + + + 10 9 8 7 6 5 4 3 2 1 0 + XOP + + +SYNTAX + + DIVS Yop, Xop; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Divide Primitives: DIVS and DIVQ” on page 3-35 + + + + +9-48 ADSP-219x Instruction Set Reference + Type 25: Saturate + Saturate MR/SR on overflow +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 1 1 0 R + + + 11 10 9 8 7 6 5 4 3 2 1 0 + + + + +SYNTAX + + SAT MR; + + SAT SR; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “MAC Saturate” on page 4-21 + + + + + ADSP-219x Instruction Set Reference 9-49 + Instruction Opcodes + + + + +Type 26:Push/Pop/Cache + Stack control +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 0 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + CF PPP LPP SPP + + +SYNTAX + + PUSH |PC, LOOP, STS|; + + POP |PC, LOOP, STS|; + + FLUSH CACHE; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “PUSH or POP Stacks” on page 8-55 + • “FLUSH CACHE” on page 8-61 + + + + +9-50 ADSP-219x Instruction Set Reference + Type 29: Dreg «···» DM + Memory read/write with immediate modify (postmodify with update or + premodify offset) +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 1 0 0 U DRU G D + + + 11 10 9 8 7 6 5 4 3 2 1 0 + MOD DATA I DRL + + +SYNTAX + + Dreg = DM(Ireg += ); /* postmodify read */ + + DM(Ireg += ) = Dreg; /* postmodify write */ + + Dreg = DM(Ireg + ); /* premodify read */ + + DM(Ireg + ) = Dreg; /* premodify write */ + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect Memory Read/Write—immediate postmodify” on + page 7-49 + • “Indirect Memory Read/Write—immediate premodify” on + page 7-52 + + + + + ADSP-219x Instruction Set Reference 9-51 + Instruction Opcodes + + + + +Type 30: NOP + No operation +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 0 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + SWCD + + +SYNTAX + + NOP; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “No Operation” on page 8-66 + + + + +9-52 ADSP-219x Instruction Set Reference + Type 31: Idle + Idle +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 0 1 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + IDLE VALUE + + +SYNTAX + + IDLE; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Idle” on page 8-67 + + + + + ADSP-219x Instruction Set Reference 9-53 + Instruction Opcodes + + + + +Type 32: Any Reg «···» PM/DM + DAG memory read/write with premodify offset or postmodify update +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 1 0 1 MS U G D 0 + + + 10 9 8 7 6 5 4 3 2 1 0 + RGP REG I M + + +SYNTAX + + |DM(Ia += Mb), DM(Ic += Md)| = Reg; /*postmodify write,16-bit*/ + + Reg = |DM(Ia += Mb), DM(Ic += Md)|; /*premodify read,16-bit*/ + + |DM(Ia + Mb), DM(Ic + Md)| = Reg; /*premodify write,16-bit*/ + + Reg = |DM (Ia + Mb), DM (Ic + Md)|; /*postmodify read,16-bit */ + + |PM(Ia += Mb), PM(Ic += Md)| = Reg; /*postmodify write,24-bit*/ + + Reg = |PM(Ia += Mb), PM(Ic += Md)|; /*premodify read,24-bit*/ + + |PM(Ia + Mb), PM(Ic + Md)| = Reg; /*premodify write,24-bit*/ + + Reg = |PM(Ia + Mb), PM(Ic + Md)|; /*postmodify read,24-bit*/ + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect 16-bit Memory Read/Write—postmodify” on page 7-30 + • “Indirect 16-bit Memory Read/Write—premodify” on page 7-34 + • “Indirect 24-bit Memory Read/Write—postmodify” on page 7-37 + • “Indirect 24-bit Memory Read/Write—premodify” on page 7-41 + + + +9-54 ADSP-219x Instruction Set Reference + Type 32a: DM«···DAG Reg | DAG Reg«···Ireg + DAG register store with register transfer +OPCODE + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 1 0 1 0 U G 1 1 + + + 10 9 8 7 6 5 4 3 2 1 0 + 0 RGP DAG REG I M + + +SYNTAX + + DM(Ireg1 += Mreg1) = |Ireg2, Mreg2, Lreg2|, + |Ireg2, Mreg2, Lreg2|= Ireg1 ; + + DM(Ireg1 += Mreg1) = |Ireg2, Mreg2, Lreg2|, + |Ireg2, Mreg2, Lreg2| = Ireg1 ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Indirect DAG Register Write (premodify or postmodify), with + DAG Register Move” on page 7-45 + + + + + ADSP-219x Instruction Set Reference 9-55 + Instruction Opcodes + + + + +Type 33: Reg3 «··· Data12 + Load short constants +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 11 + 0 0 0 1 0 0 0 0 12-bit data + + + 10 9 8 7 6 5 4 3 2 1 0 + 12-bit data REG3 + + +SYNTAX + + Reg3 = ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Direct Register Load” on page 7-27 + + + + +9-56 ADSP-219x Instruction Set Reference + Type 34: Dreg «···» IOreg + I/O register read/write +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 0 1 2MSBs addr D + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8-bit Address DREG + + +SYNTAX + + IO() = Dreg; + + Dreg = IO (); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “External IO Port Read/Write” on page 7-59 + + + + + ADSP-219x Instruction Set Reference 9-57 + Instruction Opcodes + + + + +Type 35: Dreg «···»Sreg + System control register read/write +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 0 0 D + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8-bit Address DREG + + +SYNTAX + + REG() = Dreg; + + Dreg = REG(); + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “System Control Register Read/Write” on page 7-61 + + + + +9-58 ADSP-219x Instruction Set Reference + Type 36: Long Jump/Call + Conditional long jump/call (two-word instruction) +OPCODE BITS + + • First word + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 0 1 S + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 8 Address MSBs COND + + + • Second word + + 23 22 21 20 19 18 17 16 15 14 13 12 + 16 Address LSBs + + + 11 10 9 8 7 6 5 4 3 2 1 0 + 16 Address LSBs + + +SYNTAX + + [IF Cond] LJUMP ; + + [IF Cond] LCALL ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Long CALL” on page 8-37 + • “Long JUMP” on page 8-40 + + + + + ADSP-219x Instruction Set Reference 9-59 + Instruction Opcodes + + + + +Type 37: Interrupt + Software interrupt +OPCODE BITS + + + 23 22 21 20 19 18 17 16 15 14 13 12 + 0 0 0 0 0 1 1 1 0 + + + 11 10 9 8 7 6 5 4 3 2 1 0 + C BIT + + +SYNTAX + + SETINT ; + + CLRINT ; + +SEE ALSO + + • “Opcode Mnemonics” on page 9-1 + • “Set Interrupt” on page 8-62 + • “Clear Interrupt” on page 8-64 + + + + +9-60 ADSP-219x Instruction Set Reference + ADSP-219x Instruction Set Reference 9-61 + Instruction Opcodes + + + + +9-62 ADSP-219x Instruction Set Reference diff --git a/docs/opcode_mnemonics.txt b/docs/opcode_mnemonics.txt new file mode 100644 index 0000000..6989e19 --- /dev/null +++ b/docs/opcode_mnemonics.txt @@ -0,0 +1,812 @@ +9 INSTRUCTION OPCODES + Figure 9-0. + Table 9-0. + Listing 9-0. + + + + This chapter lists and describes the opcodes that defines each of the + instructions in the ADSP-219x’s instruction set. This information is use- + ful for debugging programs. + This chapter covers the following topics: + • “Opcode Mnemonics” on page 9-1 + • “Opcode Definitions” on page 9-20 + + +Opcode Mnemonics + This section lists, describes, and gives the numeric value for each opcode + mnemonic. + + Table 9-1. Opcode mnemonics + +Mnemonic Description Details + +AMF Specifies an ALU or multiplier operation. page 9-8 + +AS Specifies whether ALU saturation mode is page 9-40 + 0 = disabled + 1 = enabled + +B Specifies whether branch is page 9-32 + page 9-41 + 0 = immediate + page 9-42 + 1 = delayed + + + + + ADSP-219x Instruction Set Reference 9-1 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +BIT Specifies which interrupt to enable or disable (0–15). page 9-60 + +BO Specifies whether the supplied 4-bit constant in a type 9 instruction is page 9-12 + page 9-27 + 01 = as is + 11 = negated + +BR Specifies whether bit-reverse addressing on DAG1 is page 9-40 + 0 = disabled + 1 = enabled + +BSR Specifies whether the secondary DAG address registers are page 9-40 + 0 = disabled + 1 = enabled + +C Specifies whether a software interrupt is page 9-60 + 0 = set + 1 = cleared + +CC Specifies the two LSBs of a 4-bit constant value in a type 9 instruction. page 9-12 + page 9-27 + +CF Specifies whether to flush the instruction cache page 9-50 + 0 = No flush + 1 = flush + +COND Specifies one of the condition codes on which to base execution of the page 9-11 + instruction. + + + + +9-2 ADSP-219x Instruction Set Reference + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +D Specifies the direction of a data move. page 9-22 + page 9-35 + 0 = read + page 9-51 + 1 = write page 9-54 + page 9-57 + page 9-58 + +DD Specifies a destination data register for a DM bus transfer. page 9-21 + 00 = AX0 + 01 = AX1 + 10 = MX0 + 11 = MX1 + +DDREG Specifies a destination register for a register-to-register move operation. page 9-13 + +DREG Specifies an unrestricted data register (REG0 only). page 9-13 + +DMI Specifies a DAG index address register (I0–I3) for a DM bus transfer. page 9-18 + page 9-21 + +DMM Specifies a DAG modify address register (M0–M3) for a DM bus trans- page 9-18 + fer. page 9-21 + +DRGP Specifies a destination register group. page 9-39 + 00 = REG0 + 01 = REG1 + 10 = REG2 + 11 = REG3 + +DRL Specifies two MSBs of DREG data register address. page 9-13 + +DRU Specifies two LSBs of DREG data register address. page 9-13 + +Exponent Specifies an 8-bit, two’s-complement shift value. page 9-37 + + + + + ADSP-219x Instruction Set Reference 9-3 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +G Specifies a DAG register group. page 9-17 + 0 = DAG1 + 1 = DAG2 + +IREG/MREG Specifies DAG index and modify registers (I0–I7, M0–M7). page 9-18 + +I Specifies DAG index register (I0–I7). page 9-17 + +Idle Value Specifies a 4-bit value that defines an internal clock divisor. page 9-53 + +INT Specifies whether interrupts are globally page 9-40 + 0 = disabled + 1 = enabled + +LPP Specifies push/pop of the loop stacks. page 9-50 + 0 = disabled + 1 = enabled + +M Specifies a DAG modify register. page 9-17 + +MM Specifies whether MAC integer mode is page 9-40 + 0 = disabled + 1 = enabled + +MOD DATA Specifies an 8-bit, two’s-complement immediate data value. page 9-44 + page 9-51 + +MS Specifies memory bus for a memory data transfer page 9-54 + 0 = 16-bit DM bus + 1 = 24-bit PM bus + + + + +9-4 ADSP-219x Instruction Set Reference + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +OL Specifies whether ALU overflow mode is page 9-40 + 0 = disabled + 1 = enabled + +PD Specifies a destination data register for a PM bus transfer. page 9-21 + 00 = AY0 + 01 = AY1 + 10 = MY0 + 11 = MY1 + +PMI Specifies a DAG index address register (I4–I7) for a PM bus transfer. page 9-18 + +PMM Specifies a DAG modify address register (M4–M7) for a PM bus trans- page 9-18 + fer. + +PPP Specifies push/pop of the PC stack. page 9-50 + 0 = disabled + 1 = enabled + +Q Specifies the RTI mode. page 9-42 + 0 = normal + 1 = single-step + +R Specifies a result register. page 9-49 + 0 = MR register + 1 = SR register + +REG Specifies a core register of RGPx. page 9-13 + +REG1 Specifies a register group 1 register page 9-13 + page 9-25 + + + + + ADSP-219x Instruction Set Reference 9-5 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +REG2 Specifies a register group 2 register page 9-13 + page 9-25 + +REG3 Specifies a register group 3 register page 9-13 + page 9-56 + +RGP Specifies a register group. page 9-13 + 00 = REG0 + 01 = REG1 + 10 = REG2 + 11 = REG3. + +S Specifies the branch type. page 9-32 + page 9-41 + 0 = jump + 1 = call + +SDREG Specifies the source data register for a data move operation. page 9-13 + +SF Specifies a shift function. page 9-15 + +SPP Specifies push/pop of the status stack. page 9-50 + 0 = disabled + 1 = enabled + +SR Specifies whether the secondary data registers are page 9-40 + 0 = disabled + 1 = enabled + + + + +9-6 ADSP-219x Instruction Set Reference + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +SRGP Specifies a source register group for a data move operation. page 9-39 + 00 = REG0 + 01 = REG1 + 10 = REG2 + 11 = REG3 + +SWCD Specifies a 4-bit nonfunctional value used by ADI tools only. page 9-52 + +T Specifies the return type. page 9-42 + 0 = RTS + 1 = RTI + +TERM Specifies the terminating condition for the type 11 instruction. page 9-34 + 1110 = NOT CE + 1111 = TRUE + +TI Specifies whether the timer is page 9-40 + 0 = disabled + 1 = enabled + +U Specifies whether the DAG index register is page 9-54 + 0 = premodified with no update + 1 = postmodified with update + +XOP Specifies a restricted data register used to supply the x operand value in page 9-19 + a multifunction or conditional instruction. + +XREG Specifies the source register (REG0) in a shift function. page 9-13 + + + + + ADSP-219x Instruction Set Reference 9-7 + Instruction Opcodes + + + + + Table 9-1. Opcode mnemonics (Cont’d) + +Mnemonic Description Details + +Y0 Specifies whether the source of the x-operand is page 9-11 + 0 = data register + 1 = 0 (explicit value) + +YOP Specifies a restricted data register used to supply the y operand value in page 9-19 + a multifunction or conditional instruction. + +YREG Specifies the destination register (REG0) in a shift function. page 9-13 + page 9-11 + +YY Specifies the two MSBs of a 4-bit constant value in a type 9 instruc- page 9-12 + tion. page 9-27 + +Z Specifies a result or feedback register page 9-23 + page 9-26 + 0 = result register + page 9-27 + 1 = feedback register page 9-11 + + +ALU or Multiplier Function (AMF) Codes + Table 9-2 on page 9-9 lists the AMF codes used by these instruction types: + • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21 + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26 + • “Type 9: Compute” on page 9-27 + + + + +9-8 ADSP-219x Instruction Set Reference + Table 9-2. ALU/multiplier function (AMF) codes + +Code Function Description + +Multiplier functions + +00000 NOP No operation + +00001 X * Y (RND) Multiply + +00010 MR + X * Y (RND) Multiply and accumulate + +00011 MR – X * Y (RND) Multiply and subtract + +00100 X * Y (SS) Multiply + +00101 X * Y (SU) Multiply + +00110 X * Y (US) Multiply + +00111 X * Y (UU) Multiply + +01000 MR + X * Y (SS) Multiply and accumulate + +01001 MR + X * Y (SU) Multiply and accumulate + +01010 MR + X * Y (US) Multiply and accumulate + +01011 MR + X * Y (UU) Multiply and accumulate + +01100 MR – X * Y (SS) Multiply and subtract + +01101 MR – X * Y (SU) Multiply and subtract + +01110 MR – X * Y (US) Multiply and subtract + +01111 MR – X * Y (UU) Multiply and subtract + +(RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned; +(US) =x operand unsigned, y operand signed; (UU) = both operands unsigned + + + + + ADSP-219x Instruction Set Reference 9-9 + Instruction Opcodes + + + + + Table 9-2. ALU/multiplier function (AMF) codes (Cont’d) + +Code Function Description + +ALU functions + +10000 Y PASS/CLEAR + +10001 Y+1 PASS + +10010 X+Y+C Add with carry + +10011 X+Y Add + +10100 NOT Y Negate + +10101 –Y PASS + +10110 X–Y+C–1 Subtract (X–Y) with borrow + +10111 X–Y Subtract + +11000 Y–1 PASS + +11001 Y–X Subtract + +11010 Y–X+C–1 Subtract (Y–X) with borrow + +11011 NOT X Negate + +11100 X AND Y AND/test bit,clear bit + +11101 X OR Y OR/set bit + +11110 X XOR Y XOR/toggle bit + +11111 ABS X Absolute value + + (RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned; + (US) =x operand unsigned, y operand signed; (UU) = both operands unsigned + + + + +9-10 ADSP-219x Instruction Set Reference + Condition Codes + Table 9-3 on page 9-11 lists the condition codes used by these instruction + types: + • “Type 9: Compute” on page 9-27 + • “Type 10: Direct Jump” on page 9-32 + • “Type 16: Shift Reg0” on page 9-38 + • “Type 19: Indirect Jump/Call” on page 9-41 + • “Type 20: Return” on page 9-42 + • “Type 36: Long Jump/Call” on page 9-59 + • “Type 11: Do ··· Until” on page 9-34 + uses NOT CE and TRUE only for the terminating condition. + + Table 9-3. Condition codes + +Code Condition Description + +0000 EQ Equal to 0 (= 0) + +0001 NE Not equal to 0 (≠ 0) + +0010 GT Greater than 0 (>0) + +0011 LE Less than or equal to 0 (≤0) + +0100 LT Less than 0 (<0) + +0101 GE Greater than or equal to 0 (≥0) + +0110 AV ALU overflow + +0111 NOT AV Not ALU overflow + + + + + ADSP-219x Instruction Set Reference 9-11 + Instruction Opcodes + + + + + Table 9-3. Condition codes (Cont’d) + +Code Condition Description + +1000 AC ALU carry + +1001 NOT AC Not ALU carry + +1010 SWCOND CCODE register condition + +1011 NOT SWCOND Not CCODE register condition + +1100 MV MAC overflow + +1101 NOT MV Not MAC overflow + +1110 NOT CE Counter not expired + +1111 TRUE Always true + + +Constant Codes + Table 9-4 lists the valid constants used by “Type 9: Compute” on + page 9-27. As shown, the YY/CC bits determine the constant value and the + BO bits determine the sign of the value. + + + Table 9-4. Constants + +Code Decimal / Hex Decimal / Hex + +YY CC BO = 01 BO = 11 + + 00 00 1 / 0x0001 −2 / 0xFFFE + + 00 01 2 / 0x0002 −3 / 0xFFFD + + 00 10 4 / 0x0004 −5 / 0xFFFB + + 00 11 8 / 0x0008 −9 / 0xFFF7 + + + + +9-12 ADSP-219x Instruction Set Reference + Table 9-4. Constants (Cont’d) + +Code Decimal / Hex Decimal / Hex + +YY CC BO = 01 BO = 11 + + 01 00 16 / 0x0010 −17 / 0xFFEF + + 01 01 32 / 0x0020 −33 / 0xFFDF + + 01 10 64 / 0x0040 −65 / 0xFFBF + + 01 11 128 / 0x0080 −129 / 0xFF7F + + 10 00 256 / 0x0100 −257 / 0xFEFF + + 10 01 512 / 0x0200 −513 / 0xFDFF + + 10 10 1024 / 0x0400 −1025 / 0xFBFF + + 10 11 2048 / 0x0800 −2049 / 0xF7FF + + 11 00 4096 / 0x1000 −4097 / 0xEFFF + + 11 01 8192 / 0x2000 −8193 / 0xDFFF + + 11 10 16384 / 0x4000 −16385 / 0xBFFF + + 11 11 −32768 / 0x8000 +32767 / 0x7FFF + + +Core Register Codes + Table 9-5 on page 9-14 list the core registers and their addresses. The + complete address of any individual register is formed by appending the + register’s address bits to its RGP bits, so, for example, the address of the I2 + register is 010010. The opcode mnemonics DREG, DDREG, SDREG, XREG, and + YREG and the following instruction types reference these registers by their + address bits: + • “Type 3: Dreg/Ireg/Mreg «···» DM/PM” on page 9-22 + + + + ADSP-219x Instruction Set Reference 9-13 + Instruction Opcodes + + + + + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 6: Dreg «··· Data16” on page 9-24 + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26 + • “Type 9: Compute” on page 9-27 + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36 + • “Type 15: Shift Data8” on page 9-37 + • “Type 16: Shift Reg0” on page 9-38 + • “Type 17: Any Reg «··· Any Reg” on page 9-39 + • “Type 34: Dreg «···» IOreg” on page 9-57 + • “Type 35: Dreg «···»Sreg” on page 9-58 + + Table 9-5. Core registers + +RGP/Address Register Groups (RGP) + +Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3) + +0000 AX0 I0 I4 ASTAT + +0001 AX1 I1 I5 MSTAT + +0010 MX0 I2 I6 SSTAT + +0011 MX1 I3 I7 LPSTACKP + +0100 AY0 M0 M4 CCODE + +0101 AY1 M1 M5 SE + +0110 MY0 M2 M6 SB + + + + +9-14 ADSP-219x Instruction Set Reference + Table 9-5. Core registers (Cont’d) + +RGP/Address Register Groups (RGP) + +Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3) + +0111 MY1 M3 M7 PX + +1000 MR2 L0 L4 DMPG1 + +1001 SR2 L1 L5 DMPG2 + +1010 AR L2 L6 IOPG + +1011 SI L3 L7 IJPG + +1100 MR1 IMASK Reserved Reserved + +1101 SR1 IRPTL Reserved Reserved + +1110 MR0 ICNTL CNTR Reserved + +1111 SR0 STACKA LPSTACKA STACKP + + +SF Function Codes + Table 9-6 list the shift function (SF) codes used by these instruction types: + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36 + • “Type 15: Shift Data8” on page 9-37 + —shift functions (codes 0000–0111) only + • “Type 16: Shift Reg0” on page 9-38 + + + + + ADSP-219x Instruction Set Reference 9-15 + Instruction Opcodes + + + + + Table 9-6. SF codes + +Code Function + + 0000 LSHIFT (HI) + + 0001 LSHIFT (HI, OR) + + 0010 LSHIFT (LO) + + 0011 LSHIFT (LO, OR) + + 0100 ASHIFT (HI) + + 0101 ASHIFT (HI, OR) + + 0110 ASHIFT (LO) + + 0111 ASHIFT (LO, OR) + + 1000 NORM (HI) + + 1001 NORM (HI, OR) + + 1010 NORM (LO) + + 1011 NORM (LO, OR) + + 1100 EXP (HI) + + 1101 EXP (HIX) + + 1110 EXP (LO) + + 1111 Derive Block Exponent + + + + +9-16 ADSP-219x Instruction Set Reference + I and M Codes + Table 9-7 on page 9-17 lists the DAG index and modify register codes + used by the following instruction types. The G bit (DAG1/DAG2) determines + which group of I (index) and M (modify) registers. + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23. + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 19: Indirect Jump/Call” on page 9-41 + • “Type 21: Modify DagI” on page 9-43 + • “Type 21a: Modify DagI” on page 9-44 + • “Type 22: DM/PM «··· Data16” on page 9-45 + • “Type 29: Dreg «···» DM” on page 9-51 + • “Type 32: Any Reg «···» PM/DM” on page 9-54 + + Table 9-7. I and M codes + + DAG1 (G=0) DAG2 (G=1) + +Code I M I M + +00 I0 M0 I4 M4 + +01 I1 M1 I5 M5 + +10 I2 M2 I6 M6 + +11 I3 M3 I7 M7 + + + + + ADSP-219x Instruction Set Reference 9-17 + Instruction Opcodes + + + + +DMI, DMM, PMI, and PMM Codes + Table 9-8 lists the DAG index and modify register codes used by “Type 1: + Compute | DregX«···DM | DregY«···PM” on page 9-21. + + Table 9-8. DMI, DMM, PMI, PMM codes + +Code DMI DMM PMI PMM + + 00 I0 M0 I4 M4 + + 01 I1 M1 I5 M5 + + 10 I2 M2 I6 M6 + + 11 I3 M3 I7 M7 + + +IREG/MREG Codes + Table 9-9 lists the Ireg and Mreg codes used by “Type 3: Dreg/Ireg/Mreg + «···» DM/PM” on page 9-22 to specify a DAG index or modify register. + + Table 9-9. Ireg, Mreg codes + +Code Register Code Register + + 0000 I0 1000 M0 + + 0001 I1 1001 M1 + + 0010 I2 1010 M2 + + 0011 I3 1011 M3 + + 0100 I4 1100 M4 + + 0101 I5 1101 M5 + + + + +9-18 ADSP-219x Instruction Set Reference + Table 9-9. Ireg, Mreg codes (Cont’d) + +Code Register Code Register + +0110 I6 1110 M6 + +0111 I7 1111 M7 + + +XOP and YOP Codes + Table 9-10 on page 9-19 lists the XOP and YOP codes used by these + instructions: + • “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21 + • “Type 4: Compute | Dreg «···» DM/PM” on page 9-23 + • “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26 + • “Type 9: Compute” on page 9-27 + • “Type 12: Shift | Dreg «···» DM/PM” on page 9-35 + • “Type 23: Divide primitive, DIVQ” on page 9-47 + • “Type 24: Divide primitive, DIVS” on page 9-48 + + Table 9-10. XOP/YOP codes + + XOP YOP + +Code ALU MAC Shift Code ALU MAC + + 000 AX0 MX0 SI 00 AY0 MY0 + + 001 AX1 MX1 SR2 01 AY1 MY1 + + 010 AR AR AR 10 AF SR1 + + + + + ADSP-219x Instruction Set Reference 9-19 + Instruction Opcodes + + + + + Table 9-10. XOP/YOP codes + + XOP YOP + + Code ALU MAC Shift Code ALU MAC + + 011 MR0 MR0 MR0 11 0 0 + + 100 MR1 MR1 MR1 + + 101 MR2 MR2 MR2 + + 110 SR0 SR0 SR0 + + 111 SR1 SR1 SR1 + + + +Opcode Definitions diff --git a/testrom/gen_testrom.py b/testrom/gen_testrom.py new file mode 100644 index 0000000..912c1a8 --- /dev/null +++ b/testrom/gen_testrom.py @@ -0,0 +1,37 @@ +import sys +import struct +import os + +# Opcode constants +TYPE1_NOP = 0xC00000 +TYPE6_AX0 = 0x400000 +TYPE10_JUMP_ALWAYS = 0x18000F +TYPE30_NOP = 0x000000 + +def create_rom(filename, format=3): + """ + Creates a synthetic ADSP-219x ROM with known instruction patterns. + """ + os.makedirs(os.path.dirname(filename), exist_ok=True) + instructions = [ + TYPE30_NOP, # 0x0000: NOP + TYPE6_AX0 | (0x1234 << 4), # 0x0001: AX0 = 0x1234 + TYPE10_JUMP_ALWAYS | (0x0100 << 4), # 0x0002: JUMP 0x0100 + # ... add more test patterns ... + ] + + with open(filename, "wb") as f: + for ins in instructions: + if format == 3: + # Big-endian 3-byte pack + f.write(struct.pack(">I", ins)[1:]) + else: + # Big-endian 4-byte pad + f.write(struct.pack(">I", ins)) + +if __name__ == "__main__": + # Ensure full path to base_test.bin + base_dir = os.path.dirname(os.path.abspath(__file__)) + create_rom(os.path.join(base_dir, "test_roms/base_test.bin"), 3) + create_rom(os.path.join(base_dir, "test_roms/padded_test.bin"), 4) + print("Test ROMs generated in test_roms/") diff --git a/testrom/test_roms/base_test.bin b/testrom/test_roms/base_test.bin new file mode 100644 index 0000000..91c18da Binary files /dev/null and b/testrom/test_roms/base_test.bin differ diff --git a/testrom/test_roms/padded_test.bin b/testrom/test_roms/padded_test.bin new file mode 100644 index 0000000..4c79ee4 Binary files /dev/null and b/testrom/test_roms/padded_test.bin differ