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Fix Type 12 SF field and sync TESTING.md

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Type 12: SF is 4 bits (15-12), D is bit11 (not SF=3bits, D=bit12).
  Verified all 8 SF variants against assembler: LSHIFT/ASHIFT,
  HI/LO, plain/OR.  FIR output scaling chain now correct.

TESTING.md: Synced with actual verification status.
  34 of 37 types now assembler-verified.
  Only Type 22/22a (2-word data write), Type 31 (IDLE), and
  Type 32a (DAG store+transfer) remain structural-only.

Removed build artifacts (.o, .elf) from examples/build/.
This commit is contained in:
Dr. Christian Giessen
2026-04-22 20:19:41 +00:00
parent 9a82c4d522
commit 6dd976fcf6
6 changed files with 47 additions and 37 deletions
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9
r2plugin/asm_adsp219x.c
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@@ -445,12 +445,15 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask)
return true;
}
/* Type 12: Shift | DM/PM (bits 23-17 = 0001001) */
/* Type 12: Shift | DM/PM (bits 23-17 = 0001001)
G=bit16, SF=bits15-12 (4 bits, same as sf_names[]),
D=bit11 (0=read, 1=write), XOP=bits10-8 (xop_shift),
DREG=bits7-4, I=bits3-2, M=bits1-0. */
if ((ins >> 17) == 0x09)
{
ut32 g = (ins >> 16) & 1;
ut32 sf = (ins >> 13) & 0x7;
ut32 d = (ins >> 12) & 1;
ut32 sf = (ins >> 12) & 0xF;
ut32 d = (ins >> 11) & 1;
ut32 xop_i = (ins >> 8) & 0x7;
ut32 dreg = (ins >> 4) & 0xF;
ut32 ireg = (ins >> 2) & 0x3;