Compliance update: GNU Coding Standards for C, relative paths in Python, and updated README.
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/* ADSP-219x radare2 arch plugin - Precise Opcode Table Implementation */
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/* asm_adsp219x.c -- Radare2 architecture plugin for Analog Devices ADSP-219x
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Copyright (C) 2026 OpenClaw
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This file is part of our reverse engineering project for ADSP-219x.
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It implements the disassembler via the RArchPlugin interface. */
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#include <r_arch.h>
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static const char *cond_str[] = { "EQ", "NE", "GT", "LE", "LT", "GE", "AV", "NOT AV", "AC", "NOT AC", "SWCOND", "NOT SWCOND", "MV", "NOT MV", "NOT CE", "TRUE" };
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static const char *reg0[] = { "AX0", "AX1", "MX0", "MX1", "AY0", "AY1", "MY0", "MY1", "MR2", "SR2", "AR", "SI", "MR1", "SR1", "MR0", "SR0" };
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static const char *reg1[] = { "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", "L0", "L1", "L2", "L3", "IMASK", "IRPTL", "ICNTL", "CNTR" };
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static const char *reg2[] = { "I4", "I5", "I6", "I7", "M4", "M5", "M6", "M7", "L4", "L5", "L6", "L7", "STACKA", "LPCSTACKA", "RES", "RES" };
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static const char *reg3[] = { "ASTAT", "MSTAT", "SSTAT", "LPSTACKP", "CCODE", "SE", "SB", "PX", "DMPG1", "DMPG2", "IOPG", "IJPG", "RES", "RES", "RES", "STACKP" };
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/* Register name definitions for ADSP-219x. */
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static const char *cond_str[] =
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{ "EQ", "NE", "GT", "LE", "LT", "GE", "AV", "NOT AV", "AC", "NOT AC", "SWCOND", "NOT SWCOND", "MV", "NOT MV", "NOT CE", "TRUE" };
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static const char *get_reg(int gp, int idx) {
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switch (gp & 3) {
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case 0: return reg0[idx & 0xF];
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case 1: return reg1[idx & 0xF];
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case 2: return reg2[idx & 0xF];
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case 3: return reg3[idx & 0xF];
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}
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return "??";
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static const char *reg0[] =
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{ "AX0", "AX1", "MX0", "MX1", "AY0", "AY1", "MY0", "MY1", "MR2", "SR2", "AR", "SI", "MR1", "SR1", "MR0", "SR0" };
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static const char *reg1[] =
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{ "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", "L0", "L1", "L2", "L3", "IMASK", "IRPTL", "ICNTL", "CNTR" };
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static const char *reg2[] =
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{ "I4", "I5", "I6", "I7", "M4", "M5", "M6", "M7", "L4", "L5", "L6", "L7", "STACKA", "LPCSTACKA", "RESERVED", "RESERVED" };
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static const char *reg3[] =
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{ "ASTAT", "MSTAT", "SSTAT", "LPSTACKP", "CCODE", "SE", "SB", "PX", "DMPG1", "DMPG2", "IOPG", "IJPG", "RES", "RES", "RES", "STACKP" };
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/* Returns the name of a register given its group GP and index IDX. */
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static const char *
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get_reg (int gp, int idx)
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{
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switch (gp & 0x3)
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{
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case 0:
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return reg0[idx & 0xF];
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case 1:
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return reg1[idx & 0xF];
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case 2:
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return reg2[idx & 0xF];
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case 3:
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return reg3[idx & 0xF];
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default:
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return "??";
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}
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}
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static bool decode(RArchSession *as, RAnalOp *op, RAnalOpMask mask) {
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if (op->size < 3) return false;
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const ut8 *b = op->bytes;
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ut32 ins = ((ut32)b[0] << 16) | ((ut32)b[1] << 8) | (ut32)b[2];
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op->size = 3; op->type = R_ANAL_OP_TYPE_UNK;
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if (!(mask & R_ARCH_OP_MASK_DISASM)) return true;
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/* Decodes the instruction at current OP position using MASK. */
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static bool
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decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask)
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{
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ut32 ins;
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const ut8 *b = op->bytes;
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/* Top bits classification */
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ut32 b23_22 = (ins >> 22) & 3;
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ut32 top8 = (ins >> 16) & 0xFF;
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if (op->size < 3)
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return false;
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/* Type 30/31: NOP / IDLE */
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if (top8 == 0x00) {
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if (ins == 0) { op->mnemonic = strdup("NOP"); op->type = R_ANAL_OP_TYPE_NOP; }
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else { op->mnemonic = r_str_newf("IDLE 0x%X", ins & 0xFF); op->type = R_ANAL_OP_TYPE_TRAP; }
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return true;
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}
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ins = ((ut32) b[0] << 16) | ((ut32) b[1] << 8) | (ut32) b[2];
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op->size = 3;
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op->type = R_ANAL_OP_TYPE_UNK;
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/* Type 1: Multifunction (11xxxx) */
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if (b23_22 == 3) {
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op->mnemonic = r_str_newf("multifunc 0x%06X", ins); return true;
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}
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if (!(mask & R_ARCH_OP_MASK_DISASM))
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return true;
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/* Type 3: Direct Memory (10xxxx) */
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if (b23_22 == 2) {
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ut32 d = (ins >> 20) & 1, addr = (ins >> 4) & 0xFFFF, reg = ins & 0xF;
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op->mnemonic = r_str_newf("%s %s DM(0x%04X)", reg0[reg], d?"=":"=", addr); return true;
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}
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/* Basic opcode classification based on high bits. */
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ut32 top_bits_2 = (ins >> 22) & 0x3;
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ut32 top_bits_8 = (ins >> 16) & 0xFF;
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/* Type 6/7/IO/Reg (01xxxx) */
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if (b23_22 == 1) {
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ut32 top4 = (ins >> 20) & 0xF;
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if (top4 == 4) { ut32 val = (ins >> 4) & 0xFFFF, dr = ins & 0xF; op->mnemonic = r_str_newf("%s = 0x%04X", reg0[dr], val); return true; }
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if (top4 == 5) { ut32 val = (ins >> 4) & 0xFFFF, dr = ins & 0xF; op->mnemonic = r_str_newf("%s = 0x%04X", reg1[dr], val); return true; }
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if (top8 == 0x6D) { ut32 addr = (ins >> 4) & 0xFF, dr = ins & 0xF; op->mnemonic = r_str_newf("IO(0x%02X) = %s", addr, reg0[dr]); return true; }
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if (top8 == 0x6C) { ut32 addr = (ins >> 4) & 0xFF, dr = ins & 0xF; op->mnemonic = r_str_newf("REG(0x%02X) = %s", addr, reg0[dr]); return true; }
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}
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/* Type 30/31: NOP / IDLE commands. */
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if (top_bits_8 == 0x00)
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{
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if (ins == 0)
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{
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op->mnemonic = strdup ("NOP");
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op->type = R_ANAL_OP_TYPE_NOP;
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}
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else
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{
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op->mnemonic = r_str_newf ("IDLE 0x%X", ins & 0xFF);
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op->type = R_ANAL_OP_TYPE_TRAP;
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}
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return true;
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}
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/* Groups under (00xxxx) */
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if (b23_22 == 0) {
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ut32 top4 = (ins >> 20) & 0xF;
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if (top4 == 3) { ut32 val = (ins >> 4) & 0xFFFF, dr = ins & 0xF; op->mnemonic = r_str_newf("%s = 0x%04X", reg2[dr], val); return true; }
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if ((ins >> 19) == 3) {
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ut32 db = (ins >> 18) & 1, s = (ins >> 17) & 1, addr = (ins >> 4) & 0x1FFF, cond = ins & 0xF;
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op->mnemonic = r_str_newf("%s%s %s 0x%04X%s", (cond==15?"":"IF "), (cond==15?"":cond_str[cond]), (s?"CALL":"JUMP"), addr, (db?" (DB)":""));
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if (db) op->delay = 1; return true;
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}
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if ((ins >> 18) == 7) {
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ut32 addr = (ins >> 4 & 0x3FFF) | (ins & 3) << 14, db = (ins >> 3) & 1, s = (ins >> 2) & 1;
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op->mnemonic = r_str_newf("%s 0x%05X%s", (s?"CALL":"JUMP"), addr, (db?" (DB)":""));
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if (db) op->delay = 1; return true;
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}
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if (top8 == 0x0A) {
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ut32 t = (ins >> 14) & 1, cond = ins & 0xF;
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op->mnemonic = r_str_newf("%s%s %s", (cond==15?"":"IF "), (cond==15?"":cond_str[cond]), (t?"RTI":"RTS")); return true;
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}
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if (top8 == 0x0D) {
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ut32 drgp = (ins >> 10) & 3, srgp = (ins >> 8) & 3, dr = (ins >> 4) & 0xF, sr = ins & 0xF;
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op->mnemonic = r_str_newf("%s = %s", get_reg(drgp, dr), get_reg(srgp, sr)); return true;
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}
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}
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/* Type 1: Multifunction (11xxxx). */
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if (top_bits_2 == 0x3)
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{
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op->mnemonic = r_str_newf ("compute_dm_pm 0x%06X", ins);
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return true;
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}
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op->mnemonic = r_str_newf("unk 0x%06X", ins);
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return true;
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/* Type 3: Direct Memory access (10xxxx). */
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if (top_bits_2 == 0x2)
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{
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ut32 write_flag = (ins >> 20) & 0x1;
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ut32 address = (ins >> 4) & 0xFFFF;
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ut32 register_idx = ins & 0xF;
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op->mnemonic = r_str_newf ("%s %s DM(0x%04X)",
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reg0[register_idx],
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write_flag ? "=" : "=", address);
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return true;
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}
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/* Instructions starting with 01xxxx. */
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if (top_bits_2 == 0x1)
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{
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ut32 top_bits_4 = (ins >> 20) & 0xF;
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if (top_bits_4 == 0x4)
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{
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/* Type 6: Dreg = Imm16. */
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op->mnemonic = r_str_newf ("%s = 0x%04X", reg0[ins & 0xF], (ins >> 4) & 0xFFFF);
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return true;
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}
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if (top_bits_4 == 0x5)
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{
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/* Type 7: Reg1 = Imm16. */
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op->mnemonic = r_str_newf ("%s = 0x%04X", reg1[ins & 0xF], (ins >> 4) & 0xFFFF);
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return true;
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}
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if (top_bits_8 == 0x6D)
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{
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/* Type 34: IO Register load. */
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op->mnemonic = r_str_newf ("IO(0x%02X) = %s", (ins >> 4) & 0xFF, reg0[ins & 0xF]);
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return true;
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}
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if (top_bits_8 == 0x6C)
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{
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/* Type 35: System Register load. */
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op->mnemonic = r_str_newf ("REG(0x%02X) = %s", (ins >> 4) & 0xFF, reg0[ins & 0xF]);
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return true;
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}
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}
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/* Instructions starting with 00xxxx. */
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if (top_bits_2 == 0x0)
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{
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ut32 top_bits_4 = (ins >> 20) & 0xF;
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if (top_bits_4 == 0x3)
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{
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/* Type 7: Reg2 = Imm16. */
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op->mnemonic = r_str_newf ("%s = 0x%04X", reg2[ins & 0xF], (ins >> 4) & 0xFFFF);
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return true;
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}
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if ((ins >> 19) == 0x3)
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{
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/* Type 10: Jump/Call. */
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ut32 delay_slot = (ins >> 18) & 0x1;
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ut32 sub_flag = (ins >> 17) & 0x1;
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ut32 jump_addr = (ins >> 4) & 0x1FFF;
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ut32 condition = ins & 0xF;
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op->mnemonic = r_str_newf ("%s%s %s 0x%04X%s",
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(condition == 15 ? "" : "IF "),
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(condition == 15 ? "" : cond_str[condition]),
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(sub_flag ? "CALL" : "JUMP"), jump_addr,
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delay_slot ? " (DB)" : "");
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if (delay_slot)
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op->delay = 1;
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return true;
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}
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if (top_bits_8 == 0x0D)
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{
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/* Type 17: Register-to-Register move. */
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ut32 dest_gp = (ins >> 10) & 0x3;
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ut32 src_gp = (ins >> 8) & 0x3;
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ut32 dest_idx = (ins >> 4) & 0xF;
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ut32 src_idx = ins & 0xF;
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op->mnemonic = r_str_newf ("%s = %s", get_reg (dest_gp, dest_idx), get_reg (src_gp, src_idx));
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return true;
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}
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}
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op->mnemonic = r_str_newf ("unk 0x%06X", ins);
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return true;
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}
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static int archinfo(RArchSession *s, ut32 q) {
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switch (q) {
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case R_ARCH_INFO_CODE_ALIGN: return 3;
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case R_ARCH_INFO_MINOP_SIZE: case R_ARCH_INFO_MAXOP_SIZE: return 3;
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default: return -1;
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}
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/* Returns the info corresponding to code alignment and op sizes. */
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static int
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archinfo (RArchSession *s, ut32 q)
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{
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switch (q)
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{
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case R_ARCH_INFO_CODE_ALIGN:
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return 3;
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case R_ARCH_INFO_MINOP_SIZE:
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case R_ARCH_INFO_MAXOP_SIZE:
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return 3;
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default:
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return -1;
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}
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}
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/* Definition of the RArchPlugin structure for ADSP-219x. */
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const RArchPlugin r_arch_plugin_adsp219x = {
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.meta = { .name = "adsp219x", .author = "OpenClaw", .desc = "ADSP-219x Full Disasm", .license = "LGPL-3.0-only" },
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.arch = "adsp219x", .bits = R_SYS_BITS_PACK(24), .endian = R_SYS_ENDIAN_BIG, .info = archinfo, .decode = (RArchPluginDecodeCallback)decode,
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.meta = {
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.name = "adsp219x",
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.author = "OpenClaw",
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.desc = "ADSP-219x (GNU Style Layout)",
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.license = "LGPL-3.0-only"
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},
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.arch = "adsp219x",
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.bits = R_SYS_BITS_PACK (24),
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.endian = R_SYS_ENDIAN_BIG,
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.info = archinfo,
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.decode = (RArchPluginDecodeCallback) decode,
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};
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#ifndef R2_PLUGIN_INCORE
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R_API RLibStruct radare_plugin = { .type = R_LIB_TYPE_ARCH, .data = &r_arch_plugin_adsp219x, .version = R2_VERSION };
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R_API RLibStruct radare_plugin = {
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.type = R_LIB_TYPE_ARCH,
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.data = (void *) &r_arch_plugin_adsp219x,
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.version = R2_VERSION
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};
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#endif
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