From 9a82c4d522bb18c81dc266a5cd65f13e98a75dc1 Mon Sep 17 00:00:00 2001 From: "Dr. Christian Giessen" Date: Wed, 22 Apr 2026 20:16:30 +0000 Subject: [PATCH] Verify and fix gap types against assembler output Assembler-verified and fixed: - Type 12: XOP field corrected to bits10-8 (was bits11-9) - Type 14: SF=4bits, XREG uses reg0[] not xop_shift[] (was 3-bit OOB) - Type 16: XREG uses reg0[] (was xop_shift[], 4-bit index OOB) - Type 19: I-reg field at bits3-2 (was bits1-0), now correct for jump(i2) - Type 26: Push/Pop encoding is 10/11 not 01/10; PPP=bits6-5, LPP=bits4-3 (was bits6-4, bits3-2) All 6 variants verified: push/pop sts, loop, pc Assembler-verified unchanged: - Type 21/21a: MODIFY correct - Type 23/24: DIVQ/DIVS correct - Type 29: DM immediate modify read/write correct - Type 32: Any Reg <-> DM read/write correct - Type 34/35: IO/System register read/write correct - Type 36: LJUMP 2-word correct - Type 37: SETINT/CLRINT correct Remaining note: Type 12 SF field may use a different mapping than sf_names[] for combined shift+memory ops (ASHIFT encodes as SF=2 not SF=4). Needs further investigation. --- examples/build/verify_gaps.bin | Bin 0 -> 120 bytes examples/build/verify_gaps.dsp | 83 +++++++++++++++++++++++++++++++++ examples/build/verify_gaps.elf | Bin 0 -> 340 bytes examples/build/verify_gaps.o | Bin 0 -> 564 bytes r2plugin/asm_adsp219x.c | 44 +++++++++-------- r2plugin/asm_adsp219x.so | Bin 28512 -> 28512 bytes 6 files changed, 107 insertions(+), 20 deletions(-) create mode 100644 examples/build/verify_gaps.bin create mode 100644 examples/build/verify_gaps.dsp create mode 100644 examples/build/verify_gaps.elf create mode 100644 examples/build/verify_gaps.o diff --git a/examples/build/verify_gaps.bin b/examples/build/verify_gaps.bin new file mode 100644 index 0000000000000000000000000000000000000000..a9a17482c0a568ca3d48fc534216e06892b6016d GIT binary patch literal 120 zcmWN}u?>ST5J1rnz8H`td_qP_k-`cKcm$_Qc_T22N5}|_#4M>IrAgiZ&y8Xe|NTtnyuC#Y~0s<2P!q`KB)wZk|33lClya0A DM (postmodify) */ + ar = dm(i0,m0); + dm(i0,m0) = ar; + + /* Type 34: IO */ + ax0 = io(0x00); + io(0x00) = ax0; + + /* Type 35: System register */ + ax0 = reg(0x00); + reg(0x00) = ax0; + + /* Type 37: SETINT/CLRINT */ + setint 3; + clrint 3; + + /* Type 36: Long jump */ + ljump _end; + +_end: + nop; +_halt: + jump _halt; diff --git a/examples/build/verify_gaps.elf b/examples/build/verify_gaps.elf new file mode 100644 index 0000000000000000000000000000000000000000..fbf888cdad6f3f17cb2a683e872fc254b5fcc631 GIT binary patch literal 340 zcma)%J#NB45QV?}iNUgjSI9^yC@i2z6}jL5PLU`@iY@3Nh=u}$zy)1=gdBkbQE-5q zB2}a`nH6lGk)CGXd$Y6qKAzuRlv2dfOjeOiMf|!MQ%V#M7_@Yl1zlgwqqKm|mEs*$ ziKnP2Jl%@!)3~nl-#%skl_Jx4?x2;PKGxoA)K_Z8P6(MEGB&G8Qt)|6RxwvV}acf@cJ= NNBt}Z7s<^J^bbBT8g2jp literal 0 HcmV?d00001 diff --git a/examples/build/verify_gaps.o b/examples/build/verify_gaps.o new file mode 100644 index 0000000000000000000000000000000000000000..3b713e9a4a132fb03f5a919182656084d4cf36df GIT binary patch literal 564 zcma)2K}y3w6n&FS(}qYpgcd})sI;i75Wxe)MWvvNxj~FJY9XyM9YI(22p*va@Gw1& z;Ko0hjJou}|L?v3|73pVZF+UV7=r`DWd7@bsxfEvzzJILAO+G9B>E}(5}g#C^Kq8- zzG95x8TygejnIvH5?+K)I>$C(kp2$-1{@xT&mlPWIWmsx5F!*}kZlKY8*C7~BLD({ zHvBfmE%fYaL*ST{@T{$fq;K^z(abHKthLg`4W88Fy(*R|lJ)D-6!Nt$lty0M=~Cs3 z)qJ7KTa84ORgwHm=jCdS{Gq6{{r2BHC1ZB5U^pbvY)6VAqkKeR!EoRtv7r8c5z?TU zZZ`+a+rKp0km;FUcWi0~JBrI%+2n4F$u`ecH-^-ZO^p+qIYDtsVZ6f!i3x?f%gpUj Fd;@c~FhBqR literal 0 HcmV?d00001 diff --git a/r2plugin/asm_adsp219x.c b/r2plugin/asm_adsp219x.c index b8056d5..c2366d7 100644 --- a/r2plugin/asm_adsp219x.c +++ b/r2plugin/asm_adsp219x.c @@ -451,7 +451,7 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask) ut32 g = (ins >> 16) & 1; ut32 sf = (ins >> 13) & 0x7; ut32 d = (ins >> 12) & 1; - ut32 xop_i = (ins >> 9) & 0x7; + ut32 xop_i = (ins >> 8) & 0x7; ut32 dreg = (ins >> 4) & 0xF; ut32 ireg = (ins >> 2) & 0x3; ut32 mreg = ins & 0x3; @@ -469,32 +469,36 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask) return true; } - /* Type 14: Shift | Dreg move (bits 23-16 = 00010100) */ + /* Type 14: Shift | Dreg move (bits 23-16 = 00010100) + SF=bits15-12 (4 bits), XREG=bits11-8 (reg0 index), + DDREG=bits7-4, SDREG=bits3-0. */ if ((ins >> 16) == 0x14) { - ut32 sf = (ins >> 12) & 0x7; - ut32 xreg = (ins >> 9) & 0x7; + ut32 sf = (ins >> 12) & 0xF; + ut32 xreg = (ins >> 8) & 0xF; ut32 ddreg = (ins >> 4) & 0xF; ut32 sdreg = ins & 0xF; op->mnemonic = r_str_newf ("%s %s, %s = %s", - sf_names[sf], xop_shift[xreg], + sf_names[sf], reg0[xreg], reg0[ddreg], reg0[sdreg]); return true; } - /* Type 16: Conditional Shift (bits 23-16 = 00001110) */ + /* Type 16: Conditional Shift (bits 23-16 = 00001110) + SF=bits15-12 (4 bits), XREG=bits11-8 (reg0 index), + COND=bits3-0. */ if ((ins >> 16) == 0x0E) { ut32 sf = (ins >> 12) & 0xF; - ut32 xreg = (ins >> 8) & 0x7; + ut32 xreg = (ins >> 8) & 0xF; ut32 cond = ins & 0xF; if (cond == 15) op->mnemonic = r_str_newf ("SR = %s %s", - sf_names[sf], xop_shift[xreg]); + sf_names[sf], reg0[xreg]); else op->mnemonic = r_str_newf ("IF %s SR = %s %s", cond_str[cond], sf_names[sf], - xop_shift[xreg]); + reg0[xreg]); return true; } @@ -574,7 +578,7 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask) ut32 s_bit = (ins >> 14) & 1; ut32 g = (ins >> 13) & 1; ut32 cond = (ins >> 4) & 0xF; - ut32 ireg = ins & 0x3; + ut32 ireg = (ins >> 2) & 0x3; int base = g ? 4 : 0; if (cond == 15) op->mnemonic = r_str_newf ("%s (I%d)%s", @@ -624,39 +628,39 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask) return true; } - /* Type 26: Push/Pop/Cache (bits 23-16 = 00001000) */ - if ((ins >> 16) == 0x08) + /* Type 26: Push/Pop/Cache (bits 23-16 = 00000100) */ + if ((ins >> 16) == 0x04) { ut32 cf = (ins >> 7) & 1; - ut32 ppp = (ins >> 4) & 0x7; - ut32 lpp = (ins >> 2) & 0x3; + ut32 ppp = (ins >> 5) & 0x3; + ut32 lpp = (ins >> 3) & 0x3; ut32 spp = ins & 0x3; char buf[64]; int pos = 0; if (cf) pos += snprintf (buf + pos, sizeof (buf) - pos, "FLUSH CACHE"); - if (ppp == 1) + if (ppp == 2) pos += snprintf (buf + pos, sizeof (buf) - pos, "%sPUSH PC", pos ? ", " : ""); - else if (ppp == 2) + else if (ppp == 3) pos += snprintf (buf + pos, sizeof (buf) - pos, "%sPOP PC", pos ? ", " : ""); - if (lpp == 1) + if (lpp == 2) pos += snprintf (buf + pos, sizeof (buf) - pos, "%sPUSH LOOP", pos ? ", " : ""); - else if (lpp == 2) + else if (lpp == 3) pos += snprintf (buf + pos, sizeof (buf) - pos, "%sPOP LOOP", pos ? ", " : ""); - if (spp == 1) + if (spp == 2) pos += snprintf (buf + pos, sizeof (buf) - pos, "%sPUSH STS", pos ? ", " : ""); - else if (spp == 2) + else if (spp == 3) pos += snprintf (buf + pos, sizeof (buf) - pos, "%sPOP STS", pos ? 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