Fix Type 8 decode: correct all bitfield extractions

- DDREG: fixed to bits 7-4 (was bits 8-6, mixed XOP bit into dest)
- SDREG: fixed to bits 3-0 (was bits 5-0, included foreign bits)
- Dest/src registers now correctly use reg0[] table (was xop_alu[])
- NONE pattern: check full bits 7-0 == 0xAA (was only bits 5-0)
- XOP/YOP tables now follow AMF type (MAC vs ALU), not Z bit
- Output format: f(xop, yop), ddreg = sdreg (matches ADI syntax)
- Verified against assembler output for all three Type 8 variants:
  ALU+move, MAC+move, and NONE=ALU status-only
- Full regression: isa_test.bin, fir.bin, iir.bin all unchanged

examples/build/type8_test.dsp

@@ -0,0 +1,16 @@
+	.section/PM program0;
+	.global _start;
+_start:
+	/* Type 8: Compute + Dreg move */
+	/* AR = AX0 + AY0, MX0 = AX1 */
+	ar = ax0 + ay0, ax0 = mx0;
+
+	/* MR = MX0 * MY0 (SS), AX1 = AY0 */
+	mr = mx0 * my0 (ss), ax1 = ay0;
+
+	/* NONE = AX0 + AY0 (generate status only) */
+	none = ax0 + ay0;
+
+	nop;
+_halt:
+	jump _halt;