Fix Type 8 decode: correct all bitfield extractions

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- DDREG: fixed to bits 7-4 (was bits 8-6, mixed XOP bit into dest)
- SDREG: fixed to bits 3-0 (was bits 5-0, included foreign bits)
- Dest/src registers now correctly use reg0[] table (was xop_alu[])
- NONE pattern: check full bits 7-0 == 0xAA (was only bits 5-0)
- XOP/YOP tables now follow AMF type (MAC vs ALU), not Z bit
- Output format: f(xop, yop), ddreg = sdreg (matches ADI syntax)
- Verified against assembler output for all three Type 8 variants:
  ALU+move, MAC+move, and NONE=ALU status-only
- Full regression: isa_test.bin, fir.bin, iir.bin all unchanged

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This commit is contained in:

Dr. Christian Giessen

2026-04-22 19:50:07 +00:00

parent 6849a701d4

commit adfc7b34b4

3 changed files with 50 additions and 12 deletions

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r2plugin/asm_adsp219x.so

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