From d7f0569a47962d51ff0aae03eb15d8e935ab0638 Mon Sep 17 00:00:00 2001 From: Siggi Date: Sun, 12 Apr 2026 18:10:08 +0000 Subject: [PATCH] Add real ADSP-2191 assembly examples + open21xx assembler test --- .../adsp-2191_complex_rad2_fft/ADSP-2191.ldf | 115 ++ .../ADSP-2191_Complex_Rad2_FFT.txt | 188 +++ .../adsp-2191_complex_rad2_fft/Cfft2_2191.asm | 181 +++ .../adsp-2191_complex_rad2_fft/Cfft2_2191.dpj | Bin 0 -> 3164 bytes .../adsp-2191_complex_rad2_fft/inimag.dat | 1026 +++++++++++++++++ .../adsp-2191_complex_rad2_fft/inreal.dat | 1026 +++++++++++++++++ .../adsp-2191_complex_rad2_fft/twid_cos.dat | 512 ++++++++ .../adsp-2191_complex_rad2_fft/twid_sin.dat | 512 ++++++++ examples/adsp-2191_fir/ADSP-2191 FIR.dpj | Bin 0 -> 3131 bytes examples/adsp-2191_fir/ADSP-2191 FIR.txt | 101 ++ examples/adsp-2191_fir/ADSP-2191.ldf | 115 ++ examples/adsp-2191_fir/ADSP-2191_FIR.txt | 101 ++ examples/adsp-2191_fir/Coeff_l.dat | 31 + examples/adsp-2191_fir/Fir.asm | 81 ++ examples/adsp-2191_fir/Fir_test.asm | 76 ++ examples/adsp-2191_fir/input_dec.dat | 512 ++++++++ examples/adsp-2191_iir/ADSP-2191 IIR.dpj | Bin 0 -> 3131 bytes examples/adsp-2191_iir/ADSP-2191 IIR.txt | 115 ++ examples/adsp-2191_iir/ADSP-2191.ldf | 115 ++ examples/adsp-2191_iir/ADSP-2191_IIR.txt | 115 ++ examples/adsp-2191_iir/coef_hex.dat | 8 + examples/adsp-2191_iir/iir.asm | 97 ++ examples/adsp-2191_iir/iir_test.asm | 64 + examples/adsp-2191_iir/inreal_256.dat | 256 ++++ .../ADSP-2191 Viterbi Decoder.txt | 80 ++ .../ADSP-2191 Viterbi.dpj | Bin 0 -> 2610 bytes .../adsp-2191_viterbi_decoder/ADSP-2191.ldf | 115 ++ .../ADSP-2191_Viterbi_Decoder.txt | 80 ++ .../adsp-2191_viterbi_decoder/GSM_rec.dat | 378 ++++++ .../adsp-2191_viterbi_decoder/VITERBI.asm | 189 +++ examples/isa_test.bin | Bin 0 -> 144 bytes examples/isa_test.dsp | 94 ++ examples/isa_test.elf | Bin 0 -> 364 bytes examples/isa_test.o | Bin 0 -> 692 bytes 34 files changed, 6283 insertions(+) create mode 100644 examples/adsp-2191_complex_rad2_fft/ADSP-2191.ldf create mode 100644 examples/adsp-2191_complex_rad2_fft/ADSP-2191_Complex_Rad2_FFT.txt create mode 100644 examples/adsp-2191_complex_rad2_fft/Cfft2_2191.asm create mode 100644 examples/adsp-2191_complex_rad2_fft/Cfft2_2191.dpj create mode 100644 examples/adsp-2191_complex_rad2_fft/inimag.dat create mode 100644 examples/adsp-2191_complex_rad2_fft/inreal.dat create mode 100644 examples/adsp-2191_complex_rad2_fft/twid_cos.dat create mode 100644 examples/adsp-2191_complex_rad2_fft/twid_sin.dat create mode 100644 examples/adsp-2191_fir/ADSP-2191 FIR.dpj create mode 100644 examples/adsp-2191_fir/ADSP-2191 FIR.txt create mode 100644 examples/adsp-2191_fir/ADSP-2191.ldf create mode 100644 examples/adsp-2191_fir/ADSP-2191_FIR.txt create mode 100644 examples/adsp-2191_fir/Coeff_l.dat create mode 100644 examples/adsp-2191_fir/Fir.asm create mode 100644 examples/adsp-2191_fir/Fir_test.asm create mode 100644 examples/adsp-2191_fir/input_dec.dat create mode 100644 examples/adsp-2191_iir/ADSP-2191 IIR.dpj create mode 100644 examples/adsp-2191_iir/ADSP-2191 IIR.txt create mode 100644 examples/adsp-2191_iir/ADSP-2191.ldf create mode 100644 examples/adsp-2191_iir/ADSP-2191_IIR.txt create mode 100644 examples/adsp-2191_iir/coef_hex.dat create mode 100644 examples/adsp-2191_iir/iir.asm create mode 100644 examples/adsp-2191_iir/iir_test.asm create mode 100644 examples/adsp-2191_iir/inreal_256.dat create mode 100644 examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi Decoder.txt create mode 100644 examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi.dpj create mode 100644 examples/adsp-2191_viterbi_decoder/ADSP-2191.ldf create mode 100644 examples/adsp-2191_viterbi_decoder/ADSP-2191_Viterbi_Decoder.txt create mode 100644 examples/adsp-2191_viterbi_decoder/GSM_rec.dat create mode 100644 examples/adsp-2191_viterbi_decoder/VITERBI.asm create mode 100644 examples/isa_test.bin create mode 100644 examples/isa_test.dsp create mode 100644 examples/isa_test.elf create mode 100644 examples/isa_test.o diff --git a/examples/adsp-2191_complex_rad2_fft/ADSP-2191.ldf b/examples/adsp-2191_complex_rad2_fft/ADSP-2191.ldf new file mode 100644 index 0000000..16f7c52 --- /dev/null +++ b/examples/adsp-2191_complex_rad2_fft/ADSP-2191.ldf @@ -0,0 +1,115 @@ + +ARCHITECTURE(ADSP-2191) + +$OBJECTS = $COMMAND_LINE_OBJECTS; +// This memory map is set up to facilite testing of the tool +// chain -- code and data area are as large as possible. + +MEMORY +{ + seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) } + seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) } + seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) } + + seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x008fff) WIDTH(16) } + seg_buf1 { TYPE(DM RAM) START(0x009000) END(0x0095ff) WIDTH(16) } + seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) } + seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) } + seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) } + seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) } +} + +PROCESSOR p0 +{ + LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) + OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) + + SECTIONS + { + sec_dmy + { + INPUT_SECTIONS( $OBJECTS(IVreset)) + } > seg_dmy + + sec_itab + { + INPUT_SECTIONS( $OBJECTS(IVpwrdwn)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVkernel)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVstackint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVmailboxint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVtimerint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVringint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVpcibmint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVdspdspint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint13)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint14)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVac97frint)) + . = .+0x1; + } > seg_itab + seg_code + { + INPUT_SECTIONS( $OBJECTS(program) ) + } >seg_code + + sec_buf1 + { + INPUT_SECTIONS($OBJECTS(seg_buf1) ) + }>seg_buf1 + + sec_buf2 + { + INPUT_SECTIONS($OBJECTS(seg_buf2) ) + }>seg_buf2 + + sec_data1 + { + INPUT_SECTIONS( $OBJECTS(data1) ) + } >seg_data1 + + sec_data2 + { + INPUT_SECTIONS( $OBJECTS(data2) ) + INPUT_SECTIONS( $OBJECTS(program2) ) + } >seg_data2 + + + // support for initialization, including C++ + sec_ctor + { + INPUT_SECTIONS( $OBJECTS(ctor)) + } >seg_data1 + + // provide linker variables describing the stack (grows down) + // ldf_stack_limit is the lowest address in the stack + // ldf_stack_base is the highest address in the stack + sec_stack + { + ldf_stack_limit = .; + ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1; + } >seg_stack + sec_heap + { + .heap = .; + .heap_size = MEMORY_SIZEOF(seg_heap); + .heap_end = . + MEMORY_SIZEOF(seg_heap) - 1; + } >seg_heap + } +} diff --git a/examples/adsp-2191_complex_rad2_fft/ADSP-2191_Complex_Rad2_FFT.txt b/examples/adsp-2191_complex_rad2_fft/ADSP-2191_Complex_Rad2_FFT.txt new file mode 100644 index 0000000..cf36fe3 --- /dev/null +++ b/examples/adsp-2191_complex_rad2_fft/ADSP-2191_Complex_Rad2_FFT.txt @@ -0,0 +1,188 @@ +**************************************************************************** + +Cfft2_2191_Px.asm Example 2191 complex radix-2 FFT Program + +Analog Devices, Inc. +DSP Division +Three Technology Way +P.O. Box 9106 +Norwood, MA 02062 + +23-JUNE-2001 BJM + +This directory contains an example ADSP-2191 single-core subroutine +that implements radix-2 FFT of length 64 or greater on input data x(n). A +detailed discussion of the complex radix-2 FFT algorithm can be found in the +source header comments of "CFFT2_2191.ASM". + +Files contained in this directory: + +CFFT2_2191.ASM ADSP-2191 source for a complex radix-2 FFT example. +ADSP-2191.LDF Linker description file for the CFFT2_2191.ASM example +CFFT2_2191.DPJ The VisualDSP project file for the complex radix-2 FFT. +INPUTREAL.DAT Real part of complex input data +INPUTIMAG.DAT Imaginary part of complex input data +TWID_SIN.DAT Sin array FFT twiddle factors +TWID_COS.DAT Cos array FFT twiddle factors + + _________________________________________________________________ + +CONTENTS + +I. FUNCTION/ALGORITHM DESCRIPTION +II. IMPLEMENTATION DESCRIPTION +III. DESCRIPTION OF INPUT DATA + 1. Input Samples + 2. Twiddle factors + +_______________________________________________________________ + +I. FUNCTION/ALGORITHM DESCRIPTION + +The program CFFT2_2191.ASM is an implementation of a complex input radix-2 DIT +FFT. + +This radix-2 FFT routine will take data lengths that are any power of two (>= 64 +points). + + +II. IMPLEMENTATION DESCRIPTION + +This FFT implementation takes advantage of the architecture of the +ADSP-2191. + +The following table of variables and their location is presented, where "N" is +the length of the FFT: + + Input Output +Routine DM PM DM PM +------------------------------------------------------------------------------- +CFFT2_2191: + inputreal[N] refft[N] inputreal[N] + inputimag[N] + twid_imag[N/2] + twid_real[N/2] +-------------------------------------------------------------------------------- + + + + inputreal[N] Real part of normal-ordered complex input stored in DM + inputimag[N] Imaginary part of normal-ordered complex input stored in PM + refft[N] Real part of frequency domain data (fft output) stored in DM + twid_imag[N] Sin table stored in DM + twid_real[N] Cos table stored in DM + + + +III. DESCRIPTION OF INPUT DATA + +1. INPUT SAMPLES: +----------------- + +This FFT routine expects input data which conforms to the following criteria: + +Gather input data such that an array of complex fixed point values are +arranged in the following order: + +inputreal[N]: + real(0) + real(1) + real(2) + etc... + +inputimag[N]: + imag(0) + imag(1) + imag(2) + etc... + + +2. TWIDDLE FACTOR DATA: +----------------------- + +This FFT routine expects N/2 fixed point values of one half period of a +sine waveform and N/2 fixed point values of a one half period of a cosine +waveform to be used as twiddle factors. These twiddles should be in +a bit-reversed order. + +Generate twiddle data such that an array of twiddle factor values are +arranged in the following order: + + cos(0) + cos(1) + cos(2) + ... + ... + ... + cos(N/2) + + sin(0) + sin(1) + sin(2) + ... + ... + ... + sin(N/2) + +Then, bit reverse these sin and cosine twiddle arrays. This can be done by +writing a small bit reversal program which utilizes the bit reversed +addressing mode of DAG1 of the ADSP-2191. + +The bit reversed array of twiddle factor values are arranged in the following +order: + +twid_real[N]: + + cos(0) + cos(N/4) + cos(N/8) + ... + ... + ... + cos(N/2) + +twid_imag[N]: + + sin(0 + sin(N/4) + sin(N/8) + ... + ... + ... + sin(N/2) + + + +2191 - Complex Radix-2 FFT (Cfft2_2191.asm) + +In order to perform FFTs of different lengths, the following code changes are +necessary: +(The rules/relations described in the source code must be followed!) + + - Modify N to reflect the length of the FFT to be performed (N must be a power of 2) + - Modify log2n such that STAGES = (log2(N)) + - Mofify Mod_Value such that Mod_Value = ( 2^(16-LOG2N) ) + - Modifiy Refft_Bitrev and Inputreal_Bitrev to represent the bit reversed + address of the output real and imaginary buffers + +Cfft2_2191.asm code excerpt shown below: + +/**********The constants below must be changed for different length FFTs******* + +N = number of points in the FFT, must be a power of 2 +log2N = log2(N) +Mod_Value = 2^(16-LOG2N) +Refft_Bitrev = bitrev addr of output real in dm +Inputreal_Bitrev = bitrev addr of output imag in dm + +******************************************************************************/ + +/* Set Constants for N-point FFT */ +#define N 1024 +#define Ndiv2 (N/2) +#define log2N 10 +#define Mod_Value 64 +#define Refft_Bitrev 0x0001 +#define Inputreal_Bitrev 0x0009 + + diff --git a/examples/adsp-2191_complex_rad2_fft/Cfft2_2191.asm b/examples/adsp-2191_complex_rad2_fft/Cfft2_2191.asm new file mode 100644 index 0000000..378a554 --- /dev/null +++ b/examples/adsp-2191_complex_rad2_fft/Cfft2_2191.asm @@ -0,0 +1,181 @@ +/****************************************************************************** +Cfft2_2191.ASM ADSP-2191 Radix-2 DIT Complex FFT + +Performs a radix-2 DIT FFT of length 64 or greater on input data x(n). + + N Real part of normal-ordered complex input stored in DM + N Imaginary part of normal-ordered complex input stored in PM + N Real part of fft stored in DM + N/2 Sin table stored in DM + N/2 Cos table stored in PM + +Calling Information: + pm(twid_real[N/2]) - sin(2pi*n/N) table in bitreversed order + dm(twid_imag[N/2]) - cos(2pi*n/N) table in bitreversed order + + dm(Inputreal[N]) - Real part of complex input array stored in dm + pm(Inputimag[N]) - Imaginary part of complex input array stored in pm + +Results: + dm(Refft[N]) - Real FFT results ordered sequentially + dm(Inputreal[N]) - Imaginary FFT results ordered sequentially + +Benchmarks: + FFT Length cycles time (us) 160MHz + ---------- ------------- --------------- + 1024 24160 151 + +Memory Usage: + PM code(24-bit) = 92 words + PM data(24-bit) = N + 2 + N/2 words + DM data(16-bit) = 2N + 4 + N + 1 words + +******************************************************************************/ + +/**********The constants below must be changed for different length FFTs******* + +N = number of points in the FFT, must be a power of 2 +log2N = log2(N) +Mod_Value = 2^(16-LOG2N) +Refft_Bitrev = bitrev addr of output real in dm +Inputreal_Bitrev = bitrev addr of output imag in dm + +******************************************************************************/ + +/* Set Constants for N-point FFT */ +#define N 1024 +#define Ndiv2 (N/2) +#define log2N 10 +#define Mod_Value 64 +#define Refft_Bitrev 0x0001 +#define Inputreal_Bitrev 0x0009 + + +/* DM data */ +.section/data data1; +.VAR twid_imag [Ndiv2] = "twid_sin.dat"; +.VAR groups = 1; +.VAR node_space = Ndiv2; + +/* DM data */ +.section/data seg_buf1; +.VAR Inputreal [N+2] = "inreal.dat"; + +/* DM data */ +.section/data seg_buf2; +.VAR Refft[N+2]; + +/* PM data */ +.section/pm data2; +.VAR/init24 twid_real [Ndiv2] = "twid_cos.dat"; +.VAR Inputimag [N+2] = "inimag.dat"; + +/* PM interrupt vector code */ +.section/pm IVreset; + JUMP start; NOP; NOP; + + +/* Program Code */ +.section/pm program; +start: + dmpg2 = page(twid_real); /* Initialize page for PM data */ + M0 = 0; + L0 = length(twid_imag); /* Initialize twid_imag circular buffer */ + AX1 = twid_imag; + REG(b0) = AX1; /* Initialize pointer to twid_imag */ + M1 = 1; + L1 = 0; /* Initialize for modulo addressing */ + M4 = 0; + L4 = length(twid_real); /* Initialize twid_real circular buffer */ + AX1 = twid_real; + REG(b4) = AX1; /* Initialize pointer to twid_real */ + M5 = 1; + L5 = 0; /* Initialize for modulo addressing */ + M6 = -1; + L6 = 0; /* Initialize for modulo addressing */ + L2 = 0; + L3 = 0; + L7 = 0; + + CNTR = log2N -1; /* Initialize Stage Counter */ + DO stage_loop UNTIL CE; /* Compute all stages in FFT */ + I0 = twid_imag; /* I0 --> (-S) of W0 */ + I1 = Inputreal; /* I1 --> x1 in 1st group of stage */ + I2 = Inputreal; /* I2 --> x0 in 1st group of stage */ + I4 = twid_real; /* I4 --> C of W0 */ + I5 = Inputimag; /* I5 --> y1 in 1st group of stage */ + I6 = Inputimag; /* I6 --> y0 in 1st group of stage */ + SI = DM(groups); + CNTR = SI; /* CNTR = # of groups in stage */ + SR = LSHIFT SI BY 1(LO); + DM(groups) = SR0; + SI = DM(node_space); /* SI = node_space modifier */ + M2 =SI; + M7 =SI; + MODIFY(I1,M2); /* I1 --> x1 in 1st group of stage */ + MODIFY(I5,M7); /* I5 --> y1 in 1st group of stage */ + DO group_loop UNTIL CE; + MY0 = PM(I4,M5), MX0 = DM(I1,M0); /* MY0=C, MX0=x1 */ + MR = MX0*MY0(SS), MX1 = PM(I5,M4); /* MR=C*x1,MX1=y1 */ + MY1 = DM(I0,M1); /* MY1 = (-S) */ + CNTR = SI; /* CNTR = butterfly counter */ + DO bfly_loop UNTIL CE; + MR = MR-MX1*MY1(RND), AY0 = DM(I2,M0); /* MR=x1*C-y1*-S, AY0=x0 */ + AR = MR1+AY0, AX1 = PM(I5,M5); /* AR=x0'=x0+(x1*C-y1*-S) */ + DM(I2,M1) = AR, AR = AY0-MR1; /* DM=x0', AR=x1'=x0-(x1*C-y1*(-S)) */ + MR = MX0*MY1(SS), DM(I1,M1) = AR; /* MR=x1*(-S), DM=x1' */ + MR = MR+MX1*MY0(RND), AY1 = PM(I6,M4), MX0 = DM(I1,M0); /*MR=x1*(-S)+y1*C, AY1=y0, MX0=next x1*/ + AR = MR1+AY1, MX1 = PM(I5,M6); /* AR=y0'=y0+(y1*C+x1*(-S)), MX1= next y1 */ + PM(I6,M5) = AR, AR = AY1-MR1; /* PM=y0', AR=y1'=y0-(y1*C+x1*(-S)) */ +bfly_loop: + MR = MX0*MY0(SS), PM(I5,M5) = AR; /* PM=y1' */ + MY0 = PM(I5,M7), MX0 = DM(I1,M2); +group_loop: + MY0=PM(I6,M7), MX0=DM(I2,M2); + SR=ASHIFT SI BY -1 (LO); +stage_loop: + DM(node_space)=SR0; + + I0 = twid_imag; /* I0 --> (-S) */ + I1 = Inputreal; /* I1 --> x1 */ + I2 = Inputreal; /* I2 --> x0 */ + M2 = 2; + I3 = Refft_Bitrev; /* Refft bitreversed */ + M3 = Mod_Value; /* Bitreversed modifier */ + I4 = twid_real; /* I4 --> C */ + I5 = Inputimag; /* I5 --> y1 */ + I6 = Inputimag; /* I6 --> y0 */ + M6 = 2; + MODIFY(I1,M1); /* I1 -->x1 */ + MODIFY(I5,M5); /* I5 -->y1 */ + MY0 = PM(I4,M5), MX0 = DM(I1,M2); /* MY0=C, MX0=x1 */ + MR = MX0*MY0(SS), MX1 = PM(I5,M6); /* MR = C*x1, MX1 = y1 */ + MY1 = DM(I0,M1); /* MY1 = (-S) */ + CNTR = Ndiv2; + DO last_loop UNTIL CE; + MR = MR-MX1*MY1(RND), AY0 = DM(I2,M2); /* MR=x1*C-y1*(-S), AY0=x0 */ + AR = MR1+AY0, AY1 = PM(I6,M4); /* AR=x0'=x0+(x1*C-y1*(-S)), AY1=y0 */ + ENA BIT_REV; + DM(I3,M3) = AR, AR = AY0-MR1; /* Read real data */ + MR = MX0*MY1(SS), DM(I3,M3) = AR; /* Place in sequential order(using bit-reversal) */ + DIS BIT_REV; + MR = MR+MX1*MY0(RND), MY0 = PM(I4,M5), MX0 = DM(I1,M2); + AR = MR1+AY1, MX1 = PM(I5,M6); /* AR=y0'=y0+(y1*C+x1*(-S)), MX1= next y1 */ + PM(I6,M5) = AR, AR = AY1-MR1; /* PM=y0', AR=y1'=y0-(y1*C+x1*(-S)) */ + MY1 = DM(I0,M1); /* MY1 = (-S) */ +last_loop: + MR = MX0*MY0(SS), PM(I6,M5) = AR; /*PM=y1' */ + + I3 = Inputreal_Bitrev; + M3 = Mod_Value; /* Bitreversed modifier */ + I5 = Inputimag; + ENA BIT_REV; + CNTR = N; + DO bit_rev_imag UNTIL CE; + AX0 = PM(I5,M5); /* Read imaginary data */ +bit_rev_imag: DM(I3,M3) = AX0; /* Place in sequential order */ + DIS BIT_REV; + +looping: JUMP looping; + + diff --git a/examples/adsp-2191_complex_rad2_fft/Cfft2_2191.dpj b/examples/adsp-2191_complex_rad2_fft/Cfft2_2191.dpj new file mode 100644 index 0000000000000000000000000000000000000000..ee8b350bcd1e9d2874c55531e1a1fb35853f6747 GIT binary patch literal 3164 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finite impulse response filter (FIR) + +Analog Devices, Inc. +DSP Division +Three Technology Way +P.O. Box 9106 +Norwood, MA 02062 + +23-JUNE-2001 BJM + +This directory contains an example ADSP-2191, single-core subroutine +that implements a N-tap finite impulse response filter (FIR) using coefficients. + +Files contained in this directory: + +fir.dpj VisualDSP project file +fir.asm ADSP-2191 source for FIR +fir_test.asm Calling function for fic.asm +ADSP-2191.ldf Linker description file +input_dec.dat Sample data for FIR + _________________________________________________________________ + +CONTENTS + +I. FUNCTION/ALGORITHM DESCRIPTION +II. IMPLEMENTATION DESCRIPTION +III. DESCRIPTION OF INPUT DATA + +I. FUNCTION/ALGORITHM DESCRIPTION + +The project fir.dpj contains an implementation of a single-core subroutine +that implements a N-tap finite impulse response filter (FIR). This +routine has been optimized to take advantage of the repetitive multiply +accumulates inherent to the algorithm. + +y(n) = Summation from k=0 to M of h(k)*x(n-k) + + +II. IMPLEMENTATION DESCRIPTION + +The assembly language module FIR_TEST.ASM initializes the input and +coefficient buffers and then calls FIR.ASM. + +The first buffer declared, IN, is Num_Samp locations long. + +The next buffer declared, OUT, is also Num_Samp long, and stores the +output of the filter. + +Delay_Line is the third buffer declared. This buffer holds the delay line. +Since there are past intermediate values for each stage of the FIR, the length of +this buffer is as long as the number of Taps. + +The coefficient buffer, COEFF, contains the FIR filter coefficients. The +coefficients are typically generated by a filter design software package. + +The linker descriptive file is ADSP-2191.LDF, which describes the hardware in +terms of memory spaces and peripherals. + +Because there is no data dependency between DSP cores, it is possible +to do perform an FIR in DSP core 1, while also performing an FIR in DSP core 2 +on separate input data, using different coefficients. + +III. DESCRIPTION OF INPUT DATA + +1. INPUT SAMPLES: +----------------- +This FIR routine expects input data which conforms to the following criteria: + +Generate input data such that an array of input fixed point values are arranged +in the following order: + +INPUT DATA + +indata(0) +indata(1) +indata(2) +indata(3) +... +... +... + + + +2. COEFFICIENT DATA: +----------------------- +This FIR routine expects TAPS 1.15 fixed point values to be used as coefficients. + +COEFFICIENT DATA + +coef(0) +coef(1) +coef(2) +coef(3) +... +... +... + + + diff --git a/examples/adsp-2191_fir/ADSP-2191.ldf b/examples/adsp-2191_fir/ADSP-2191.ldf new file mode 100644 index 0000000..c83a0cd --- /dev/null +++ b/examples/adsp-2191_fir/ADSP-2191.ldf @@ -0,0 +1,115 @@ + +ARCHITECTURE(ADSP-2191) + +$OBJECTS = $COMMAND_LINE_OBJECTS; +// This memory map is set up to facilite testing of the tool +// chain -- code and data area are as large as possible. + +MEMORY +{ + seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) } + seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) } + seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) } + + seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x0088ff) WIDTH(16) } + seg_buf1 { TYPE(DM RAM) START(0x008900) END(0x0095ff) WIDTH(16) } + seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) } + seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) } + seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) } + seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) } +} + +PROCESSOR p0 +{ + LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) + OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) + + SECTIONS + { + sec_dmy + { + INPUT_SECTIONS( $OBJECTS(IVreset)) + } > seg_dmy + + sec_itab + { + INPUT_SECTIONS( $OBJECTS(IVpwrdwn)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVkernel)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVstackint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVmailboxint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVtimerint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVringint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVpcibmint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVdspdspint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint13)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint14)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVac97frint)) + . = .+0x1; + } > seg_itab + seg_code + { + INPUT_SECTIONS( $OBJECTS(program) ) + } >seg_code + + sec_buf1 + { + INPUT_SECTIONS($OBJECTS(seg_buf1) ) + }>seg_buf1 + + sec_buf2 + { + INPUT_SECTIONS($OBJECTS(seg_buf2) ) + }>seg_buf2 + + sec_data1 + { + INPUT_SECTIONS( $OBJECTS(data1) ) + } >seg_data1 + + sec_data2 + { + INPUT_SECTIONS( $OBJECTS(data2) ) + INPUT_SECTIONS( $OBJECTS(program2) ) + } >seg_data2 + + + // support for initialization, including C++ + sec_ctor + { + INPUT_SECTIONS( $OBJECTS(ctor)) + } >seg_data1 + + // provide linker variables describing the stack (grows down) + // ldf_stack_limit is the lowest address in the stack + // ldf_stack_base is the highest address in the stack + sec_stack + { + ldf_stack_limit = .; + ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1; + } >seg_stack + sec_heap + { + .heap = .; + .heap_size = MEMORY_SIZEOF(seg_heap); + .heap_end = . + MEMORY_SIZEOF(seg_heap) - 1; + } >seg_heap + } +} diff --git a/examples/adsp-2191_fir/ADSP-2191_FIR.txt b/examples/adsp-2191_fir/ADSP-2191_FIR.txt new file mode 100644 index 0000000..7400ae9 --- /dev/null +++ b/examples/adsp-2191_fir/ADSP-2191_FIR.txt @@ -0,0 +1,101 @@ +**************************************************************************** + +fir.asm N-tap finite impulse response filter (FIR) + +Analog Devices, Inc. +DSP Division +Three Technology Way +P.O. Box 9106 +Norwood, MA 02062 + +23-JUNE-2001 BJM + +This directory contains an example ADSP-2191, single-core subroutine +that implements a N-tap finite impulse response filter (FIR) using coefficients. + +Files contained in this directory: + +fir.dpj VisualDSP project file +fir.asm ADSP-2191 source for FIR +fir_test.asm Calling function for fic.asm +ADSP-2191.ldf Linker description file +input_dec.dat Sample data for FIR + _________________________________________________________________ + +CONTENTS + +I. FUNCTION/ALGORITHM DESCRIPTION +II. IMPLEMENTATION DESCRIPTION +III. DESCRIPTION OF INPUT DATA + +I. FUNCTION/ALGORITHM DESCRIPTION + +The project fir.dpj contains an implementation of a single-core subroutine +that implements a N-tap finite impulse response filter (FIR). This +routine has been optimized to take advantage of the repetitive multiply +accumulates inherent to the algorithm. + +y(n) = Summation from k=0 to M of h(k)*x(n-k) + + +II. IMPLEMENTATION DESCRIPTION + +The assembly language module FIR_TEST.ASM initializes the input and +coefficient buffers and then calls FIR.ASM. + +The first buffer declared, IN, is Num_Samp locations long. + +The next buffer declared, OUT, is also Num_Samp long, and stores the +output of the filter. + +Delay_Line is the third buffer declared. This buffer holds the delay line. +Since there are past intermediate values for each stage of the FIR, the length of +this buffer is as long as the number of Taps. + +The coefficient buffer, COEFF, contains the FIR filter coefficients. The +coefficients are typically generated by a filter design software package. + +The linker descriptive file is ADSP-2191.LDF, which describes the hardware in +terms of memory spaces and peripherals. + +Because there is no data dependency between DSP cores, it is possible +to do perform an FIR in DSP core 1, while also performing an FIR in DSP core 2 +on separate input data, using different coefficients. + +III. DESCRIPTION OF INPUT DATA + +1. INPUT SAMPLES: +----------------- +This FIR routine expects input data which conforms to the following criteria: + +Generate input data such that an array of input fixed point values are arranged +in the following order: + +INPUT DATA + +indata(0) +indata(1) +indata(2) +indata(3) +... +... +... + + + +2. COEFFICIENT DATA: +----------------------- +This FIR routine expects TAPS 1.15 fixed point values to be used as coefficients. + +COEFFICIENT DATA + +coef(0) +coef(1) +coef(2) +coef(3) +... +... +... + + + diff --git a/examples/adsp-2191_fir/Coeff_l.dat b/examples/adsp-2191_fir/Coeff_l.dat new file mode 100644 index 0000000..d9f50bd --- /dev/null +++ b/examples/adsp-2191_fir/Coeff_l.dat @@ -0,0 +1,31 @@ +86, +115, +-77, +-103, +24, +187, +18, +-248, +-132, +319, +327, +-374, +-744, +412, +2564, +3671, +2564, +412, +-744, +-374, +327, +319, +-132, +-248, +18, +187, +24, +-103, +-77, +115, +86 diff --git a/examples/adsp-2191_fir/Fir.asm b/examples/adsp-2191_fir/Fir.asm new file mode 100644 index 0000000..fe99e3b --- /dev/null +++ b/examples/adsp-2191_fir/Fir.asm @@ -0,0 +1,81 @@ +/************************************************************** + +File Name: FIR.asm + +Date Modified: 6/22/01 BM + + +Description: + Subroutine that implements a FIR Filter given + coefficients and samples. + + Equation: y(n) = Summation from k=0 to M of h(k)*x(n-k) + +Calling Parameters: + b0,i0 = address of delay line buffer + l0 = length of delay line buffer + b1,i1 = address of input samples buffer + b4,i4 = address of coefficients buffer + l4 = length of coefficients buffer + b2,i2 = address of output buffer + m1 = 1 + m3 = -1 + m4 = 1 + +Assumptions: + + Delay line must be of length TAPS + Delay line , Output and Input buffers stored in DM Block. + Instructions, and Coefficients stored in PM Block. + +Return Values: + i2 = output buffer + i0 = delay line pointer + +Registers Affected: + i0,i1,i2,i4,MX,MY,MR,SR + +Cycle Count: + 7 + Bin_Samp(Taps-1 + 4) + cache misses + +Memory Usage: + Instructions Words (24-bits): + 11 + Taps-1 instruction words + + Data Words (16 or 24-bits): + Number of taps locations for coefficients (24-bits) + Number of taps locations for the delay line buffer (16-bits) + Number of samples locations for the input buffer (16-bits) + Number of samples locations for the output buffer (16-bits) + +Notes: + +**************************************************************/ +#define Samps_per_Bin 40 /* Number of Input samples in each bin */ +#define Taps 31 /* Number of filter taps */ + +.GLOBAL fir; + +/* program memory code */ +.section/pm program; + +fir: + MR = 0, MX0 = DM(I1,M1), MY0 = PM(I4,m4); /* Read Input sample and coefficient */ + DM(I0,M3) = MX0; /* Put Input sample in delay line */ + + CNTR=Samps_per_Bin; /* Set CNTR to Samps_per_Bin for each bin */ + DO mult_acc UNTIL CE; + .repeat (Taps-1); + MR=MR+MX0*MY0(SS), MX0=DM(I0,M3), MY0=PM(I4,M4); + .end_repeat; + MR=MR+MX0*MY0(SS), MX0=DM(I0,M1), MY0=PM(I4,M4); + SR=ASHIFT MR2 (HI), MX0=DM(I1,M1); + SR=SR OR LSHIFT MR1 (LO), DM(I0,M3) = MX0; +mult_acc: + MR = 0, DM(I2,M1)=SR0; /* Write to output */ + rts (db); + MX0 = DM(I0,M1); /* Update delay pointer */ + MX0 = DM(I1,M3); + + + diff --git a/examples/adsp-2191_fir/Fir_test.asm b/examples/adsp-2191_fir/Fir_test.asm new file mode 100644 index 0000000..e56811d --- /dev/null +++ b/examples/adsp-2191_fir/Fir_test.asm @@ -0,0 +1,76 @@ +/************************************************************************ +File Name: Fir_test.asm + +Date Modified: 6/22/01 BM + + +Purpose: Demonstrate initialization and operation of + FIR.asm on the ADSP-2192. FIR.asm is a + single precision direct form FIR filter. All + coefficients and data values are assumed to + be in 1.15 format. + +************************************************************************/ + +#define Num_Samp 512 /* NUmber of Input samples */ +#define Taps 31 /* Number of filter taps */ +#define Shift 2 /* Number of shifts */ +#define Samps_per_Bin 40 /* Number of Input samples in each bin */ +#define Num_Bins (Num_Samp/Samps_per_Bin) /* Number of bins */ + +.EXTERN fir; + +/* DM data */ +.section/data data1; +.VAR IN[Num_Samp] = "input_dec.dat"; /* Input buffer */ +.VAR OUT[Num_Samp]; /* Output buffer */ +.VAR Delay_Line[Taps]; /* Delay line */ + + +/* PM data */ +.section/pm data2; +.VAR COEFF[Taps] = "coeff_l.dat"; + +/* PM interrupt vector code */ +.section/pm IVreset; + JUMP start; NOP; NOP; NOP; + +/* Program memory code */ +.section/pm program; +start: + I0=Delay_Line; /* Initialize delay line pointer */ + M1 = 1; + I1 = IN; /* Initialize Input pointer */ + I2 = OUT; /* Initialize Output pointer */ + L1=0; /* Initialize for modulo addressing */ + L2=0; /* Initialize for modulo addressing */ + M3=-1; + M4=1; + SE = Shift; + DMPG2=page(COEFF); + + L0=LENGTH (Delay_Line); /* Initialize delay line circular buffer */ + ax0 = Delay_Line; + REG(b0) = ax0; /* Initialize pointer to delay line */ + + L4=length(COEFF); /* Initialize coeficient circular buffer */ + ax0 = COEFF; + reg(b4) = ax0; /* Initialize pointer to coeficient */ + + CNTR=Taps; /* 'Taps' location delay line */ + DO zero UNTIL CE; +zero: dm(I0,M1)=L0; /* Delay_line = 0 */ + + + CNTR = Num_Bins; /* Num_Bins to process Num_Samp */ + do per_bin until CE; + call fir (db); + I4=COEFF; /* Load Coeff buffer pointer */ + nop; +per_bin: + nop; + +looping: JUMP looping; /* Loop upon itself */ + +/************************************************************************/ + diff --git a/examples/adsp-2191_fir/input_dec.dat b/examples/adsp-2191_fir/input_dec.dat new file mode 100644 index 0000000..d88e8e6 --- /dev/null +++ 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response filter (IIR) + +Analog Devices, Inc. +DSP Division +Three Technology Way +P.O. Box 9106 +Norwood, MA 02062 + +23-JUNE-2001 BJM + +This directory contains an example ADSP-2191, single-core Infinite +Impulse Response (IIR) filter. +The IIR code uses coefficients, in an ordered array and applies them to +the filter. A detailed discussion of the IIR algorithm can be found +in the source header comments of "IIR.ASM". + +Files contained in this directory: + +iir.asm ADSP-2191 source for an example IIR filter +iir_test.asm ADSP-2191 source to call iir.asm +adsp-2191.ldf Linker description file for the IIR example +iir.dpj The VDSP project file for the IIR example. +inreal_256.dat Input data for IIR example in 1.15 format. +coefs_hex.dat Coefficients for IIR example in 1.15 format. + _________________________________________________________________ + +CONTENTS + +I. FUNCTION/ALGORITHM DESCRIPTION +II. IMPLEMENTATION DESCRIPTION +III. DESCRIPTION OF INPUT DATA + +I. FUNCTION/ALGORITHM DESCRIPTION + +The IIR filter code executes a canonical form (also called direct form II) +realization structure. The equation of the canonical form is + + w(n)=x(n) + b1*w(n-1) + b2*w(n-2) + y(n)=w(n) + a1*w(n-1) + a2*w(n-2) + +The input sample is x(n) and the output is y(n). The term w(n) is the +intermediate value; w(n-1) is the previous value and w(n-2) the one before +that. The variables a and b are the coefficients for the filter. + +This example of canonical equation uses a variant that limits the summation +in the canonical form to two. This type of IIR is called a biquad and is a +second order filter. Higher order filters can be achieved by cascading several +sections of biquads together. + + +II. IMPLEMENTATION DESCRIPTION + +The assembly language module IIR_TEST.ASM initializes the input and +coefficient buffers and then calls IIR.ASM. + +The first buffer declared, INBUF, is N_samp sample locations long. + +The next buffer declared, OUTBUF, is also N_samp samples long, and stores the +output of the filter. + +DLINE is the third buffer declared. This buffer holds the delay line for each +biquad. That is w(n-1) and w(n-2) for each biquad section of the filter. Since +there are two past intermediate vales for each stage of the biquad, the length of +this buffer is twice as long as the stages. + +The coefficient buffer, COEFS, contains the IIR filter coefficients. The +coefficients are typically generated by a filter +design software package. + +The linker descriptive file is ADSP-2191.LDF, which describes the hardware in +terms of memory spaces and peripherals. + +Because there is no data dependency between DSP cores, it is possible +to do perform an IIR in DSP core 1, while also performing an IIR in DSP core 2 +on separate input data, using different coefficients. + + +III. DESCRIPTION OF INPUT DATA + +1. INPUT SAMPLES: +----------------- +This IIR routine expects input data which conforms to the following criteria: + +Generate input data such that an array of input fixed point values are +in 1.15 format, with the data being arranged in the following order: + +INPUT DATA + +indata(0) +indata(1) +indata(2) +indata(3) +etc... + + +2. COEFFICIENT DATA: +----------------------- +This IIR routine expects [Biquad_secs*4] fixed point values to be used as coefficients. + + +COEFFICIENT DATA + +A2(0) +A1(0) +B2(0) +B1(0) +... +... +... + + + + diff --git a/examples/adsp-2191_iir/ADSP-2191.ldf b/examples/adsp-2191_iir/ADSP-2191.ldf new file mode 100644 index 0000000..c83a0cd --- /dev/null +++ b/examples/adsp-2191_iir/ADSP-2191.ldf @@ -0,0 +1,115 @@ + +ARCHITECTURE(ADSP-2191) + +$OBJECTS = $COMMAND_LINE_OBJECTS; +// This memory map is set up to facilite testing of the tool +// chain -- code and data area are as large as possible. + +MEMORY +{ + seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) } + seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) } + seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) } + + seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x0088ff) WIDTH(16) } + seg_buf1 { TYPE(DM RAM) START(0x008900) END(0x0095ff) WIDTH(16) } + seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) } + seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) } + seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) } + seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) } +} + +PROCESSOR p0 +{ + LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) + OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) + + SECTIONS + { + sec_dmy + { + INPUT_SECTIONS( $OBJECTS(IVreset)) + } > seg_dmy + + sec_itab + { + INPUT_SECTIONS( $OBJECTS(IVpwrdwn)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVkernel)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVstackint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVmailboxint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVtimerint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVringint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVpcibmint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVdspdspint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint13)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint14)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVac97frint)) + . = .+0x1; + } > seg_itab + seg_code + { + INPUT_SECTIONS( $OBJECTS(program) ) + } >seg_code + + sec_buf1 + { + INPUT_SECTIONS($OBJECTS(seg_buf1) ) + }>seg_buf1 + + sec_buf2 + { + INPUT_SECTIONS($OBJECTS(seg_buf2) ) + }>seg_buf2 + + sec_data1 + { + INPUT_SECTIONS( $OBJECTS(data1) ) + } >seg_data1 + + sec_data2 + { + INPUT_SECTIONS( $OBJECTS(data2) ) + INPUT_SECTIONS( $OBJECTS(program2) ) + } >seg_data2 + + + // support for initialization, including C++ + sec_ctor + { + INPUT_SECTIONS( $OBJECTS(ctor)) + } >seg_data1 + + // provide linker variables describing the stack (grows down) + // ldf_stack_limit is the lowest address in the stack + // ldf_stack_base is the highest address in the stack + sec_stack + { + ldf_stack_limit = .; + ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1; + } >seg_stack + sec_heap + { + .heap = .; + .heap_size = MEMORY_SIZEOF(seg_heap); + .heap_end = . + MEMORY_SIZEOF(seg_heap) - 1; + } >seg_heap + } +} diff --git a/examples/adsp-2191_iir/ADSP-2191_IIR.txt b/examples/adsp-2191_iir/ADSP-2191_IIR.txt new file mode 100644 index 0000000..047f70f --- /dev/null +++ b/examples/adsp-2191_iir/ADSP-2191_IIR.txt @@ -0,0 +1,115 @@ +**************************************************************************** + +IIR.asm Infinite impulse response filter (IIR) + +Analog Devices, Inc. +DSP Division +Three Technology Way +P.O. Box 9106 +Norwood, MA 02062 + +23-JUNE-2001 BJM + +This directory contains an example ADSP-2191, single-core Infinite +Impulse Response (IIR) filter. +The IIR code uses coefficients, in an ordered array and applies them to +the filter. A detailed discussion of the IIR algorithm can be found +in the source header comments of "IIR.ASM". + +Files contained in this directory: + +iir.asm ADSP-2191 source for an example IIR filter +iir_test.asm ADSP-2191 source to call iir.asm +adsp-2191.ldf Linker description file for the IIR example +iir.dpj The VDSP project file for the IIR example. +inreal_256.dat Input data for IIR example in 1.15 format. +coefs_hex.dat Coefficients for IIR example in 1.15 format. + _________________________________________________________________ + +CONTENTS + +I. FUNCTION/ALGORITHM DESCRIPTION +II. IMPLEMENTATION DESCRIPTION +III. DESCRIPTION OF INPUT DATA + +I. FUNCTION/ALGORITHM DESCRIPTION + +The IIR filter code executes a canonical form (also called direct form II) +realization structure. The equation of the canonical form is + + w(n)=x(n) + b1*w(n-1) + b2*w(n-2) + y(n)=w(n) + a1*w(n-1) + a2*w(n-2) + +The input sample is x(n) and the output is y(n). The term w(n) is the +intermediate value; w(n-1) is the previous value and w(n-2) the one before +that. The variables a and b are the coefficients for the filter. + +This example of canonical equation uses a variant that limits the summation +in the canonical form to two. This type of IIR is called a biquad and is a +second order filter. Higher order filters can be achieved by cascading several +sections of biquads together. + + +II. IMPLEMENTATION DESCRIPTION + +The assembly language module IIR_TEST.ASM initializes the input and +coefficient buffers and then calls IIR.ASM. + +The first buffer declared, INBUF, is N_samp sample locations long. + +The next buffer declared, OUTBUF, is also N_samp samples long, and stores the +output of the filter. + +DLINE is the third buffer declared. This buffer holds the delay line for each +biquad. That is w(n-1) and w(n-2) for each biquad section of the filter. Since +there are two past intermediate vales for each stage of the biquad, the length of +this buffer is twice as long as the stages. + +The coefficient buffer, COEFS, contains the IIR filter coefficients. The +coefficients are typically generated by a filter +design software package. + +The linker descriptive file is ADSP-2191.LDF, which describes the hardware in +terms of memory spaces and peripherals. + +Because there is no data dependency between DSP cores, it is possible +to do perform an IIR in DSP core 1, while also performing an IIR in DSP core 2 +on separate input data, using different coefficients. + + +III. DESCRIPTION OF INPUT DATA + +1. INPUT SAMPLES: +----------------- +This IIR routine expects input data which conforms to the following criteria: + +Generate input data such that an array of input fixed point values are +in 1.15 format, with the data being arranged in the following order: + +INPUT DATA + +indata(0) +indata(1) +indata(2) +indata(3) +etc... + + +2. COEFFICIENT DATA: +----------------------- +This IIR routine expects [Biquad_secs*4] fixed point values to be used as coefficients. + + +COEFFICIENT DATA + +A2(0) +A1(0) +B2(0) +B1(0) +... +... +... + + + + diff --git a/examples/adsp-2191_iir/coef_hex.dat b/examples/adsp-2191_iir/coef_hex.dat new file mode 100644 index 0000000..afc6f8e --- /dev/null +++ b/examples/adsp-2191_iir/coef_hex.dat @@ -0,0 +1,8 @@ +0xce58, +0x113e, +0x7fff, +0x7fff, +0xd7cf, +0xf7ce, +0x7fff, +0x7fff diff --git a/examples/adsp-2191_iir/iir.asm b/examples/adsp-2191_iir/iir.asm new file mode 100644 index 0000000..2ea8494 --- /dev/null +++ b/examples/adsp-2191_iir/iir.asm @@ -0,0 +1,97 @@ +/************************************************************** + +File Name: IIR.asm + +Date Modified: 6/21/01 BJM + + +Description: + Subroutine that implements a IIR Filter given + coefficients and samples. + + Equation: + w(n) = x(n) + A1*w(n-1) + A2*w(n-2) + y(n) = w(n) + B1*w(n-1) + B2*w(n-2) (single biquad structure) + +Calling Parameters: + b0,i0 = address of delay line buffer + l0 = length of delay line buffer + b1,i1 = address of input samples buffer + b4,i4 = address of coefficients buffer + l4 = length of coefficients buffer + b2,i2 = address of output buffer + + +Assumptions: + The coefficient buffer should be in the order A2, A1, B2, B1 for each + biquad section. + + Delay line, Output and Input buffers stored in DM Block(16-bit). + Instructions, and Coefficients stored in PM Block(24-bit). + + Block 0: + Coefficient buffer = { A2[0],A1[0],B2[0],B1[0],A2[1],A1[1],B2[1],... } + + Block 1: + Input buffer ={ In[0],In[1],In[2],... } + Output buffer ={ Out[0],Out[1],Out[2],... } + +Return Values: + i2 = output buffer + i0 = delay line pointer + +Registers Affected: + i0,i1,i2,i4,MX,MY,MR,SR + +Cycle Count: + +Memory Usage: + Instructions Words (24-bits): + 17 (IIR) + 6 (Dline Init) instruction words + + Data Words (16 or 24-bits): + Coefs = Number of locations for coefficients (24-bits) + 2*Biquad_secs = Number of locations for the delay line (16-bits) + N_samp = Number of samples locations for the input (16-bits) + N_samp = Number of samples locations for the output (16-bits) + +Notes: + +**************************************************************/ + +#define N_samp 256 +#define Biquad_secs 2 + +.GLOBAL IIR, Zero_Dline; +.EXTERN Dline, Coefs, Outbuf; + +.section/pm program; +IIR: + SE = 0; + CNTR = N_samp; /* Set CNTR for N input samples */ + DO filtering UNTIL CE; + MX0 = DM(I1,M3); /* Read Input sample */ + MY0 = 0x2000; + CNTR = Biquad_secs; /* Loop for each biquad */ + MR = MX0*MY0(SU),MX0 = DM(I0,M3), MY0 = PM(I4,M4); /* Scale input, fetch current biquad A2 */ + DO quads UNTIL CE; + MR = MR+MX0*MY0(SS), MX1 = DM(I0,M3), MY0 = PM(I4,M4); /* Fetch current biquad A1 */ + MR = MR+MX1*MY0(SS), MY0 = PM(I4,M4); /* Fetch current biquad B2 */ + SR = ASHIFT MR1(HI), MY1 = PM(I4,M4); /* Fetch current biquad B1 */ + MR = MR+MX0*MY0(SS), MX0 = DM(I0,M0), MY0 = PM(I4,M4); /* Fetch next biquad A2 */ +quads: + DM(I0,M3) = SR1, MR = MR+MX1*MY1(SS); +filtering: + DM(I2,M3) = MR1; /* Write filtered output */ + rts (db); + nop;nop; + + +.section/pm program; +Zero_Dline: + CNTR=LENGTH(Dline); + DO zero UNTIL CE; +zero: DM(I0,M0)=0; /* Zero the delay line */ + rts (db); + nop;nop; + diff --git a/examples/adsp-2191_iir/iir_test.asm b/examples/adsp-2191_iir/iir_test.asm new file mode 100644 index 0000000..41ebbbe --- /dev/null +++ b/examples/adsp-2191_iir/iir_test.asm @@ -0,0 +1,64 @@ +/************************************************************************ +File Name: IIR_test.asm + +Date Modified: 6/21/01 BJM + +Description: ADSP-2192 single-core program to call + IIR.asm. IIR.asm implements a Cascaded + Biquad IIR filter. All data values and + coefficients are assumed to be in 1.15 + format. + +************************************************************************/ + +#define N_samp 256 +#define Biquad_secs 2 +#define Coef_Length 4*Biquad_secs + 1 + +.EXTERN IIR, Zero_Dline; +.GLOBAL Dline, Coefs, Outbuf; + +/* A2 A1 B2 B1 A2 A1 B2 B1 */ +/* A21, A11, B21, B11, A22, A12, B22, B12*/ +.section/pm data2; +.VAR Coefs[4 * Biquad_secs] = "coef_hex.dat"; + +.section/data data1; +.VAR Inbuf[N_samp] = "inreal_256.dat"; +.VAR Dline[2 * Biquad_secs]; +.VAR Outbuf[N_samp]; /* Filtered sample buffer */ + +/* PM interrupt vector code */ +.section/pm IVreset; + JUMP start; NOP; NOP; NOP; /* Interupt vector table */ + +/* Program memory code */ +.section/pm program; +start: + DMPG2 = page(Coefs); + I0=Dline; /* Initialize delay line pointer */ + I1 = Inbuf; /* Initialize input data pointer */ + I2 = Outbuf; /* Initialize output data pointer */ + I4 = Coefs; + M0=1; + M3 = 1; + M4 = 1; + AX0 = I0; + reg(B0) = AX0; /* Initialize pointer to delay line */ + AX0 = I4; + reg(B4) = AX0; /* Initialize pointer to delay line */ + + CALL Zero_Dline (db); /* Call zero delay function */ + L0 = length(Dline); /* Initialize delay line circular buffer */ + L1 = 0; /* Initialize for modulo addressing */ + CALL IIR (db); /* Call IIR filter function */ + M0 = 0; + L4 = Coef_Length; /* Initialize for modulo addressing */ + +looping: JUMP looping; /* Loop upon itself */ + + + + + + diff --git a/examples/adsp-2191_iir/inreal_256.dat b/examples/adsp-2191_iir/inreal_256.dat new file mode 100644 index 0000000..5ffa8a3 --- /dev/null +++ b/examples/adsp-2191_iir/inreal_256.dat @@ -0,0 +1,256 @@ +-5, +231, +-69, +118, +-112, +98, +-152, +56, +-260, +-42, +226, +-24, +130, +-69, +123, +-112, +104, +-211, +-33, +229, +0, +80, +-69, +87, +-127, +71, +-208, +-73, +194, +32, +49, +-42, +58, +-97, +62, +-197, +-112, +168, +78, +35, +20, +54, +-53, +50, +-152, +-125, +159, +133, +3, +44, +7, +-32, +10, +-118, +-150, +126, +157, +-31, +69, +-49, +-18, +-45, +-98, +-185, +97, +185, +-68, +102, +-52, +48, +-41, +-26, +-198, +79, +220, +-77, +122, +-77, +77, +-74, +10, +-216, +53, +232, +-84, +138, +-94, +103, +-96, +49, +-215, +35, +243, +-87, +115, +-125, +94, +-141, +33, +-270, +-24, +233, +-57, +127, +-101, +111, +-141, +60, +-254, +-27, +239, +-25, +118, +-73, +123, +-118, +84, +-232, +-43, +222, +-1, +93, +-52, +96, +-111, +86, +-215, +-84, +192, +29, +48, +-36, +62, +-100, +60, +-194, +-106, +179, +88, +31, +5, +33, +-71, +41, +-156, +-121, +153, +109, +-23, +15, +-20, +-51, +-4, +-131, +-163, +114, +149, +-44, +62, +-37, +-4, +-28, +-80, +-175, +112, +203, +-53, +112, +-54, +35, +-57, +-40, +-203, +65, +209, +-76, +120, +-86, +70, +-77, +9, +-219, +47, +240, +-75, +126, +-115, +79, +-121, +20, +-245, +11, +230, +-78, +135, +-102, +112, +-119, +75, +-226, +12, +256, +-42, +142, +-91, +117, +-126, +88, +-223, +-8, +244, +-24, +118, +-81, +113, +-131, +73, +-245, +-62, +207, +-22, +57, +-84, +76, +-121, +79, +-222, +-80, +203, +43, +54, +-34, +67, +-94, +72, +-177, +-88, +192, +84, +17, +-5, +22, +-90, +11, +-189, +-153, +134, +105, +-34, +14, +-10, +-38, +11, +-119, +-145, +133 diff --git a/examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi Decoder.txt b/examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi Decoder.txt new file mode 100644 index 0000000..197829f --- /dev/null +++ b/examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi Decoder.txt @@ -0,0 +1,80 @@ +**************************************************************************** + +Viterbi.asm Soft Decision GSM Viterbi Decoder + +Analog Devices, Inc. +DSP Division +Three Technology Way +P.O. Box 9106 +Norwood, MA 02062 + +21-JUNE-2001 BJM + +This directory contains an example ADSP-2191 single-core subroutine +that implements a soft decision half-rate, soft-decision, GSM Viterbi decoder. + +Files contained in this directory: + +VITERBI.dpj VisualDSP project file +VITERBI.asm ADSP-2191 source for Viterbi +ADSP-2191.ldf Linker description file +GSM_REC.dat Soft decision data for Viterbi + _________________________________________________________________ + +CONTENTS + +I. FUNCTION/ALGORITHM DESCRIPTION +II. IMPLEMENTATION DESCRIPTION +III. DESCRIPTION OF INPUT DATA + +I. FUNCTION/ALGORITHM DESCRIPTION + +The project Viterbi.dpj contains an implementation of a single-core +subroutine that implements a half-rate, soft-decision, GSM Vitertbi decoder. + +II. IMPLEMENTATION DESCRIPTION + +1. METRIC UPDATE: +----------------- +The metric update section accumulates branch distance metrics into path metrics. +The lowest path metric at the end of processing is considered to denote the +path most likely to contain the correct decoding of the input. + +Each element of the state_trans[] array represents a state transition. +Each of the 16-bits in an element of state_trans[] represents one of the +16 possible new states, and indicates which of two possible states +is the most likely previous state. + +2. TRACE BACK: +-------------- +The traceback traces back through the state_trans[] array. Starting +with a new state, the bits of "state" are rotated to compute the +position of the bit in the current state_trans[] array element that +represents this new state. This bit indicates which state was previous. +We update the state to the previous state using this bit. + +During any state transition, the most significant of the four bits in +"state" is the most recent input bit to the convolutional encoder. +This is the bit which is added to the output of the decoder. + +III. DESCRIPTION OF INPUT DATA + +1. INPUT SAMPLES: +----------------- +The Viterbi decoder routine expects input data which conforms to the following criteria: + +The class 1 bits are encoded with the 1/2 rate convolutional code defined by +the polynomials: + +G0 = 1 + D3+ D4 +G1 = 1 + D + D3+ D4 + +Encoded outputs are transmitted as signed antipodal analog signals. They are received at +the decoder and quantized. The quantized number is represented in a 2's +compliment giving the range of -8 to 7. The process of quantizing a binary analog signal +with a multi-bit qunatizer is called soft decision. This soft decision is stored in the +array 'SOFT_DEC_INPUT'. + + + + diff --git a/examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi.dpj b/examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi.dpj new file mode 100644 index 0000000000000000000000000000000000000000..289a77e0af3b82ede187065b6af4a5abcad87ec6 GIT binary patch literal 2610 zcmds1-HOvd6rRnxZX4>2S6(O#dMDc<>5u3Ng*2(lK*`o^?TQ4}G?{JFrkygWrNUl# z<9i5R=_@GWBlsx3!8(&P+hkoK&_clzk~wqEH*?NRzkZ8uf!!#B-05%^TwWGH z0qDoQVT;kB$)R7l@nT@-+PlA8CxPc{^s&xb2|Rop8hmA96L+xI#BUk~Yp(LwzPhw%Jz(N@aj-iY=Sk QC&{#=AG1n~5$gc>1MOw$)c^nh literal 0 HcmV?d00001 diff --git a/examples/adsp-2191_viterbi_decoder/ADSP-2191.ldf b/examples/adsp-2191_viterbi_decoder/ADSP-2191.ldf new file mode 100644 index 0000000..c83a0cd --- /dev/null +++ b/examples/adsp-2191_viterbi_decoder/ADSP-2191.ldf @@ -0,0 +1,115 @@ + +ARCHITECTURE(ADSP-2191) + +$OBJECTS = $COMMAND_LINE_OBJECTS; +// This memory map is set up to facilite testing of the tool +// chain -- code and data area are as large as possible. + +MEMORY +{ + seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) } + seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) } + seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) } + + seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x0088ff) WIDTH(16) } + seg_buf1 { TYPE(DM RAM) START(0x008900) END(0x0095ff) WIDTH(16) } + seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) } + seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) } + seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) } + seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) } +} + +PROCESSOR p0 +{ + LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) + OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) + + SECTIONS + { + sec_dmy + { + INPUT_SECTIONS( $OBJECTS(IVreset)) + } > seg_dmy + + sec_itab + { + INPUT_SECTIONS( $OBJECTS(IVpwrdwn)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVkernel)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVstackint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVmailboxint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVtimerint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVringint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVpcibmint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVdspdspint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint13)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVint14)) + . = .+0x1; + INPUT_SECTIONS( $OBJECTS(IVac97frint)) + . = .+0x1; + } > seg_itab + seg_code + { + INPUT_SECTIONS( $OBJECTS(program) ) + } >seg_code + + sec_buf1 + { + INPUT_SECTIONS($OBJECTS(seg_buf1) ) + }>seg_buf1 + + sec_buf2 + { + INPUT_SECTIONS($OBJECTS(seg_buf2) ) + }>seg_buf2 + + sec_data1 + { + INPUT_SECTIONS( $OBJECTS(data1) ) + } >seg_data1 + + sec_data2 + { + INPUT_SECTIONS( $OBJECTS(data2) ) + INPUT_SECTIONS( $OBJECTS(program2) ) + } >seg_data2 + + + // support for initialization, including C++ + sec_ctor + { + INPUT_SECTIONS( $OBJECTS(ctor)) + } >seg_data1 + + // provide linker variables describing the stack (grows down) + // ldf_stack_limit is the lowest address in the stack + // ldf_stack_base is the highest address in the stack + sec_stack + { + ldf_stack_limit = .; + ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1; + } >seg_stack + sec_heap + { + .heap = .; + .heap_size = MEMORY_SIZEOF(seg_heap); + .heap_end = . + MEMORY_SIZEOF(seg_heap) - 1; + } >seg_heap + } +} diff --git a/examples/adsp-2191_viterbi_decoder/ADSP-2191_Viterbi_Decoder.txt b/examples/adsp-2191_viterbi_decoder/ADSP-2191_Viterbi_Decoder.txt new file mode 100644 index 0000000..197829f --- /dev/null +++ b/examples/adsp-2191_viterbi_decoder/ADSP-2191_Viterbi_Decoder.txt @@ -0,0 +1,80 @@ +**************************************************************************** + +Viterbi.asm Soft Decision GSM Viterbi Decoder + +Analog Devices, Inc. +DSP Division +Three Technology Way +P.O. Box 9106 +Norwood, MA 02062 + +21-JUNE-2001 BJM + +This directory contains an example ADSP-2191 single-core subroutine +that implements a soft decision half-rate, soft-decision, GSM Viterbi decoder. + +Files contained in this directory: + +VITERBI.dpj VisualDSP project file +VITERBI.asm ADSP-2191 source for Viterbi +ADSP-2191.ldf Linker description file +GSM_REC.dat Soft decision data for Viterbi + _________________________________________________________________ + +CONTENTS + +I. FUNCTION/ALGORITHM DESCRIPTION +II. IMPLEMENTATION DESCRIPTION +III. DESCRIPTION OF INPUT DATA + +I. FUNCTION/ALGORITHM DESCRIPTION + +The project Viterbi.dpj contains an implementation of a single-core +subroutine that implements a half-rate, soft-decision, GSM Vitertbi decoder. + +II. IMPLEMENTATION DESCRIPTION + +1. METRIC UPDATE: +----------------- +The metric update section accumulates branch distance metrics into path metrics. +The lowest path metric at the end of processing is considered to denote the +path most likely to contain the correct decoding of the input. + +Each element of the state_trans[] array represents a state transition. +Each of the 16-bits in an element of state_trans[] represents one of the +16 possible new states, and indicates which of two possible states +is the most likely previous state. + +2. TRACE BACK: +-------------- +The traceback traces back through the state_trans[] array. Starting +with a new state, the bits of "state" are rotated to compute the +position of the bit in the current state_trans[] array element that +represents this new state. This bit indicates which state was previous. +We update the state to the previous state using this bit. + +During any state transition, the most significant of the four bits in +"state" is the most recent input bit to the convolutional encoder. +This is the bit which is added to the output of the decoder. + +III. DESCRIPTION OF INPUT DATA + +1. INPUT SAMPLES: +----------------- +The Viterbi decoder routine expects input data which conforms to the following criteria: + +The class 1 bits are encoded with the 1/2 rate convolutional code defined by +the polynomials: + +G0 = 1 + D3+ D4 +G1 = 1 + D + D3+ D4 + +Encoded outputs are transmitted as signed antipodal analog signals. They are received at +the decoder and quantized. The quantized number is represented in a 2's +compliment giving the range of -8 to 7. The process of quantizing a binary analog signal +with a multi-bit qunatizer is called soft decision. This soft decision is stored in the +array 'SOFT_DEC_INPUT'. + + + + diff --git a/examples/adsp-2191_viterbi_decoder/GSM_rec.dat b/examples/adsp-2191_viterbi_decoder/GSM_rec.dat new file mode 100644 index 0000000..8f304e3 --- /dev/null +++ b/examples/adsp-2191_viterbi_decoder/GSM_rec.dat @@ -0,0 +1,378 @@ +4, +0, +-3, +-6, +1, +-4, +-5, +-4, +3, +-2, +2, +-6, +1, +-6, +1, +-6, +-1, +-4, +0, +-4, +4, +1, +-5, +6, +3, +3, +-1, +1, +0, +-5, +0, +-1, +-7, +0, +-5, +-3, +-2, +5, +-6, +2, +0, +-4, +2, +-1, +1, +5, +4, +5, +0, +1, +3, +0, +6, +6, +-5, +-3, +-1, +-1, +5, +2, +6, +3, +4, +0, +-6, +-6, +-1, +2, +2, +-1, +-4, +-1, +1, +2, +3, +2, +-5, +6, +6, +-4, +0, +-6, +-5, +-6, +6, +-5, +1, +-7, +-7, +-6, +6, +4, +4, +6, +-7, +6, +-4, +3, +2, +-2, +0, +-1, +-2, +0, +-6, +5, +0, +-4, +-2, +6, +0, +-4, +0, +3, +-2, +3, +-3, +-7, +-6, +0, +1, +-3, +0, +-1, +5, +4, +-5, +6, +2, +-3, +-7, +3, +2, +6, +5, +2, +0, +2, +6, +-3, +3, +2, +0, +2, +-7, +4, +6, +6, +-5, +-4, +0, +4, +1, +-7, +4, +6, +4, +6, +0, +-6, +0, +-4, +2, +4, +2, +0, +-2, +-1, +0, +5, +2, +0, +-2, +5, +2, +-6, +3, +-4, +5, +0, +6, +0, +0, +2, +6, +-7, +1, +5, +-4, +-2, +-2, +-5, +1, +6, +-5, +-7, +-4, +1, +0, +1, +-3, +5, +1, +6, +-7, +-6, +1, +-6, +3, +-5, +-7, +-3, +-2, +0, +6, +-5, +-4, +1, +-2, +6, +0, +1, +2, +3, +-4, +-6, +6, +4, +4, +3, +6, +5, +5, +0, +-7, +-7, +0, +5, +4, +-3, +-2, +-3, +6, +6, +-6, +-1, +-4, +-2, +-7, +2, +0, +4, +1, +-7, +2, +-7, +3, +1, +2, +5, +0, +-5, +-4, +-6, +-7, +4, +-3, +5, +-5, +5, +-2, +-5, +-4, +2, +2, +-5, +3, +-1, +-1, +3, +2, +-5, +5, +0, +6, +3, +-3, +-3, +3, +5, +-5, +-6, +6, +-6, +1, +6, +-7, +-4, +5, +6, +5, +-4, +6, +3, +-6, +-4, +3, +2, +3, +-3, +4, +0, +1, +0, +-7, +4, +1, +3, +-5, +-5, +-6, +-3, +5, +3, +-4, +-7, +6, +-2, +2, +3, +4, +3, +0, +4, +0, +2, +5, +4, +2, +-5, +3, +-4, +-6, +-6, +-2, +-2, +-3, +6, +-4, +-3, +-7, +4, +-1, +0, +-5, +-3, +2, +5, +4, +-5, +5, +5, +-7, +-5, +-7, +-2, +-1, +-4, +0, +2, +4, +-6, +-1, +-2, +4, +1, +-4, +-7 diff --git a/examples/adsp-2191_viterbi_decoder/VITERBI.asm b/examples/adsp-2191_viterbi_decoder/VITERBI.asm new file mode 100644 index 0000000..50e1ad2 --- /dev/null +++ b/examples/adsp-2191_viterbi_decoder/VITERBI.asm @@ -0,0 +1,189 @@ +/************************************************************** +File Name: Viterbi.asm + +Date Modified: 6/23/01 BJM + +Description: + ADSP-2192 single core subroutine that implements the + 1/2 rate GSM soft decision Viterbi decoder. + +Assumptions: + The class 1 bits are encoded with the 1/2 rate convolutional code defined by + the polynomials: + G0 = 1 + D3+ D4 + G1 = 1 + D + D3+ D4 + + Encoded outputs are transmitted as signed antipodal analog signals. They are recieved at + the decoder and quantized. The quantized number is represented in a 2's + compliment giving the range of -8 to 7. The process of quantizing a binary analog signal + with a multi-bit qunatizer is called soft decision. This soft decision is represented by + the array 'SOFT_DEC_INPUT' + + +Registers Affected: + I0,I1,I2,I3,I4 + M0,M1,M2,M3,M4,M5,M6,M7 + L0,L1,L2,L3,L4 + B1,B3,B4 + AX0,AX1,AY0,AY1 + AR,AF,SR,SI,SE + MX0 + +Cycle Count: + 30751 Cycles +Memory Usage: + Instructions Words (24-bits): + 107 instruction words + + Data Words (16 or 24-bits): + 2*N_out = Number of soft decisions (16-bit) + N_out = Number of state transitions (16-bit) + 16 = Number of New and Old metrics (16-bit) + N_Words = Decoded output of GSM frame (16-bit) + 8 = Metric Table (16-bit) + +Notes: + +**************************************************************/ + +#define N_out 189 +#define N_words 12 +#define N_mod_16 13 + +/* DM data */ +.section/data data1; +.VAR soft_dec_input[2*N_out] = "gsm_rec.dat"; +.VAR state_trans[N_out]; +.VAR old_acc_metric[16]; +.VAR new_acc_metric[16]; +.VAR decoded_output[N_words+4]; +.VAR met_table[8]; + + + +/* PM interrupt vector code */ +.section/pm IVreset; + JUMP start; NOP; NOP; NOP; /* Interupt vector table */ + +/* Program memory code */ +.section/pm program; +start: + I0 = soft_dec_input; /* Initialize soft_dec_input pointer */ + L0 = 0; /* Initialize for modulo addressing */ + I1 = old_acc_metric; /* Initialize old_acc_metric pointer */ + L1 = length(old_acc_metric); /* Initialize old_acc_metric circular buffer */ + AX0 = I1; + reg(B1) = AX0; /* Initialize pointer to old_acc_metric */ + I2 = state_trans; /* Initialize state_trans pointer */ + L2 = 0; /* Initialize for modulo addressing */ + I3 = met_table; /* Initialize met_table pointer */ + L3 = length(met_table); /* Initialize met_table circular buffer */ + AX0 = I3; + reg(B3) = AX0; /* Initialize pointer to met_table */ + I4 = new_acc_metric; /* Initialize new_acc_metric pointer */ + L4 = length(new_acc_metric); /* Initialize new_acc_metric circular buffer */ + AX0 = I4; + reg(B4) = AX0; /* Initialize pointer to new_acc_metric */ + M0 = -8; + M1 = 1; + M2 = -16; + M3 = 0; + M4 = 8; + M5 = -7; + M6 = -8; + M7 = -1; + SE = 1; /* Setup bit shift */ + SI = 0X8000; + SR0 = 0; + SR1 = 0; + +CNTR = 16; + DO zero_metric UNTIL CE; +zero_metric: dm(I1,M1) = M3; /* Initialize accumulated metric array */ + + CNTR = N_out; /* FOR (k=0; k> Bit_Pos */ + MR2 = AR, AR = MR0 AND AY1; + SR = LSHIFT MR1 by - 3(LO); + SE = AR; + AR = TSTBIT 0 OF SR0; + SI = AR; + SR = LSHIFT SI (LO); + AR = AX0 OR SR0; + AX0 = AR; + AR = MR0 -1; /* Decoded_output |= ((State & 8) >> 3) << (k & 15) */ + MR0 = AR; +state_bits: + MR1 = MR2; /* State = new_acc_metric */ + MX0 = 16; + dm(I3,M1) = AX0; +trace_back: + AX0 = 0; + +looping: JUMP looping; /* Loop upon itself */ + + diff --git a/examples/isa_test.bin b/examples/isa_test.bin new file mode 100644 index 0000000000000000000000000000000000000000..0ddc7d3675d34897ce9871fc86603eb6f0b7e5d8 GIT binary patch literal 144 zcmZQzU~p7+a7}OYTD8Q5fys%1EkJ-FK!MS~fFXcEB!EFQ{{MFa5QD=2gx2vgEZ}9> z$jk6ZDS=<<0l#tszw!cpJflWMqH=CI*!h7|#SK_ysCq!l1yw$e_W%%)kVs85lx9;!F_92|x;j*&$pI z>8R}Bn%?NOYKaR2lM@45fB-{)0;7QeLjZ$F0E1}!|L+DM28RI%t>a}_z{{|am*J68 z0>9D&e&q&!?g( d$j=~u!T?APXbD&ih=zeDKnBRQFaS~q0stY~BnAKg literal 0 HcmV?d00001 diff --git a/examples/isa_test.o b/examples/isa_test.o new file mode 100644 index 0000000000000000000000000000000000000000..298f9d849e00e9a42c9017b5f210689452758e17 GIT binary patch literal 692 zcmZ{hzfQtX6vn?IAZqavqsADF*fKC-F(x`0G+>At?ckzIDS~JOA*Cidi4S1nBQQ8Q znD_<`J_vDkaC1}7xwP2Do1S}q-*--W|J@e%wiQKzKNO^^e+u~U#Hwt_Ac7Fnrk*d> z?{=OZ3kYo?Y9?T&6vKdtX%jQn&zHdvGx&RsqZh|Z9Pe6LXnmn~h29hTtI)26zAp5> zNOeV0{(nx+NrVS-9G_$u*q_CutUyeJ#qPHngQ{W#NFYL;hg2)cZ2`y3RN+ykD217T z6N*wqA{O^BKo^M90ewK6 z3F!GD^G*4O44D7m82Q{i>ecz}A3Wy7HNIj$v&Tav!y2HRxz1yX!h0U68&v3e9