# ADSP-219x Architecture Reference

## Core Features

The ADSP-219x family is a 16-bit fixed-point DSP core with a 24-bit
instruction word.

- **Harvard Architecture**: Separate Program Memory (PM) and Data
  Memory (DM) buses.
- **Instruction Width**: 24 bits (3 bytes). ROM dumps are typically
  packed (3 bytes per word, big-endian) or padded (4 bytes with a
  leading 0x00).
- **Memory Model**:
  - PM: 24-bit words, up to 64K words (model-dependent).
  - DM: 16-bit words, up to 64K words.

## Register Set

| Group    | Registers (index 0-15)                                                                   | Purpose                                          |
|----------|------------------------------------------------------------------------------------------|--------------------------------------------------|
| **REG0** | AX0, AX1, MX0, MX1, AY0, AY1, MY0, MY1, MR2, SR2, AR, SI, MR1, SR1, MR0, SR0          | ALU, Multiplier, Shifter operand/result registers |
| **REG1** | I0, I1, I2, I3, M0, M1, M2, M3, L0, L1, L2, L3, IMASK, IRPTL, ICNTL, CNTR             | DAG1 + interrupt control + counter               |
| **REG2** | I4, I5, I6, I7, M4, M5, M6, M7, L4, L5, L6, L7, STACKA, LPCSTACKA, (reserved x2)      | DAG2 + stack/loop registers                      |
| **REG3** | ASTAT, MSTAT, SSTAT, LPSTACKP, CCODE, SE, SB, PX, DMPG1, DMPG2, IOPG, IJPG, (res x3), STACKP | Status, page, and control registers              |

## Arithmetic Elements

- **ALU**: 16-bit, supports add/subtract/logic/pass/abs with
  carry, overflow, and saturation.
- **Multiplier/MAC**: 16x16 -> 40-bit accumulator (MR0/MR1/MR2).
  Signed/unsigned modes (SS, SU, US, UU) plus rounding.
- **Barrel Shifter**: 32-bit shift register (SR0/SR1), supports
  logical/arithmetic shift, normalize, and exponent detect.

## Instruction Encoding (Top-Level Dispatch)

Instructions are decoded by their most-significant bits:

| Bits 23-22 | Bits 21-20 | Type(s)                           |
|------------|------------|-----------------------------------|
| 11         | xx         | Type 1: Compute + DM + PM (multifunction) |
| 10         | xx         | Type 3/3a: Direct memory access   |
| 01         | 00         | Type 6: Dreg = Imm16 (REG0)      |
| 01         | 01         | Type 7: Reg = Imm16 (REG1)       |
| 01         | 10         | Type 11/33/34/35 (DO, IO, REG3)  |
| 01         | 11         | Type 4: Compute + DM/PM postmodify |
| 00         | 11         | Type 7: Reg = Imm16 (REG2)       |
| 00         | 10         | Type 9/9a: Compute (standalone)   |
| 00         | 01         | Type 10/10a: Jump/Call            |
| 00         | 00         | Type 15/17/18/20/25/30/31 (misc)  |

## Boot and ROM Format

The ADSP-2191 boots from external memory (SPI flash, host, etc.).
A raw ROM dump contains packed 24-bit instructions in big-endian
byte order. Boot-stream images may include block headers:

    [Target Addr] [Byte Count] [Flags] [Data...]

The reset vector is at PM address 0x0000.