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Viterbi.asm      Soft Decision GSM Viterbi Decoder

Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062

21-JUNE-2001 BJM

This directory contains an example ADSP-2191 single-core subroutine 
that implements a soft decision half-rate, soft-decision, GSM Viterbi decoder.

Files contained in this directory:

VITERBI.dpj			VisualDSP project file
VITERBI.asm			ADSP-2191 source for Viterbi
ADSP-2191.ldf			Linker description file 
GSM_REC.dat			Soft decision data for Viterbi
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CONTENTS

I.    FUNCTION/ALGORITHM DESCRIPTION
II.   IMPLEMENTATION DESCRIPTION
III.  DESCRIPTION OF INPUT DATA         

I. FUNCTION/ALGORITHM DESCRIPTION

The project Viterbi.dpj contains an implementation of a single-core
subroutine that implements a half-rate, soft-decision, GSM Vitertbi decoder.  

II.   IMPLEMENTATION DESCRIPTION

1. METRIC UPDATE:
-----------------
The metric update section accumulates branch distance metrics into path metrics.
The lowest path metric at the end of processing is considered to denote the 
path most likely to contain the correct decoding of the input. 

Each element of the state_trans[] array represents a state transition.  
Each of the 16-bits in an element of state_trans[] represents one of the
16 possible new states, and indicates which of two possible states
is the most likely previous state.

2. TRACE BACK:
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The traceback traces back through the state_trans[] array.  Starting
with a new state, the bits of "state" are rotated to compute the
position of the bit in the current state_trans[] array element that 
represents this new state.  This bit indicates which state was previous.  
We update the state to the previous state using this bit. 

During any state transition, the most significant of the four bits in
"state" is the most recent input bit to the convolutional encoder.
This is the bit which is added to the output of the decoder.

III.  DESCRIPTION OF INPUT DATA

1. INPUT SAMPLES:
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The Viterbi decoder routine expects input data which conforms to the following criteria:

The class 1 bits are encoded with the 1/2 rate convolutional code defined by 
the polynomials:

G0 = 1 + D3+ D4
G1 = 1 + D + D3+ D4

Encoded outputs are transmitted as signed antipodal analog signals.  They are received at 
the decoder and quantized.  The quantized number is represented in a 2's
compliment giving the range of -8 to 7.  The process of quantizing a binary analog signal
with a multi-bit qunatizer is called soft decision.  This soft decision is stored in the 
array 'SOFT_DEC_INPUT'.