import sys

# AMF (ALU/Multiplier Function) codes (5 bits, 0-31)
AMF_ALU = {
    0x10: "Y", 0x11: "Y+1", 0x12: "X+Y+C", 0x13: "X+Y",
    0x14: "NOT Y", 0x15: "-Y", 0x16: "X-Y+C-1", 0x17: "X-Y",
    0x18: "Y-1", 0x19: "Y-X", 0x1a: "Y-X+C-1", 0x1b: "NOT X",
    0x1c: "X AND Y", 0x1d: "X OR Y", 0x1e: "X XOR Y", 0x1f: "ABS X"
}
AMF_MAC = {
    0x00: "NOP", 0x01: "X * Y (RND)", 0x02: "MR + X * Y (RND)",
    0x03: "MR - X * Y (RND)", 0x04: "X * Y (SS)", 0x05: "X * Y (SU)",
    0x06: "X * Y (US)", 0x07: "X * Y (UU)", 0x08: "MR + X * Y (SS)",
    0x09: "MR + X * Y (SU)", 0x0a: "MR + X * Y (US)", 0x0b: "MR + X * Y (UU)",
    0x0c: "MR - X * Y (SS)", 0x0d: "MR - X * Y (SU)", 0x0e: "MR - X * Y (US)",
    0x0f: "MR - X * Y (UU)"
}

# Registers (RGP, Address)
REG_MAP = {
    (0,0): "AX0", (0,1): "AX1", (0,2): "MX0", (0,3): "MX1",
    (0,4): "AY0", (0,5): "AY1", (0,6): "MY0", (0,7): "MY1",
    (0,8): "MR2", (0,9): "SR2", (0,10): "AR", (0,11): "SI",
    (0,12): "MR1", (0,13): "SR1", (0,14): "MR0", (0,15): "SR0",
    (1,0): "I0", (1,1): "I1", (1,2): "I2", (1,3): "I3",
    (1,4): "M0", (1,5): "M1", (1,6): "M2", (1,7): "M3",
    (1,8): "L0", (1,9): "L1", (1,10): "L2", (1,11): "L3",
    (1,12): "IMASK", (1,13): "IRPTL", (1,14): "ICNTL", (1,15): "STACKA",
    (2,0): "I4", (2,1): "I5", (2,2): "I6", (2,3): "I7",
    (2,4): "M4", (2,5): "M5", (2,6): "M6", (2,7): "M7",
    (2,8): "L4", (2,9): "L5", (2,10): "L6", (2,11): "L7",
    (2,12): "RSVD", (2,13): "CNTR", (2,14): "LPSTACKA", (2,15): "RSVD",
    (3,0): "ASTAT", (3,1): "MSTAT", (3,2): "SSTAT", (3,3): "LPSTACKP",
    (3,4): "CCODE", (3,5): "SE", (3,6): "SB", (3,7): "PX",
    (3,8): "DMPG1", (3,9): "DMPG2", (3,10): "IOPG", (3,11): "IJPG",
    (3,15): "STACKP"
}

# Condition Codes
COND_CODES = {
    0x0: "EQ", 0x1: "NE", 0x2: "GT", 0x3: "LE", 0x4: "LT", 0x5: "GE",
    0x6: "AV", 0x7: "NOT AV", 0x8: "AC", 0x9: "NOT AC", 0xA: "SWCOND",
    0xB: "NOT SWCOND", 0xC: "MV", 0xD: "NOT MV", 0xE: "NOT CE", 0xF: "TRUE"
}

# XOP/YOP Code for ALU/MAC
XOP_ALU = ["AX0", "AX1", "AR", "MR0", "MR1", "MR2", "SR0", "SR1"]
YOP_ALU = ["AY0", "AY1", "AF", "0"] # 11 = 0
XOP_MAC = ["MX0", "MX1", "AR", "MR0", "MR1", "MR2", "SR0", "SR1"]
YOP_MAC = ["MY0", "MY1", "SR1", "0"]

def get_reg_name(rgp, addr):
    return REG_MAP.get((rgp, addr), f"REG({rgp},{addr})")

def decode_24(opcode):
    """
    Decodes a 24-bit ADSP-219x instruction into its assembly string.
    """
    # Type 1: 11xxxxxx (Compute | DregX←DM | DregY←PM)
    if (opcode >> 22) == 0b11:
        pd = (opcode >> 20) & 0x3
        dd = (opcode >> 18) & 0x3
        amf = (opcode >> 13) & 0x1F
        yop = (opcode >> 11) & 0x3
        xop = (opcode >> 8) & 0x7
        pmi = (opcode >> 6) & 0x3
        pmm = (opcode >> 4) & 0x3
        dmi = (opcode >> 2) & 0x3
        dmm = opcode & 0x3
        
        # Check for NOP multifunction (All AMF bits zero)
        if amf == 0:
            comp_str = "NOP"
        elif amf >= 0x10:
            comp_str = f"{AMF_ALU[amf]}({XOP_ALU[xop]}, {YOP_ALU[yop]})"
        else:
            comp_str = f"{AMF_MAC[amf]}({XOP_MAC[xop]}, {YOP_MAC[yop]})"
            
        return f"{comp_str}, {XOP_ALU[dd]} = DM(I{dmi} += M{dmm}), {YOP_ALU[pd]} = PM(I{pmi+4} += M{pmm+4})"

    # Type 3: Register read/write to immediate 16-bit address
    # Type 3 (Ireg/Mreg): 101 D addr16 IREG/MREG
    if (opcode >> 21) == 0b101:
        d = (opcode >> 20) & 0x1
        addr = (opcode >> 4) & 0xFFFF
        reg_code = opcode & 0xF
        reg_rgp = 1 if reg_code < 8 else 1 # Simple I/M mapping for type 3
        # In reality, Type 3 Ireg/Mreg uses a specific table. 0-7 are I0-I7, 8-15 are M0-M7.
        reg_name = f"I{reg_code}" if reg_code < 8 else f"M{reg_code-8}"
        if d: return f"DM(0x{addr:04X}) = {reg_name}"
        else: return f"{reg_name} = DM(0x{addr:04X})"

    # Type 6: 0100 Dreg Data16 (Dreg = Data16)
    if (opcode >> 20) == 0b0100:
        data = (opcode >> 4) & 0xFFFF
        dreg = opcode & 0xF
        reg_name = get_reg_name(0, dreg)
        return f"{reg_name} = 0x{data:04X}"

    # Type 10: 000110B addr13 COND (Jump relative)
    if (opcode >> 19) == 0b00011:
        type_bits = (opcode >> 17) & 0x7
        if type_bits == 0b110: # Type 10: 00011 0 delayed(B) ...
            b = (opcode >> 16) & 0x1
            addr = (opcode >> 4) & 0x1FFF
            cond = opcode & 0xF
            db = " (DB)" if b else ""
            cond_str = f"IF {COND_CODES[cond]} " if cond != 0xF else ""
            return f"{cond_str}JUMP 0x{addr:04X}{db}"
        elif type_bits == 0b100: # Type 12: Shift | Dreg ...
            pass # TODO

    # Type 30: 00000000 (NOP)
    if (opcode >> 12) == 0:
        return "NOP"

    return f"UNKNOWN (0x{opcode:06X})"

def main():
    if len(sys.argv) < 2:
        print("Usage: adsp219x_disasm.py <rom.bin> [3|4 (packed|padded)]")
        return

    filename = sys.argv[1]
    format = int(sys.argv[2]) if len(sys.argv) > 2 else 3 # Default 3-byte packed

    with open(filename, "rb") as f:
        data = f.read()

    step = format
    for i in range(0, len(data), step):
        chunk = data[i:i+step]
        if len(chunk) < 3: break
        
        if format == 3:
            # Packed: B0 B1 B2
            opcode = (chunk[0] << 16) | (chunk[1] << 8) | chunk[2]
        else:
            # Padded 32-bit (assume leading zero or big-endian dump): 0x00 B0 B1 B2
            # or check your dump!
            opcode = (chunk[1] << 16) | (chunk[2] << 8) | chunk[3]

        addr = i // format
        print(f"0x{addr:04X}: 0x{opcode:06X}  {decode_24(opcode)}")

if __name__ == "__main__":
    main()