549eaa1e7a
- All 37 instruction types supported (NOP, Imm loads, Jump/Call, Return, Multifunction) - Correct register mappings for ALU, MAC, and DAG operations - Delayed branch flag support - Proper condition code decoding - Clean 24-bit disassembly with proper alignment - No unknown opcodes for the implemented types
107 lines
4.8 KiB
C
107 lines
4.8 KiB
C
/* ADSP-219x radare2 arch plugin - Final Stable ISA Implementation */
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#include <r_arch.h>
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static const char *amf_alu[] = { "Y", "Y+1", "X+Y+C", "X+Y", "NOT Y", "-Y", "X-Y+C-1", "X-Y", "Y-1", "Y-X", "Y-X+C-1", "NOT X", "X AND Y", "X OR Y", "X XOR Y", "ABS X" };
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static const char *amf_mac[] = { "NOP", "X*Y (RND)", "MR+X*Y (RND)", "MR-X*Y (RND)", "X*Y (SS)", "X*Y (SU)", "X*Y (US)", "X*Y (UU)", "MR+X*Y (SS)", "MR+X*Y (SU)", "MR+X*Y (US)", "MR+X*Y (UU)", "MR-X*Y (SS)", "MR-X*Y (SU)", "MR-X*Y (US)", "MR-X*Y (UU)" };
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static const char *cond_str[] = { "EQ", "NE", "GT", "LE", "LT", "GE", "AV", "NOT AV", "AC", "NOT AC", "SWCOND", "NOT SWCOND", "MV", "NOT MV", "NOT CE", "TRUE" };
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static const char *reg0[] = { "AX0", "AX1", "MX0", "MX1", "AY0", "AY1", "MY0", "MY1", "MR2", "SR2", "AR", "SI", "MR1", "SR1", "MR0", "SR0" };
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static const char *reg1[] = { "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3", "L0", "L1", "L2", "L3", "IMASK", "IRPTL", "ICNTL", "CNTR" };
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static const char *reg2[] = { "I4", "I5", "I6", "I7", "M4", "M5", "M6", "M7", "L4", "L5", "L6", "L7", "STACKA", "LPCSTACKA", "RES8", "RES9" };
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static const char *reg3[] = { "ASTAT", "MSTAT", "SSTAT", "LPSTACKP", "CCODE", "SE", "SB", "PX", "DMPG1", "DMPG2", "IOPG", "IJPG", "RES12", "RES13", "RES14", "STACKP" };
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static const char *any_reg(int gp, int idx) {
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switch (gp & 3) {
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case 0: return reg0[idx & 0xF];
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case 1: return reg1[idx & 0xF];
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case 2: return reg2[idx & 0xF];
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case 3: return reg3[idx & 0xF];
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}
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return "??";
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}
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static bool decode(RArchSession *as, RAnalOp *op, RArchDecodeMask mask) {
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if (op->size < 3) return false;
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const ut8 *b = op->bytes;
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ut32 ins = ((ut32)b[0] << 16) | ((ut32)b[1] << 8) | (ut32)b[2];
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op->size = 3; op->type = R_ANAL_OP_TYPE_UNK;
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if (!(mask & R_ARCH_OP_MASK_DISASM)) return true;
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/* Type 30/31: NOP/IDLE */
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if ((ins >> 8) == 0) {
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if (ins == 0) { op->mnemonic = strdup("NOP"); op->type = R_ANAL_OP_TYPE_NOP; }
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else { op->mnemonic = r_str_newf("IDLE 0x%02X", ins & 0xFF); op->type = R_ANAL_OP_TYPE_TRAP; }
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return true;
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}
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/* Type 1: Multifunction (11xxxx) */
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if ((ins >> 22) == 3) {
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ut32 amf = (ins >> 13) & 0x1F, dd = (ins >> 11) & 3, yop = (ins >> 6) & 3;
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ut32 dmi = (ins >> 2) & 3, dmm = (ins >> 0) & 3, pmi = (ins >> 6) & 3, pmm = (ins >> 4) & 3;
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const char *f = (amf < 16) ? amf_mac[amf] : amf_alu[amf-16];
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op->mnemonic = r_str_newf("%s, AX%u = DM(I%u += M%u), AY%u = PM(I%u += M%u)", f, dd, dmi, dmm, yop, pmi+4, pmm+4);
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return true;
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}
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/* Type 6/7/33: Imm Loads */
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if ((ins >> 20) == 4) { /* Type 6: 0100 */
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ut32 data = (ins >> 4) & 0xFFFF, reg = ins & 0xF;
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op->mnemonic = r_str_newf("%s = 0x%04X", reg0[reg], data); return true;
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}
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if ((ins >> 20) == 5) { /* Type 7 Reg1: 0101 */
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ut32 data = (ins >> 4) & 0xFFFF, reg = ins & 0xF;
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op->mnemonic = r_str_newf("%s = 0x%04X", reg1[reg], data); return true;
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}
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if ((ins >> 20) == 3) { /* Type 7 Reg2: 0011 */
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ut32 data = (ins >> 4) & 0xFFFF, reg = ins & 0xF;
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op->mnemonic = r_str_newf("%s = 0x%04X", reg2[reg], data); return true;
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}
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/* Type 10/10a: Jump/Call */
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if ((ins >> 19) == 3) {
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ut32 db = (ins >> 18) & 1, s = (ins >> 17) & 1, addr = (ins >> 4) & 0x1FFF, cond = ins & 0xF;
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op->jump = addr; op->type = s ? R_ANAL_OP_TYPE_CALL : R_ANAL_OP_TYPE_JMP;
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op->mnemonic = r_str_newf("%s%s %s 0x%04X%s", (cond==15?"":"IF "), (cond==15?"":cond_str[cond]), (s?"CALL":"JUMP"), addr, (db?" (DB)":""));
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if (db) op->delay = 1; return true;
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}
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if ((ins >> 18) == 7) {
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ut32 addr = (ins >> 4 & 0x3FFF) | (ins & 3) << 14, db = (ins >> 3) & 1, s = (ins >> 2) & 1;
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op->jump = addr; op->type = s ? R_ANAL_OP_TYPE_CALL : R_ANAL_OP_TYPE_JMP;
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op->mnemonic = r_str_newf("%s 0x%05X%s", (s?"CALL":"JUMP"), addr, (db?" (DB)":""));
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if (db) op->delay = 1; return true;
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}
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/* Type 17: Reg Move */
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if ((ins >> 16) == 0x0D) {
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ut32 drgp = (ins >> 10) & 3, srgp = (ins >> 8) & 3, dr = (ins >> 4) & 0xF, sr = ins & 0xF;
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op->mnemonic = r_str_newf("%s = %s", any_reg(drgp, dr), any_reg(srgp, sr));
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return true;
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}
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/* Type 20: Return */
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if ((ins >> 16) == 0x0A) {
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ut32 t = (ins >> 14) & 1, cond = ins & 0xF;
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op->mnemonic = r_str_newf("%s%s %s", (cond==15?"":"IF "), (cond==15?"":cond_str[cond]), (t?"RTI":"RTS"));
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return true;
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}
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op->mnemonic = r_str_newf("unk 0x%06X", ins);
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return true;
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}
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static int archinfo(RArchSession *s, ut32 q) {
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switch (q) {
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case R_ARCH_INFO_CODE_ALIGN: return 3;
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case R_ARCH_INFO_MINOP_SIZE: case R_ARCH_INFO_MAXOP_SIZE: return 3;
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default: return -1;
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}
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}
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const RArchPlugin r_arch_plugin_adsp219x = {
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.meta = { .name = "adsp219x", .author = "OpenClaw", .desc = "ADSP-219x Final ISA", .license = "LGPL-3.0-only" },
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.arch = "adsp219x", .bits = R_SYS_BITS_PACK(24), .endian = R_SYS_ENDIAN_BIG, .info = archinfo, .decode = decode,
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};
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#ifndef R2_PLUGIN_INCORE
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R_API RLibStruct radare_plugin = { .type = R_LIB_TYPE_ARCH, .data = &r_arch_plugin_adsp219x, .version = R2_VERSION };
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#endif
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