9a82c4d522
Assembler-verified and fixed: - Type 12: XOP field corrected to bits10-8 (was bits11-9) - Type 14: SF=4bits, XREG uses reg0[] not xop_shift[] (was 3-bit OOB) - Type 16: XREG uses reg0[] (was xop_shift[], 4-bit index OOB) - Type 19: I-reg field at bits3-2 (was bits1-0), now correct for jump(i2) - Type 26: Push/Pop encoding is 10/11 not 01/10; PPP=bits6-5, LPP=bits4-3 (was bits6-4, bits3-2) All 6 variants verified: push/pop sts, loop, pc Assembler-verified unchanged: - Type 21/21a: MODIFY correct - Type 23/24: DIVQ/DIVS correct - Type 29: DM immediate modify read/write correct - Type 32: Any Reg <-> DM read/write correct - Type 34/35: IO/System register read/write correct - Type 36: LJUMP 2-word correct - Type 37: SETINT/CLRINT correct Remaining note: Type 12 SF field may use a different mapping than sf_names[] for combined shift+memory ops (ASHIFT encodes as SF=2 not SF=4). Needs further investigation.
ADSP-219x Radare2 Plugin
Native architecture plugin for disassembling ADSP-219x (including ADSP-2191) 24-bit instructions in radare2 and iaito.
Build & Install
make
make install
Requires: GCC, radare2 >= 5.8.0 (RArchPlugin API).
Usage
r2 -a adsp219x -b 24 firmware.bin
Validation
Compare against the assembler-verified test ROM:
r2 -a adsp219x -b 24 -q -c "pd 48" ../examples/isa_test.bin
The test ROM (isa_test.dsp) was assembled with open21xx and
contains known opcodes for all major instruction types.
Coding Standards
This plugin follows the GNU Coding Standards for C source code. No hardcoded absolute paths in any scripts.