58 lines
2.7 KiB
Diff
58 lines
2.7 KiB
Diff
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From e4b0fced6f3fd3c8ce5ab4d3aae97b880e7e07b0 Mon Sep 17 00:00:00 2001
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From: sahil <sahil@arm.com>
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Date: Mon, 2 May 2022 17:43:17 +0530
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Subject: [PATCH] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region
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Enable SCP QSPI flash region access by adding it in the PlatformLibMem
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Upstream-Status: Pending
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Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
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Signed-off-by: sahil <sahil@arm.com>
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Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005
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---
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Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 4 ++++
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.../NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++++-
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2 files changed, 11 insertions(+), 1 deletion(-)
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diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
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index 4966011e..c7219136 100644
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--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
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+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
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@@ -41,6 +41,10 @@
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#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
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#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
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+// SCP QSPI flash device
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+#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000
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+#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000
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+
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/*
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* Platform information structure stored in Non-secure SRAM. Platform
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* information are passed from the trusted firmware with the below structure
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diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
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index 5cacd437..8bb94074 100644
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--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
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+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
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@@ -15,7 +15,7 @@
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#include <NeoverseN1Soc.h>
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// The total number of descriptors, including the final "end-of-table" descriptor.
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-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
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+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20
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/** A helper function to locate the NtFwConfig PPI and get the base address of
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NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
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@@ -283,6 +283,12 @@ ArmPlatformGetVirtualMemoryMap (
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VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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+ // SCP QSPI flash device
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+ VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
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+ VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
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+ VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ;
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+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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+
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if (PlatInfo->MultichipMode == 1) {
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//Remote DDR (2GB)
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VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +
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