openclaw/tqma6-yocto-mirror
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Complete Yocto mirror with license table for TQMa6UL (2038-compliance)

Browse Source 
- 264 license table entries with exact download URLs (224/264 resolved)
- Complete sources/ directory with all BitBake recipes
- Build configuration: tqma6ul-multi-mba6ulx, spaetzle (musl)
- Full traceability for Softwarefreigabeantrag
- GCC 13.4.0, Linux 6.6.102, U-Boot 2023.04, musl 1.2.4
- License distribution: GPL-2.0 (24), MIT (23), GPL-2.0+ (18), BSD-3 (16)
This commit is contained in:
Siggi (OpenClaw Agent)
2026-03-01 20:58:18 +00:00
commit 16accb6b24
15086 changed files with 1292356 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

471
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch Normal file
View File

@@ -0,0 +1,471 @@
From 928cb457b9ab2abefbacad655eefdde943b4ee9a Mon Sep 17 00:00:00 2001
From: sahil <sahil@arm.com>
Date: Thu, 17 Mar 2022 16:28:05 +0530
Subject: [PATCH] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG
NT_FW_CONFIG DTB contains platform information passed by
Tf-A boot stage.
This information is used for Virtual memory map generation
during PEI phase and passed on to DXE phase as a HOB, where
it is used in ConfigurationManagerDxe.
Upstream-Status: Pending
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I54a86277719607eb00d4a472fae8f13c180eafca
---
.../ConfigurationManager.c | 24 ++--
.../ConfigurationManagerDxe.inf | 3 +-
.../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 16 +--
.../Library/PlatformLib/AArch64/Helper.S | 4 +-
.../Library/PlatformLib/PlatformLib.c | 12 +-
.../Library/PlatformLib/PlatformLib.inf | 8 +-
.../Library/PlatformLib/PlatformLibMem.c | 103 +++++++++++++++++-
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 7 +-
8 files changed, 152 insertions(+), 25 deletions(-)
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index a6b4cb0e..c15020f5 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -1,7 +1,7 @@
/** @file
Configuration Manager Dxe
- Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+ Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -16,6 +16,7 @@
#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
#include <Library/ArmLib.h>
#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
@@ -28,6 +29,7 @@
#include "Platform.h"
extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat;
+static NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
/** The platform configuration repository information.
*/
@@ -1242,13 +1244,11 @@ InitializePlatformRepository (
IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo
)
{
- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
UINT64 Dram2Size;
UINT64 RemoteDdrSize;
RemoteDdrSize = 0;
- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB);
PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size;
@@ -1512,7 +1512,6 @@ GetGicCInfo (
)
{
EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
UINT32 TotalObjCount;
UINT32 ObjIndex;
@@ -1523,7 +1522,6 @@ GetGicCInfo (
}
PlatformRepo = This->PlatRepoInfo;
- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
if (PlatInfo->MultichipMode == 1) {
TotalObjCount = PLAT_CPU_COUNT * 2;
@@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject (
{
EFI_STATUS Status;
EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
UINT32 AcpiTableCount;
if ((This == NULL) || (CmObject == NULL)) {
@@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject (
Status = EFI_NOT_FOUND;
PlatformRepo = This->PlatRepoInfo;
- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+
AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList);
if (PlatInfo->MultichipMode == 0)
AcpiTableCount -= 1;
@@ -1697,7 +1694,6 @@ GetArmNameSpaceObject (
{
EFI_STATUS Status;
EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
- NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
UINT32 GicRedistCount;
UINT32 GicCpuCount;
UINT32 ProcHierarchyInfoCount;
@@ -1718,8 +1714,6 @@ GetArmNameSpaceObject (
Status = EFI_NOT_FOUND;
PlatformRepo = This->PlatRepoInfo;
- // Probe for multi chip information
- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
if (PlatInfo->MultichipMode == 1) {
GicRedistCount = 2;
GicCpuCount = PLAT_CPU_COUNT * 2;
@@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize (
IN EFI_SYSTEM_TABLE * SystemTable
)
{
+ VOID *PlatInfoHob;
EFI_STATUS Status;
+ PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid);
+
+ if (PlatInfoHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob);
+
// Initialize the Platform Configuration Repository before installing the
// Configuration Manager Protocol
Status = InitializePlatformRepository (
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 4f8e7f13..a4e8b783 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -1,7 +1,7 @@
## @file
# Configuration Manager Dxe
#
-# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -42,6 +42,7 @@
[LibraryClasses]
ArmPlatformLib
+ HobLib
PrintLib
UefiBootServicesTableLib
UefiDriverEntryPoint
diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
index 097160c7..4966011e 100644
--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
+* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -41,11 +41,6 @@
#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
-// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is
-// pre-populated by a earlier boot stage
-#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \
- 0x00008000)
-
/*
* Platform information structure stored in Non-secure SRAM. Platform
* information are passed from the trusted firmware with the below structure
@@ -55,12 +50,17 @@
typedef struct {
/*! 0 - Single Chip, 1 - Chip to Chip (C2C) */
UINT8 MultichipMode;
- /*! Slave count in C2C mode */
- UINT8 SlaveCount;
+ /*! Secondary chip count in C2C mode */
+ UINT8 SecondaryChipCount;
/*! Local DDR memory size in GigaBytes */
UINT8 LocalDdrSize;
/*! Remote DDR memory size in GigaBytes */
UINT8 RemoteDdrSize;
} NEOVERSEN1SOC_PLAT_INFO;
+// NT_FW_CONFIG DT structure
+typedef struct {
+ UINT64 NtFwConfigDtAddr;
+} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI;
+
#endif
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
index 8d2069de..a0b89a7b 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+* Copyright (c) 2019 - 2023, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
// the UEFI firmware through the CPU registers.
//
ASM_PFX(ArmPlatformPeiBootAction):
+ adr x10, NtFwConfigDtBlob
+ str x0, [x10]
ret
//
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
index c0effd37..2f753be7 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
+ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -8,8 +8,12 @@
#include <Library/ArmPlatformLib.h>
#include <Library/BaseLib.h>
+#include <NeoverseN1Soc.h>
#include <Ppi/ArmMpCoreInfo.h>
+UINT64 NtFwConfigDtBlob;
+STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi;
+
STATIC ARM_CORE_INFO mCoreInfoTable[] = {
{ 0x0, 0x0 }, // Cluster 0, Core 0
{ 0x0, 0x1 }, // Cluster 0, Core 1
@@ -46,6 +50,7 @@ ArmPlatformInitialize (
IN UINTN MpId
)
{
+ mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob;
return RETURN_SUCCESS;
}
@@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gArmMpCoreInfoPpiGuid,
&mMpCoreInfoPpi
+ },
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gNtFwConfigDtInfoPpiGuid,
+ &mNtFwConfigDtInfoPpi
}
};
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 96e590cd..78f309c3 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -1,7 +1,7 @@
## @file
# Platform Library for N1Sdp.
#
-# Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -18,10 +18,14 @@
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+[LibraryClasses]
+ FdtLib
+
[Sources.common]
PlatformLibMem.c
PlatformLib.c
@@ -59,7 +63,9 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
[Guids]
+ gArmNeoverseN1SocPlatformInfoDescriptorGuid
gEfiHobListGuid ## CONSUMES ## SystemTable
[Ppis]
gArmMpCoreInfoPpiGuid
+ gNtFwConfigDtInfoPpiGuid
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 339fa07b..1d53ec75 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,11 +10,95 @@
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <libfdt.h>
#include <NeoverseN1Soc.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
+/** A helper function to locate the NtFwConfig PPI and get the base address of
+ NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
+
+ @param [out] plat_info Pointer to the NeoverseN1Soc PLATFORM_INFO HOB
+
+ @retval EFI_SUCCESS Success.
+ returns EFI_INVALID_PARAMETER A parameter is invalid.
+**/
+EFI_STATUS
+GetNeoverseN1SocPlatInfo (
+ OUT NEOVERSEN1SOC_PLAT_INFO *plat_info
+ )
+{
+ CONST UINT32 *Property;
+ INT32 Offset;
+ CONST VOID *NtFwCfgDtBlob;
+ NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi;
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (
+ &gNtFwConfigDtInfoPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&NtFwConfigInfoPpi
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "PeiServicesLocatePpi failed with error %r\n",
+ Status
+ ));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr;
+ if (fdt_check_header (NtFwCfgDtBlob) != 0) {
+ DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info");
+ if (Offset == -FDT_ERR_NOTFOUND) {
+ DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL);
+ if (Property == NULL) {
+ DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ plat_info->LocalDdrSize = fdt32_to_cpu (*Property);
+
+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL);
+ if (Property == NULL) {
+ DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ plat_info->RemoteDdrSize = fdt32_to_cpu (*Property);
+
+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL);
+ if (Property == NULL) {
+ DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ plat_info->SecondaryChipCount = fdt32_to_cpu (*Property);
+
+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL);
+ if (Property == NULL) {
+ DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ plat_info->MultichipMode = fdt32_to_cpu (*Property);
+
+ return EFI_SUCCESS;
+}
+
/**
Returns the Virtual Memory Map of the platform.
@@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap (
NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
UINT64 DramBlock2Size;
UINT64 RemoteDdrSize;
+ EFI_STATUS Status;
Index = 0;
- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+
+ // Create platform info HOB
+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob (
+ &gArmNeoverseN1SocPlatformInfoDescriptorGuid,
+ sizeof (NEOVERSEN1SOC_PLAT_INFO)
+ );
+
+ if (PlatInfo == NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
+ ASSERT (FALSE);
+ return;
+ }
+
+ Status = GetNeoverseN1SocPlatInfo (PlatInfo);
+ ASSERT (Status == 0);
DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
(UINT64)SIZE_1GB);
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index d59f25a5..9e257ebd 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -1,7 +1,7 @@
## @file
# Describes the entire platform configuration.
#
-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,8 @@
Include # Root include for the package
[Guids.common]
+ # ARM NeoverseN1Soc Platform Info descriptor
+ gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } }
gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } }
[PcdsFixedAtBuild]
@@ -83,3 +85,6 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
+
+[Ppis]
+ gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }

63
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch Normal file
View File

@@ -0,0 +1,63 @@
From 2ccb463274d0c04f1e3253194ea6eee80c31cb49 Mon Sep 17 00:00:00 2001
From: Himanshu Sharma <Himanshu.Sharma@arm.com>
Date: Mon, 30 May 2022 10:53:30 +0000
Subject: [PATCH] Platform/ARM/N1Sdp: Modify the IRQ ID of Debug UART and
routing it to IOFPGA UART1
In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the
IPI0 trigger method to "level", which prevented SGI0 to be enabled
again after a CPU offline/online cycle.
This patch fixes the above issue by assigning a reserved IRQ ID
for the Debug UART, other than 0 and also routing it to use IOFPGA
UART1 by unsharing it from currently using serial terminal.
Upstream-Status: Pending
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: Ib35fecc57f1d8c496135c18dbebd0be0a4b76041
---
.../ConfigurationManagerDxe/ConfigurationManager.c | 2 +-
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index b11c0425..44046a00 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -320,7 +320,7 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
// Debug Serial Port
{
FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress
- 0, // Interrupt -unused
+ 250, // Interrupt (reserved)
FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate
FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock
EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index d04b22d3..676ab677 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -4,7 +4,7 @@
# This provides platform specific component descriptions and libraries that
# conform to EFI/Framework standards.
#
-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -136,9 +136,9 @@
gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95
# PL011 Serial Debug UART (DBG2)
- gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|24000000
# SBSA Watchdog
gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93

57
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch Normal file
View File

@@ -0,0 +1,57 @@
From e4b0fced6f3fd3c8ce5ab4d3aae97b880e7e07b0 Mon Sep 17 00:00:00 2001
From: sahil <sahil@arm.com>
Date: Mon, 2 May 2022 17:43:17 +0530
Subject: [PATCH] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region
Enable SCP QSPI flash region access by adding it in the PlatformLibMem
Upstream-Status: Pending
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005
---
Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 4 ++++
.../NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
index 4966011e..c7219136 100644
--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
@@ -41,6 +41,10 @@
#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000
#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000
+// SCP QSPI flash device
+#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000
+#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000
+
/*
* Platform information structure stored in Non-secure SRAM. Platform
* information are passed from the trusted firmware with the below structure
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 5cacd437..8bb94074 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -15,7 +15,7 @@
#include <NeoverseN1Soc.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20
/** A helper function to locate the NtFwConfig PPI and get the base address of
NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
@@ -283,6 +283,12 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // SCP QSPI flash device
+ VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
+ VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
+ VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
if (PlatInfo->MultichipMode == 1) {
//Remote DDR (2GB)
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) +

119
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch Normal file
View File

@@ -0,0 +1,119 @@
From 70e79ba5300f01a13422452c29e26c69042a0c8c Mon Sep 17 00:00:00 2001
From: sahil <sahil@arm.com>
Date: Mon, 2 May 2022 18:50:08 +0530
Subject: [PATCH] Platform/ARM/N1Sdp: NOR flash library for N1Sdp
Add NOR flash library, this library provides APIs for getting the list
of NOR flash devices on the platform.
Upstream-Status: Pending
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I39ad4143b7fad7e33b3b151a019a74f23e0ed441
---
.../Library/NorFlashLib/NorFlashLib.c | 52 +++++++++++++++++++
.../Library/NorFlashLib/NorFlashLib.inf | 36 +++++++++++++
2 files changed, 88 insertions(+)
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c
create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c
new file mode 100644
index 00000000..eee3d1c6
--- /dev/null
+++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c
@@ -0,0 +1,52 @@
+/** @file
+ NOR flash lib for N1Sdp
+
+ Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NorFlashPlatformLib.h>
+#include <NeoverseN1Soc.h>
+#include <PiDxe.h>
+
+#define FW_ENV_REGION_BASE FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+#define FW_ENV_REGION_SIZE (FixedPcdGet32 (PcdFlashNvStorageVariableSize) + \
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + \
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize))
+
+STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
+ {
+ /// Environment variable region
+ NEOVERSEN1SOC_SCP_QSPI_AHB_BASE, ///< device base
+ FW_ENV_REGION_BASE, ///< region base
+ FW_ENV_REGION_SIZE, ///< region size
+ SIZE_4KB, ///< block size
+ },
+};
+
+/**
+ Get NOR flash region info
+
+ @param[out] NorFlashDevices NOR flash regions info.
+ @param[out] Count number of flash instance.
+
+ @retval EFI_SUCCESS Success.
+**/
+EFI_STATUS
+NorFlashPlatformGetDevices (
+ OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,
+ OUT UINT32 *Count
+ )
+{
+ if ((NorFlashDevices == NULL) || (Count == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *NorFlashDevices = mNorFlashDevices;
+ *Count = ARRAY_SIZE (mNorFlashDevices);
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
new file mode 100644
index 00000000..784856c8
--- /dev/null
+++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
@@ -0,0 +1,36 @@
+## @file
+# NOR flash lib for N1Sdp
+#
+# Copyright (c) 2023, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = NorFlashN1SdpLib
+ FILE_GUID = 7006fcf1-a585-4272-92e3-b286b1dff5bb
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NorFlashPlatformLib
+
+[Sources.common]
+ NorFlashLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/ARM.dec
+ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize

2538
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch Normal file
View File

File diff suppressed because it is too large Load Diff

88
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch Normal file
View File

@@ -0,0 +1,88 @@
From e79fd5cfa3190eb27a9637facc9891cab55b5e09 Mon Sep 17 00:00:00 2001
From: sahil <sahil@arm.com>
Date: Mon, 2 May 2022 19:24:47 +0530
Subject: [PATCH] Platform/ARM/N1Sdp: Persistent storage for N1Sdp
Enable persistent storage on QSPI flash device.
Upstream-Status: Pending
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I403113bb885d1d411d433a7f266715d007509a5e
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 18 +++++++++++++-----
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 4 +++-
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 676ab677..80bc875a 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -44,6 +44,9 @@
# file explorer library support
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ # NOR flash support
+ NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf
+
[LibraryClasses.common.SEC]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -161,11 +164,9 @@
# ACPI Table Version
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
- # Runtime Variable storage
- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
+ # NOR flash support
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000
################################################################################
#
@@ -197,6 +198,12 @@
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
}
+ # NOR flash support
+ Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf {
+ <LibraryClasses>
+ NorFlashPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf
+ }
+
# Architectural Protocols
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
@@ -217,6 +224,7 @@
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
}
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
index e5e24ea5..4329f892 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
@@ -1,7 +1,7 @@
## @file
# FDF file of N1Sdp
#
-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -140,6 +140,8 @@ READ_LOCK_STATUS = TRUE
INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
+
INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf

50
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch Normal file
View File

@@ -0,0 +1,50 @@
From 5e8fbb3ba0f634f7fc873c6577269845f9e243db Mon Sep 17 00:00:00 2001
From: sahil <sahil@arm.com>
Date: Mon, 2 May 2022 19:28:19 +0530
Subject: [PATCH] Platform/ARM/N1Sdp: Enable FaultTolerantWrite Dxe driver for
N1Sdp
Upstream-Status: Pending
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: If448ad95b2e72cef31ce1e1e5ab2504d607f0545
---
Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +++++
Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 +
2 files changed, 6 insertions(+)
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 80bc875a..90a0d5b6 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -165,6 +165,10 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
# NOR flash support
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x18F40000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x18F20000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00020000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000
@@ -227,6 +231,7 @@
NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
}
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
# ACPI Support
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
index 4329f892..17d370a3 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf
@@ -90,6 +90,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Metronome/Metronome.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf

197
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch Normal file
View File

@@ -0,0 +1,197 @@
From 6d274379f584a638c1f2b4b8a19014d4baef1d9f Mon Sep 17 00:00:00 2001
From: sahil <sahil@arm.com>
Date: Thu, 11 Aug 2022 11:26:29 +0530
Subject: [PATCH] Platform/ARM/N1Sdp: manually poll QSPI status bit after
erase/write
This patch adds a function to poll Nor flash memory's status register
bit (WIP bit) to wait for an erase/write operation to complete.
The polling timeout is set to 1 second.
Upstream-Status: Pending
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ie678b7586671964ae0f8506a0542d73cbddddfe4
---
.../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 1 +
.../Drivers/CadenceQspiDxe/CadenceQspiReg.h | 6 +-
.../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 80 ++++++++++++++++++-
.../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 5 ++
4 files changed, 88 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
index 4f20c3ba..7a39eb2d 100644
--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf
@@ -39,6 +39,7 @@
MemoryAllocationLib
NorFlashInfoLib
NorFlashPlatformLib
+ TimerLib
UefiBootServicesTableLib
UefiDriverEntryPoint
UefiLib
diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
index fe3b327c..1971631d 100644
--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h
@@ -16,13 +16,15 @@
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS 19
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS 16
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT 0x02
-#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B 0x03
-#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B 0x02
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS 24
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE 0x01
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B 0x02
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS 23
#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS 20
+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C 0x8
+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS 7
+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS)
+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS)
#define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET 0xA0
diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
index 188c75e2..6832351a 100644
--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c
@@ -10,6 +10,7 @@
#include <Library/MemoryAllocationLib.h>
#include <Library/NorFlashInfoLib.h>
#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
@@ -184,6 +185,74 @@ FreeInstance:
return Status;
}
+/**
+ Converts milliseconds into number of ticks of the performance counter.
+
+ @param[in] Milliseconds Milliseconds to convert into ticks.
+
+ @retval Milliseconds expressed as number of ticks.
+
+**/
+STATIC
+UINT64
+MilliSecondsToTicks (
+ IN UINTN Milliseconds
+ )
+{
+ CONST UINT64 NanoSecondsPerTick = GetTimeInNanoSecond (1);
+
+ return (Milliseconds * 1000000) / NanoSecondsPerTick;
+}
+
+/**
+ Poll Status register for NOR flash erase/write completion.
+
+ @param[in] Instance NOR flash Instance.
+
+ @retval EFI_SUCCESS Request is executed successfully.
+ @retval EFI_TIMEOUT Operation timed out.
+ @retval EFI_DEVICE_ERROR Controller operartion failed.
+
+**/
+STATIC
+EFI_STATUS
+NorFlashPollStatusRegister (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ BOOLEAN SRegDone;
+ UINT32 val;
+
+ val = SPINOR_OP_RDSR << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
+ CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS |
+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(1) |
+ CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C << CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS;
+
+ CONST UINT64 TickOut =
+ GetPerformanceCounter () + MilliSecondsToTicks (SPINOR_SR_WIP_POLL_TIMEOUT_MS);
+
+ do {
+ if (GetPerformanceCounter () > TickOut) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "NorFlashPollStatusRegister: Timeout waiting for erase/write.\n"
+ ));
+ return EFI_TIMEOUT;
+ }
+
+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ SRegDone =
+ (MmioRead8 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET)
+ & SPINOR_SR_WIP) == 0;
+
+ } while (!SRegDone);
+
+ return EFI_SUCCESS;
+}
+
/**
Check whether NOR flash opertions are Locked.
@@ -305,12 +374,16 @@ NorFlashEraseSingleBlock (
DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS |
- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS;
+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(3);
if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) {
return EFI_DEVICE_ERROR;
}
+ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) {
+ return EFI_DEVICE_ERROR;
+ }
+
return EFI_SUCCESS;
}
@@ -383,6 +456,9 @@ NorFlashWriteSingleWord (
return EFI_DEVICE_ERROR;
}
MmioWrite32 (WordAddress, WriteData);
+ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) {
+ return EFI_DEVICE_ERROR;
+ }
return EFI_SUCCESS;
}
@@ -907,7 +983,7 @@ NorFlashReadID (
val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS |
CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS |
- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS;
+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(3);
if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) {
return EFI_DEVICE_ERROR;
diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
index e720937e..eb0afc60 100644
--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h
@@ -477,8 +477,13 @@ NorFlashReadID (
OUT UINT8 JedecId[3]
);
+#define SPINOR_SR_WIP BIT0 // Write in progress
+
#define SPINOR_OP_WREN 0x06 // Write enable
#define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block
#define SPINOR_OP_RDID 0x9f // Read JEDEC ID
+#define SPINOR_OP_RDSR 0x05 // Read status register
+
+#define SPINOR_SR_WIP_POLL_TIMEOUT_MS 1000u // Status Register read timeout
#endif /* NOR_FLASH_DXE_H_ */

72
sources/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0009-Platform-ARM-N1Sdp-Reserve-OP-TEE-Region-from-UEFI.patch Normal file
View File

@@ -0,0 +1,72 @@
From 60dfd5bb8f25fa5f0b6c07c3098836bec1668c19 Mon Sep 17 00:00:00 2001
From: Mariam Elshakfy <mariam.elshakfy@arm.com>
Date: Thu, 14 Mar 2024 14:47:27 +0000
Subject: [PATCH] Platform/ARM/N1Sdp: Reserve OP-TEE Region from UEFI
To enable cache on N1SDP, OP-TEE has to be moved
to run from DDR4 memory. Since this memory is
known to application side, it must be reserved
Upstream-Status: Inappropriate [will not be submitted as it's a workaround to address hardware issue]
Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
---
.../Library/PlatformLib/PlatformLib.inf | 3 +++
.../Library/PlatformLib/PlatformLibMem.c | 13 +++++++++++++
Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 4 ++++
3 files changed, 20 insertions(+)
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 78f309c3aa..dc82d5bd87 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -62,6 +62,9 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize
+
[Guids]
gArmNeoverseN1SocPlatformInfoDescriptorGuid
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 8bb9407490..d8ad0f975c 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -150,6 +150,19 @@ ArmPlatformGetVirtualMemoryMap (
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED;
+ // Reserved OP-TEE region
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ PcdGet64 (PcdOpteeMemoryBase),
+ PcdGet64 (PcdOpteeMemorySize)
+ );
+ BuildMemoryAllocationHob (
+ PcdGet64 (PcdOpteeMemoryBase),
+ PcdGet64 (PcdOpteeMemorySize),
+ EfiReservedMemoryType
+ );
+
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index 9e257ebde0..587319262a 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -86,5 +86,9 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
+ # Base Address of OP-TEE
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase|0xDE000000|UINT64|0x00000052
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize|0x02000000|UINT64|0x00000053
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }
--
2.38.1