Complete Yocto mirror with license table for TQMa6UL (2038-compliance)
- 264 license table entries with exact download URLs (224/264 resolved) - Complete sources/ directory with all BitBake recipes - Build configuration: tqma6ul-multi-mba6ulx, spaetzle (musl) - Full traceability for Softwarefreigabeantrag - GCC 13.4.0, Linux 6.6.102, U-Boot 2023.04, musl 1.2.4 - License distribution: GPL-2.0 (24), MIT (23), GPL-2.0+ (18), BSD-3 (16)
This commit is contained in:
Siggi (OpenClaw Agent)
@@ -0,0 +1,47 @@
|
||||
From 32ae4539865e64bcfb0c6955bdac8db5904e493d Mon Sep 17 00:00:00 2001
|
||||
From: Manoj Kumar <manoj.kumar3@arm.com>
|
||||
Date: Mon, 1 Feb 2021 21:36:43 +0530
|
||||
Subject: [PATCH] iommu/arm-smmu-v3: workaround for ATC_INV_SIZE_ALL in N1SDP
|
||||
|
||||
ATC_INV_SIZE_ALL request should automatically translate to ATS
|
||||
address which is not happening in SMMUv3 version gone into
|
||||
N1SDP platform. This workaround manually sets the ATS address
|
||||
field to proper value for ATC_INV_SIZE_ALL command.
|
||||
|
||||
Change-Id: If89465be94720a62be85e1e6612f17e93fa9b8a5
|
||||
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
|
||||
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
|
||||
|
||||
Upstream-Status: Inappropriate [Workaround]
|
||||
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
|
||||
---
|
||||
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 +
|
||||
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +
|
||||
2 files changed, 2 insertions(+)
|
||||
|
||||
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
|
||||
index d4d8bfee9feb..0524bf2ec021 100644
|
||||
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
|
||||
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
|
||||
@@ -1738,6 +1738,7 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,
|
||||
};
|
||||
|
||||
if (!size) {
|
||||
+ cmd->atc.addr = ATC_INV_ADDR_ALL;
|
||||
cmd->atc.size = ATC_INV_SIZE_ALL;
|
||||
return;
|
||||
}
|
||||
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
|
||||
index cd48590ada30..20892b2bfe1d 100644
|
||||
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
|
||||
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
|
||||
@@ -472,6 +472,7 @@ struct arm_smmu_cmdq_ent {
|
||||
|
||||
#define CMDQ_OP_ATC_INV 0x40
|
||||
#define ATC_INV_SIZE_ALL 52
|
||||
+ #define ATC_INV_ADDR_ALL 0x7FFFFFFFFFFFF000UL
|
||||
struct {
|
||||
u32 sid;
|
||||
u32 ssid;
|
||||
@@ -0,0 +1,159 @@
|
||||
From fc8605e74b51d9e0ab8efd0489eca2e11d807f07 Mon Sep 17 00:00:00 2001
|
||||
From: Manoj Kumar <manoj.kumar3@arm.com>
|
||||
Date: Tue, 31 Aug 2021 16:15:38 +0000
|
||||
Subject: [PATCH] n1sdp: pci_quirk: add acs override for PCI devices
|
||||
|
||||
Patch taken from:
|
||||
https://gitlab.com/Queuecumber/linux-acs-override/raw/master/workspaces/5.4/acso.patch
|
||||
|
||||
Change-Id: Ib926bf50524ce9990fbaa2f2f8670fe84bd571f9
|
||||
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
|
||||
|
||||
Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
|
||||
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
|
||||
---
|
||||
.../admin-guide/kernel-parameters.txt | 8 ++
|
||||
drivers/pci/quirks.c | 102 ++++++++++++++++++
|
||||
2 files changed, 110 insertions(+)
|
||||
|
||||
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
|
||||
index 963cdaecabcb..8e94af513b9f 100644
|
||||
--- a/Documentation/admin-guide/kernel-parameters.txt
|
||||
+++ b/Documentation/admin-guide/kernel-parameters.txt
|
||||
@@ -4162,6 +4162,14 @@
|
||||
nomsi [MSI] If the PCI_MSI kernel config parameter is
|
||||
enabled, this kernel boot option can be used to
|
||||
disable the use of MSI interrupts system-wide.
|
||||
+ pcie_acs_override [PCIE] Override missing PCIe ACS support for
|
||||
+ downstream
|
||||
+ All downstream ports - full ACS capabilities
|
||||
+ multfunction
|
||||
+ All multifunction devices - multifunction ACS subset
|
||||
+ id:nnnn:nnnn
|
||||
+ Specfic device - full ACS capabilities
|
||||
+ Specified as vid:did (vendor/device ID) in hex
|
||||
noioapicquirk [APIC] Disable all boot interrupt quirks.
|
||||
Safety option to keep boot IRQs enabled. This
|
||||
should never be necessary.
|
||||
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
|
||||
index 285acc4aaccc..d6ebef1f30db 100644
|
||||
--- a/drivers/pci/quirks.c
|
||||
+++ b/drivers/pci/quirks.c
|
||||
@@ -3612,6 +3612,107 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
|
||||
dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
|
||||
}
|
||||
|
||||
+static bool acs_on_downstream;
|
||||
+static bool acs_on_multifunction;
|
||||
+
|
||||
+#define NUM_ACS_IDS 16
|
||||
+struct acs_on_id {
|
||||
+ unsigned short vendor;
|
||||
+ unsigned short device;
|
||||
+};
|
||||
+static struct acs_on_id acs_on_ids[NUM_ACS_IDS];
|
||||
+static u8 max_acs_id;
|
||||
+
|
||||
+static __init int pcie_acs_override_setup(char *p)
|
||||
+{
|
||||
+ if (!p)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ while (*p) {
|
||||
+ if (!strncmp(p, "downstream", 10))
|
||||
+ acs_on_downstream = true;
|
||||
+ if (!strncmp(p, "multifunction", 13))
|
||||
+ acs_on_multifunction = true;
|
||||
+ if (!strncmp(p, "id:", 3)) {
|
||||
+ char opt[5];
|
||||
+ int ret;
|
||||
+ long val;
|
||||
+
|
||||
+ if (max_acs_id >= NUM_ACS_IDS - 1) {
|
||||
+ pr_warn("Out of PCIe ACS override slots (%d)\n",
|
||||
+ NUM_ACS_IDS);
|
||||
+ goto next;
|
||||
+ }
|
||||
+
|
||||
+ p += 3;
|
||||
+ snprintf(opt, 5, "%s", p);
|
||||
+ ret = kstrtol(opt, 16, &val);
|
||||
+ if (ret) {
|
||||
+ pr_warn("PCIe ACS ID parse error %d\n", ret);
|
||||
+ goto next;
|
||||
+ }
|
||||
+ acs_on_ids[max_acs_id].vendor = val;
|
||||
+
|
||||
+ p += strcspn(p, ":");
|
||||
+ if (*p != ':') {
|
||||
+ pr_warn("PCIe ACS invalid ID\n");
|
||||
+ goto next;
|
||||
+ }
|
||||
+
|
||||
+ p++;
|
||||
+ snprintf(opt, 5, "%s", p);
|
||||
+ ret = kstrtol(opt, 16, &val);
|
||||
+ if (ret) {
|
||||
+ pr_warn("PCIe ACS ID parse error %d\n", ret);
|
||||
+ goto next;
|
||||
+ }
|
||||
+ acs_on_ids[max_acs_id].device = val;
|
||||
+ max_acs_id++;
|
||||
+ }
|
||||
+next:
|
||||
+ p += strcspn(p, ",");
|
||||
+ if (*p == ',')
|
||||
+ p++;
|
||||
+ }
|
||||
+
|
||||
+ if (acs_on_downstream || acs_on_multifunction || max_acs_id)
|
||||
+ pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+early_param("pcie_acs_override", pcie_acs_override_setup);
|
||||
+
|
||||
+static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ /* Never override ACS for legacy devices or devices with ACS caps */
|
||||
+ if (!pci_is_pcie(dev) ||
|
||||
+ pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS))
|
||||
+ return -ENOTTY;
|
||||
+
|
||||
+ for (i = 0; i < max_acs_id; i++)
|
||||
+ if (acs_on_ids[i].vendor == dev->vendor &&
|
||||
+ acs_on_ids[i].device == dev->device)
|
||||
+ return 1;
|
||||
+
|
||||
+ switch (pci_pcie_type(dev)) {
|
||||
+ case PCI_EXP_TYPE_DOWNSTREAM:
|
||||
+ case PCI_EXP_TYPE_ROOT_PORT:
|
||||
+ if (acs_on_downstream)
|
||||
+ return 1;
|
||||
+ break;
|
||||
+ case PCI_EXP_TYPE_ENDPOINT:
|
||||
+ case PCI_EXP_TYPE_UPSTREAM:
|
||||
+ case PCI_EXP_TYPE_LEG_END:
|
||||
+ case PCI_EXP_TYPE_RC_END:
|
||||
+ if (acs_on_multifunction && dev->multifunction)
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ return -ENOTTY;
|
||||
+}
|
||||
+
|
||||
/*
|
||||
* Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
|
||||
* prevented for those affected devices.
|
||||
@@ -4980,6 +5081,7 @@ static const struct pci_dev_acs_enabled {
|
||||
{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
|
||||
/* Wangxun nics */
|
||||
{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
|
||||
+ { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
@@ -0,0 +1,324 @@
|
||||
From 5aa5769af625c79589fd84b8afc06149c2362218 Mon Sep 17 00:00:00 2001
|
||||
From: Deepak Pandey <Deepak.Pandey@arm.com>
|
||||
Date: Fri, 31 May 2019 16:42:43 +0100
|
||||
Subject: [PATCH] pcie: Add quirk for the Arm Neoverse N1SDP platform
|
||||
|
||||
The Arm N1SDP SoC suffers from some PCIe integration issues, most
|
||||
prominently config space accesses to not existing BDFs being answered
|
||||
with a bus abort, resulting in an SError.
|
||||
To mitigate this, the firmware scans the bus before boot (catching the
|
||||
SErrors) and creates a table with valid BDFs, which acts as a filter for
|
||||
Linux' config space accesses.
|
||||
|
||||
Add code consulting the table as an ACPI PCIe quirk, also register the
|
||||
corresponding device tree based description of the host controller.
|
||||
Also fix the other two minor issues on the way, namely not being fully
|
||||
ECAM compliant and config space accesses being restricted to 32-bit
|
||||
accesses only.
|
||||
|
||||
This allows the Arm Neoverse N1SDP board to boot Linux without crashing
|
||||
and to access *any* devices (there are no platform devices except UART).
|
||||
|
||||
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
|
||||
[Sudipto: extend to cover the CCIX root port as well]
|
||||
Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>
|
||||
[Andre: fix coding style issues, rewrite some parts, add DT support]
|
||||
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
Change-Id: I1d3a4b9bf6b3b883d262e3c4ff1f88a0eb81c1fe
|
||||
Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
|
||||
Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
|
||||
---
|
||||
arch/arm64/configs/defconfig | 1 +
|
||||
drivers/acpi/pci_mcfg.c | 7 +
|
||||
drivers/pci/controller/Kconfig | 11 ++
|
||||
drivers/pci/controller/Makefile | 2 +-
|
||||
drivers/pci/controller/pcie-n1sdp.c | 198 ++++++++++++++++++++++++++++
|
||||
include/linux/pci-ecam.h | 2 +
|
||||
6 files changed, 220 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/pci/controller/pcie-n1sdp.c
|
||||
|
||||
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
|
||||
index bbbc31391a65..973aa3b4d407 100644
|
||||
--- a/arch/arm64/configs/defconfig
|
||||
+++ b/arch/arm64/configs/defconfig
|
||||
@@ -214,6 +214,7 @@ CONFIG_NFC_S3FWRN5_I2C=m
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIEAER=y
|
||||
+CONFIG_PCI_QUIRKS=y
|
||||
CONFIG_PCI_IOV=y
|
||||
CONFIG_PCI_PASID=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
|
||||
index 860014b89b8e..2d4c1c699ffe 100644
|
||||
--- a/drivers/acpi/pci_mcfg.c
|
||||
+++ b/drivers/acpi/pci_mcfg.c
|
||||
@@ -171,6 +171,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
|
||||
ALTRA_ECAM_QUIRK(1, 13),
|
||||
ALTRA_ECAM_QUIRK(1, 14),
|
||||
ALTRA_ECAM_QUIRK(1, 15),
|
||||
+
|
||||
+#define N1SDP_ECAM_MCFG(rev, seg, ops) \
|
||||
+ {"ARMLTD", "ARMN1SDP", rev, seg, MCFG_BUS_ANY, ops }
|
||||
+
|
||||
+ /* N1SDP SoC with v1 PCIe controller */
|
||||
+ N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
|
||||
+ N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
|
||||
#endif /* ARM64 */
|
||||
|
||||
#ifdef CONFIG_LOONGARCH
|
||||
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
|
||||
index bfd9bac37e24..7a65799dded7 100644
|
||||
--- a/drivers/pci/controller/Kconfig
|
||||
+++ b/drivers/pci/controller/Kconfig
|
||||
@@ -50,6 +50,17 @@ config PCI_IXP4XX
|
||||
Say Y here if you want support for the PCI host controller found
|
||||
in the Intel IXP4xx XScale-based network processor SoC.
|
||||
|
||||
+config PCIE_HOST_N1SDP_ECAM
|
||||
+ bool "ARM N1SDP PCIe Controller"
|
||||
+ depends on ARM64
|
||||
+ depends on OF || (ACPI && PCI_QUIRKS)
|
||||
+ select PCI_HOST_COMMON
|
||||
+ default y if ARCH_VEXPRESS
|
||||
+ help
|
||||
+ Say Y here if you want PCIe support for the Arm N1SDP platform.
|
||||
+ The controller is ECAM compliant, but needs a quirk to workaround
|
||||
+ an integration issue.
|
||||
+
|
||||
config PCI_TEGRA
|
||||
bool "NVIDIA Tegra PCIe controller"
|
||||
depends on ARCH_TEGRA || COMPILE_TEST
|
||||
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
|
||||
index 37c8663de7fe..08e5afcf6e86 100644
|
||||
--- a/drivers/pci/controller/Makefile
|
||||
+++ b/drivers/pci/controller/Makefile
|
||||
@@ -39,7 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
|
||||
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
|
||||
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
|
||||
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
|
||||
-
|
||||
+obj-$(CONFIG_PCIE_HOST_N1SDP_ECAM) += pcie-n1sdp.o
|
||||
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
|
||||
obj-y += dwc/
|
||||
obj-y += mobiveil/
|
||||
diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
|
||||
new file mode 100644
|
||||
index 000000000000..408699b9dcb1
|
||||
--- /dev/null
|
||||
+++ b/drivers/pci/controller/pcie-n1sdp.c
|
||||
@@ -0,0 +1,198 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Copyright (C) 2018/2019 ARM Ltd.
|
||||
+ *
|
||||
+ * This quirk is to mask the following issues:
|
||||
+ * - PCIE SLVERR: config space accesses to invalid PCIe BDFs cause a bus
|
||||
+ * error (signalled as an asynchronous SError)
|
||||
+ * - MCFG BDF mapping: the root complex is mapped separately from the device
|
||||
+ * config space
|
||||
+ * - Non 32-bit accesses to config space are not supported.
|
||||
+ *
|
||||
+ * At boot time the SCP board firmware creates a discovery table with
|
||||
+ * the root complex' base address and the valid BDF values, discovered while
|
||||
+ * scanning the config space and catching the SErrors.
|
||||
+ * Linux responds only to the EPs listed in this table, returning NULL
|
||||
+ * for the rest.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/ioport.h>
|
||||
+#include <linux/sizes.h>
|
||||
+#include <linux/of_pci.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/pci-ecam.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/module.h>
|
||||
+
|
||||
+#include "../pci.h"
|
||||
+
|
||||
+/* Platform specific values as hardcoded in the firmware. */
|
||||
+#define AP_NS_SHARED_MEM_BASE 0x06000000
|
||||
+#define MAX_SEGMENTS 2 /* Two PCIe root complexes. */
|
||||
+#define BDF_TABLE_SIZE SZ_16K
|
||||
+
|
||||
+/*
|
||||
+ * Shared memory layout as written by the SCP upon boot time:
|
||||
+ * ----
|
||||
+ * Discover data header --> RC base address
|
||||
+ * \-> BDF Count
|
||||
+ * Discover data --> BDF 0...n
|
||||
+ * ----
|
||||
+ */
|
||||
+struct pcie_discovery_data {
|
||||
+ u32 rc_base_addr;
|
||||
+ u32 nr_bdfs;
|
||||
+ u32 valid_bdfs[0];
|
||||
+} *pcie_discovery_data[MAX_SEGMENTS];
|
||||
+
|
||||
+void __iomem *rc_remapped_addr[MAX_SEGMENTS];
|
||||
+
|
||||
+/*
|
||||
+ * map_bus() is called before we do a config space access for a certain
|
||||
+ * device. We use this to check whether this device is valid, avoiding
|
||||
+ * config space accesses which would result in an SError otherwise.
|
||||
+ */
|
||||
+static void __iomem *pci_n1sdp_map_bus(struct pci_bus *bus, unsigned int devfn,
|
||||
+ int where)
|
||||
+{
|
||||
+ struct pci_config_window *cfg = bus->sysdata;
|
||||
+ unsigned int devfn_shift = cfg->ops->bus_shift - 8;
|
||||
+ unsigned int busn = bus->number;
|
||||
+ unsigned int segment = bus->domain_nr;
|
||||
+ unsigned int bdf_addr;
|
||||
+ unsigned int table_count, i;
|
||||
+ struct pci_dev *dev;
|
||||
+
|
||||
+ if (segment >= MAX_SEGMENTS ||
|
||||
+ busn < cfg->busr.start || busn > cfg->busr.end)
|
||||
+ return NULL;
|
||||
+
|
||||
+ /* The PCIe root complex has a separate config space mapping. */
|
||||
+ if (busn == 0 && devfn == 0)
|
||||
+ return rc_remapped_addr[segment] + where;
|
||||
+
|
||||
+ dev = pci_get_domain_bus_and_slot(segment, busn, devfn);
|
||||
+ if (dev && dev->is_virtfn)
|
||||
+ return pci_ecam_map_bus(bus, devfn, where);
|
||||
+
|
||||
+ /* Accesses beyond the vendor ID always go to existing devices. */
|
||||
+ if (where > 0)
|
||||
+ return pci_ecam_map_bus(bus, devfn, where);
|
||||
+
|
||||
+ busn -= cfg->busr.start;
|
||||
+ bdf_addr = (busn << cfg->ops->bus_shift) + (devfn << devfn_shift);
|
||||
+ table_count = pcie_discovery_data[segment]->nr_bdfs;
|
||||
+ for (i = 0; i < table_count; i++) {
|
||||
+ if (bdf_addr == pcie_discovery_data[segment]->valid_bdfs[i])
|
||||
+ return pci_ecam_map_bus(bus, devfn, where);
|
||||
+ }
|
||||
+
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
|
||||
+{
|
||||
+ phys_addr_t table_base;
|
||||
+ struct device *dev = cfg->parent;
|
||||
+ struct pcie_discovery_data *shared_data;
|
||||
+ size_t bdfs_size;
|
||||
+
|
||||
+ if (segment >= MAX_SEGMENTS)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
|
||||
+
|
||||
+ if (!request_mem_region(table_base, BDF_TABLE_SIZE,
|
||||
+ "PCIe valid BDFs")) {
|
||||
+ dev_err(dev, "PCIe BDF shared region request failed\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ shared_data = devm_ioremap(dev,
|
||||
+ table_base, BDF_TABLE_SIZE);
|
||||
+ if (!shared_data)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ /* Copy the valid BDFs structure to allocated normal memory. */
|
||||
+ bdfs_size = sizeof(struct pcie_discovery_data) +
|
||||
+ sizeof(u32) * shared_data->nr_bdfs;
|
||||
+ pcie_discovery_data[segment] = devm_kmalloc(dev, bdfs_size, GFP_KERNEL);
|
||||
+ if (!pcie_discovery_data[segment])
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
|
||||
+
|
||||
+ rc_remapped_addr[segment] = devm_ioremap(dev,
|
||||
+ shared_data->rc_base_addr,
|
||||
+ PCI_CFG_SPACE_EXP_SIZE);
|
||||
+ if (!rc_remapped_addr[segment]) {
|
||||
+ dev_err(dev, "Cannot remap root port base\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ devm_iounmap(dev, shared_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/* Called for ACPI segment 0, and for all segments when using DT. */
|
||||
+static int pci_n1sdp_pcie_init(struct pci_config_window *cfg)
|
||||
+{
|
||||
+ struct platform_device *pdev = to_platform_device(cfg->parent);
|
||||
+ int segment = 0;
|
||||
+
|
||||
+ if (pdev->dev.of_node)
|
||||
+ segment = of_get_pci_domain_nr(pdev->dev.of_node);
|
||||
+ if (segment < 0 || segment > MAX_SEGMENTS) {
|
||||
+ dev_err(&pdev->dev, "N1SDP PCI controllers require linux,pci-domain property\n");
|
||||
+ dev_err(&pdev->dev, "Or invalid segment number, must be smaller than %d\n",
|
||||
+ MAX_SEGMENTS);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return pci_n1sdp_init(cfg, segment);
|
||||
+}
|
||||
+
|
||||
+/* Called for ACPI segment 1. */
|
||||
+static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
|
||||
+{
|
||||
+ return pci_n1sdp_init(cfg, 1);
|
||||
+}
|
||||
+
|
||||
+const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
|
||||
+ .bus_shift = 20,
|
||||
+ .init = pci_n1sdp_pcie_init,
|
||||
+ .pci_ops = {
|
||||
+ .map_bus = pci_n1sdp_map_bus,
|
||||
+ .read = pci_generic_config_read32,
|
||||
+ .write = pci_generic_config_write32,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
|
||||
+ .bus_shift = 20,
|
||||
+ .init = pci_n1sdp_ccix_init,
|
||||
+ .pci_ops = {
|
||||
+ .map_bus = pci_n1sdp_map_bus,
|
||||
+ .read = pci_generic_config_read32,
|
||||
+ .write = pci_generic_config_write32,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id n1sdp_pcie_of_match[] = {
|
||||
+ { .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, n1sdp_pcie_of_match);
|
||||
+
|
||||
+static struct platform_driver n1sdp_pcie_driver = {
|
||||
+ .driver = {
|
||||
+ .name = KBUILD_MODNAME,
|
||||
+ .of_match_table = n1sdp_pcie_of_match,
|
||||
+ .suppress_bind_attrs = true,
|
||||
+ },
|
||||
+ .probe = pci_host_common_probe,
|
||||
+};
|
||||
+builtin_platform_driver(n1sdp_pcie_driver);
|
||||
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
|
||||
index 6b1301e2498e..b3cf3adeab28 100644
|
||||
--- a/include/linux/pci-ecam.h
|
||||
+++ b/include/linux/pci-ecam.h
|
||||
@@ -88,6 +88,8 @@ extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x
|
||||
extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
|
||||
extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
|
||||
extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
|
||||
+extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
|
||||
+extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
|
||||
@@ -0,0 +1,136 @@
|
||||
From b59e0d6c6035db80fc9044df0333f96ede53ad7a Mon Sep 17 00:00:00 2001
|
||||
From: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
|
||||
Date: Wed, 9 Feb 2022 20:37:43 +0530
|
||||
Subject: [PATCH] n1sdp: pcie: add quirk support enabling remote chip PCIe
|
||||
|
||||
Base address mapping for remote chip Root PCIe ECAM space.
|
||||
|
||||
When two N1SDP boards are coupled via the CCIX connection, the PCI host
|
||||
complex of the remote board appears as PCIe segment 2 on the primary board.
|
||||
The resources of the secondary board, including the host complex, are
|
||||
mapped at offset 0x40000000000 into the address space of the primary
|
||||
board, so take that into account when accessing the remote PCIe segment.
|
||||
|
||||
Change-Id: I0e8d1eb119aef6444b9df854a39b24441c12195a
|
||||
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
|
||||
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
|
||||
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
||||
Signed-off-by: sahil <sahil@arm.com>
|
||||
|
||||
Upstream-Status: Inappropriate [will not be submitted as its an hack required to fix the hardware issue]
|
||||
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
|
||||
---
|
||||
drivers/acpi/pci_mcfg.c | 1 +
|
||||
drivers/pci/controller/pcie-n1sdp.c | 32 +++++++++++++++++++++++++----
|
||||
include/linux/pci-ecam.h | 1 +
|
||||
3 files changed, 30 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
|
||||
index 2d4c1c699ffe..27f1e9a45c17 100644
|
||||
--- a/drivers/acpi/pci_mcfg.c
|
||||
+++ b/drivers/acpi/pci_mcfg.c
|
||||
@@ -178,6 +178,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
|
||||
/* N1SDP SoC with v1 PCIe controller */
|
||||
N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
|
||||
N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
|
||||
+ N1SDP_ECAM_MCFG(0x20181101, 2, &pci_n1sdp_remote_pcie_ecam_ops),
|
||||
#endif /* ARM64 */
|
||||
|
||||
#ifdef CONFIG_LOONGARCH
|
||||
diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
|
||||
index 408699b9dcb1..b3b02417fd7d 100644
|
||||
--- a/drivers/pci/controller/pcie-n1sdp.c
|
||||
+++ b/drivers/pci/controller/pcie-n1sdp.c
|
||||
@@ -30,8 +30,10 @@
|
||||
|
||||
/* Platform specific values as hardcoded in the firmware. */
|
||||
#define AP_NS_SHARED_MEM_BASE 0x06000000
|
||||
-#define MAX_SEGMENTS 2 /* Two PCIe root complexes. */
|
||||
+/* Two PCIe root complexes in One Chip + One PCIe RC in Remote Chip */
|
||||
+#define MAX_SEGMENTS 3
|
||||
#define BDF_TABLE_SIZE SZ_16K
|
||||
+#define REMOTE_CHIP_ADDR_OFFSET 0x40000000000
|
||||
|
||||
/*
|
||||
* Shared memory layout as written by the SCP upon boot time:
|
||||
@@ -97,12 +99,17 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
|
||||
phys_addr_t table_base;
|
||||
struct device *dev = cfg->parent;
|
||||
struct pcie_discovery_data *shared_data;
|
||||
- size_t bdfs_size;
|
||||
+ size_t bdfs_size, rc_base_addr = 0;
|
||||
|
||||
if (segment >= MAX_SEGMENTS)
|
||||
return -ENODEV;
|
||||
|
||||
- table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
|
||||
+ if (segment > 1) {
|
||||
+ rc_base_addr = REMOTE_CHIP_ADDR_OFFSET;
|
||||
+ table_base = AP_NS_SHARED_MEM_BASE + REMOTE_CHIP_ADDR_OFFSET;
|
||||
+ } else {
|
||||
+ table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
|
||||
+ }
|
||||
|
||||
if (!request_mem_region(table_base, BDF_TABLE_SIZE,
|
||||
"PCIe valid BDFs")) {
|
||||
@@ -114,6 +121,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
|
||||
table_base, BDF_TABLE_SIZE);
|
||||
if (!shared_data)
|
||||
return -ENOMEM;
|
||||
+ rc_base_addr += shared_data->rc_base_addr;
|
||||
|
||||
/* Copy the valid BDFs structure to allocated normal memory. */
|
||||
bdfs_size = sizeof(struct pcie_discovery_data) +
|
||||
@@ -125,7 +133,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
|
||||
memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
|
||||
|
||||
rc_remapped_addr[segment] = devm_ioremap(dev,
|
||||
- shared_data->rc_base_addr,
|
||||
+ rc_base_addr,
|
||||
PCI_CFG_SPACE_EXP_SIZE);
|
||||
if (!rc_remapped_addr[segment]) {
|
||||
dev_err(dev, "Cannot remap root port base\n");
|
||||
@@ -161,6 +169,12 @@ static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
|
||||
return pci_n1sdp_init(cfg, 1);
|
||||
}
|
||||
|
||||
+/* Called for ACPI segment 2. */
|
||||
+static int pci_n1sdp_remote_pcie_init(struct pci_config_window *cfg)
|
||||
+{
|
||||
+ return pci_n1sdp_init(cfg, 2);
|
||||
+}
|
||||
+
|
||||
const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
|
||||
.bus_shift = 20,
|
||||
.init = pci_n1sdp_pcie_init,
|
||||
@@ -181,6 +195,16 @@ const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
|
||||
}
|
||||
};
|
||||
|
||||
+const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops = {
|
||||
+ .bus_shift = 20,
|
||||
+ .init = pci_n1sdp_remote_pcie_init,
|
||||
+ .pci_ops = {
|
||||
+ .map_bus = pci_n1sdp_map_bus,
|
||||
+ .read = pci_generic_config_read32,
|
||||
+ .write = pci_generic_config_write32,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id n1sdp_pcie_of_match[] = {
|
||||
{ .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
|
||||
{ },
|
||||
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
|
||||
index b3cf3adeab28..d4316795c00d 100644
|
||||
--- a/include/linux/pci-ecam.h
|
||||
+++ b/include/linux/pci-ecam.h
|
||||
@@ -90,6 +90,7 @@ extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
|
||||
extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
|
||||
extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
|
||||
extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
|
||||
+extern const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops; /* Arm N1SDP PCIe */
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
|
||||
@@ -0,0 +1,33 @@
|
||||
From ff02f77788f8c01e9d675912c063e89415804b7d Mon Sep 17 00:00:00 2001
|
||||
From: Andre Przywara <andre.przywara@arm.com>
|
||||
Date: Fri, 17 May 2019 17:39:27 +0100
|
||||
Subject: [PATCH] arm64: kpti: Whitelist early Arm Neoverse N1 revisions
|
||||
|
||||
Early revisions (r1p0) of the Neoverse N1 core did not feature the
|
||||
CSV3 field in ID_AA64PFR0_EL1 to advertise they are not affected by
|
||||
the Spectre variant 3 (aka Meltdown) vulnerability.
|
||||
|
||||
Add this particular revision to the whitelist to avoid enabling KPTI.
|
||||
|
||||
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
||||
Change-Id: I78df055a3e674aefd195d41cc6dc4ee08b0af099
|
||||
Upstream-Status: Inappropriate
|
||||
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
|
||||
---
|
||||
arch/arm64/kernel/cpufeature.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
|
||||
index b3f37e2209ad..b74210f38cd8 100644
|
||||
--- a/arch/arm64/kernel/cpufeature.c
|
||||
+++ b/arch/arm64/kernel/cpufeature.c
|
||||
@@ -1646,6 +1646,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
|
||||
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
|
||||
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
|
||||
MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
|
||||
+ MIDR_REV(MIDR_NEOVERSE_N1, 1, 0), /* missing CSV3 */
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
char const *str = "kpti command line option";
|
||||
@@ -0,0 +1,57 @@
|
||||
From afdd5ae3eeb44381f906b6227422373d4af2811d Mon Sep 17 00:00:00 2001
|
||||
From: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Date: Wed, 21 Sep 2022 15:54:14 +0100
|
||||
Subject: [PATCH] arm64: defconfig: disable config options that does not apply
|
||||
anymore
|
||||
|
||||
Following config options should be not set to be more accurate and
|
||||
works with build system like yocto
|
||||
CONFIG_BT_HCIBTUSB
|
||||
CONFIG_BT_HCIBTUSB_MTK
|
||||
CONFIG_BT_HCIUART_MRVL
|
||||
CONFIG_BT_MRVL
|
||||
CONFIG_BT_MRVL_SDIO
|
||||
CONFIG_BT_QCOMSMD
|
||||
CONFIG_BT_NXPUART
|
||||
|
||||
Upstream-Status: Pending [not submitted upstream yet]
|
||||
Signed-off-by: Adam Johnston <adam.johnston@arm.com>
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
|
||||
Signed-off-by: Anusmita Dutta Mazumder <anusmita.duttamazumder@arm.com>
|
||||
---
|
||||
arch/arm64/configs/defconfig | 14 +++++++-------
|
||||
1 file changed, 7 insertions(+), 7 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
|
||||
index d2b5208eb55d..b3028113de25 100644
|
||||
--- a/arch/arm64/configs/defconfig
|
||||
+++ b/arch/arm64/configs/defconfig
|
||||
@@ -186,17 +186,17 @@ CONFIG_BT_HIDP=m
|
||||
# CONFIG_BT_LE is not set
|
||||
CONFIG_BT_LEDS=y
|
||||
# CONFIG_BT_DEBUGFS is not set
|
||||
-CONFIG_BT_HCIBTUSB=m
|
||||
-CONFIG_BT_HCIBTUSB_MTK=y
|
||||
+# CONFIG_BT_HCIBTUSB is not set
|
||||
+# CONFIG_BT_HCIBTUSB_MTK is not set
|
||||
CONFIG_BT_HCIUART=m
|
||||
CONFIG_BT_HCIUART_LL=y
|
||||
CONFIG_BT_HCIUART_BCM=y
|
||||
CONFIG_BT_HCIUART_QCA=y
|
||||
-CONFIG_BT_HCIUART_MRVL=y
|
||||
-CONFIG_BT_MRVL=m
|
||||
-CONFIG_BT_MRVL_SDIO=m
|
||||
-CONFIG_BT_QCOMSMD=m
|
||||
-CONFIG_BT_NXPUART=m
|
||||
+# CONFIG_BT_HCIUART_MRVL is not set
|
||||
+# CONFIG_BT_MRVL is not set
|
||||
+# CONFIG_BT_MRVL_SDIO is not set
|
||||
+# CONFIG_BT_QCOMSMD is not set
|
||||
+# CONFIG_BT_NXPUART is not set
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_LEDS=y
|
||||
--
|
||||
2.38.1
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
# Enable NVMe flash storage support
|
||||
CONFIG_NVME_CORE=y
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
@@ -0,0 +1,3 @@
|
||||
# Enable Realtek Gigabit Ethernet adapter
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_R8169=y
|
||||
@@ -0,0 +1,2 @@
|
||||
# PHY_TEGRA_XUSB sets this to y, but its set as m in defconfig
|
||||
CONFIG_USB_CONN_GPIO=y
|
||||
@@ -0,0 +1,2 @@
|
||||
# CONFIG_USB_XHCI_PCI is not set
|
||||
# CONFIG_USB_XHCI_PCI_RENESAS is not set
|
||||
Reference in New Issue
Block a user