Complete Yocto mirror with license table for TQMa6UL (2038-compliance)
- 264 license table entries with exact download URLs (224/264 resolved) - Complete sources/ directory with all BitBake recipes - Build configuration: tqma6ul-multi-mba6ulx, spaetzle (musl) - Full traceability for Softwarefreigabeantrag - GCC 13.4.0, Linux 6.6.102, U-Boot 2023.04, musl 1.2.4 - License distribution: GPL-2.0 (24), MIT (23), GPL-2.0+ (18), BSD-3 (16)
This commit is contained in:
Siggi (OpenClaw Agent)
@@ -0,0 +1,32 @@
|
||||
From d6ee50f581b43b16733b8731369b071d609d5048 Mon Sep 17 00:00:00 2001
|
||||
From: Emekcan Aras <emekcan.aras@arm.com>
|
||||
Date: Thu, 31 Aug 2023 10:51:54 +0100
|
||||
Subject: [PATCH] Handle logging syscall
|
||||
|
||||
Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
|
||||
Upstream-Status: Pending [upstreamed differently in 280b6a3]
|
||||
---
|
||||
core/arch/arm/kernel/spmc_sp_handler.c | 7 ++++++-
|
||||
1 file changed, 6 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/core/arch/arm/kernel/spmc_sp_handler.c b/core/arch/arm/kernel/spmc_sp_handler.c
|
||||
index 1f218a0df..0676e8898 100644
|
||||
--- a/core/arch/arm/kernel/spmc_sp_handler.c
|
||||
+++ b/core/arch/arm/kernel/spmc_sp_handler.c
|
||||
@@ -1276,7 +1276,12 @@ void spmc_sp_msg_handler(struct thread_smc_args *args,
|
||||
handle_console_log(args);
|
||||
sp_enter(args, caller_sp);
|
||||
break;
|
||||
-
|
||||
+ case 0xdeadbeef:
|
||||
+ ts_push_current_session(&caller_sp->ts_sess);
|
||||
+ IMSG("%s", (char *)args->a1);
|
||||
+ ts_pop_current_session();
|
||||
+ sp_enter(args, caller_sp);
|
||||
+ break;
|
||||
default:
|
||||
EMSG("Unhandled FFA function ID %#"PRIx32,
|
||||
(uint32_t)args->a0);
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
From 1410d9e9c3e73b1319b98be67ad00c7630c4cb2e Mon Sep 17 00:00:00 2001
|
||||
From: Emekcan Aras <Emekcan.Aras@arm.com>
|
||||
Date: Wed, 3 Apr 2024 16:05:07 +0100
|
||||
Subject: [PATCH] increase tzdram size
|
||||
|
||||
Upstream-Status: Pending
|
||||
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
|
||||
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
|
||||
---
|
||||
core/arch/arm/plat-corstone1000/conf.mk | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/core/arch/arm/plat-corstone1000/conf.mk b/core/arch/arm/plat-corstone1000/conf.mk
|
||||
index 98347b143..c2dd71f05 100644
|
||||
--- a/core/arch/arm/plat-corstone1000/conf.mk
|
||||
+++ b/core/arch/arm/plat-corstone1000/conf.mk
|
||||
@@ -34,7 +34,7 @@ CFG_TEE_CORE_NB_CORE ?= 1
|
||||
CFG_TZDRAM_START ?= 0x02002000
|
||||
|
||||
# TEE_RAM (OPTEE kernel + DATA) + TA_RAM = 3MB
|
||||
-CFG_TZDRAM_SIZE ?= 0x300000
|
||||
+CFG_TZDRAM_SIZE ?= 0x340000
|
||||
CFG_SHMEM_START ?= 0x86000000
|
||||
CFG_SHMEM_SIZE ?= 0x00200000
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@@ -0,0 +1,237 @@
|
||||
From 56f2afcd10e8404a3c4efed6277a005fc4099e48 Mon Sep 17 00:00:00 2001
|
||||
From: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Date: Thu, 30 Jun 2022 18:36:26 +0100
|
||||
Subject: [PATCH] plat-n1sdp: add N1SDP platform support
|
||||
|
||||
Upstream-Status: Pending [Not submitted to upstream yet]
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
|
||||
These changes are to add N1SDP platform to optee-os
|
||||
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
|
||||
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
|
||||
---
|
||||
core/arch/arm/plat-n1sdp/conf.mk | 41 +++++++++++++++++
|
||||
core/arch/arm/plat-n1sdp/main.c | 53 ++++++++++++++++++++++
|
||||
core/arch/arm/plat-n1sdp/n1sdp_core_pos.S | 32 +++++++++++++
|
||||
core/arch/arm/plat-n1sdp/platform_config.h | 49 ++++++++++++++++++++
|
||||
core/arch/arm/plat-n1sdp/sub.mk | 3 ++
|
||||
5 files changed, 178 insertions(+)
|
||||
create mode 100644 core/arch/arm/plat-n1sdp/conf.mk
|
||||
create mode 100644 core/arch/arm/plat-n1sdp/main.c
|
||||
create mode 100644 core/arch/arm/plat-n1sdp/n1sdp_core_pos.S
|
||||
create mode 100644 core/arch/arm/plat-n1sdp/platform_config.h
|
||||
create mode 100644 core/arch/arm/plat-n1sdp/sub.mk
|
||||
|
||||
diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk
|
||||
new file mode 100644
|
||||
index 000000000..3dc79fe20
|
||||
--- /dev/null
|
||||
+++ b/core/arch/arm/plat-n1sdp/conf.mk
|
||||
@@ -0,0 +1,41 @@
|
||||
+include core/arch/arm/cpu/cortex-armv8-0.mk
|
||||
+
|
||||
+CFG_DEBUG_INFO = y
|
||||
+CFG_TEE_CORE_LOG_LEVEL = 4
|
||||
+
|
||||
+# Workaround 808870: Unconditional VLDM instructions might cause an
|
||||
+# alignment fault even though the address is aligned
|
||||
+# Either hard float must be disabled for AArch32 or strict alignment checks
|
||||
+# must be disabled
|
||||
+ifeq ($(CFG_SCTLR_ALIGNMENT_CHECK),y)
|
||||
+$(call force,CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT,y)
|
||||
+else
|
||||
+$(call force,CFG_SCTLR_ALIGNMENT_CHECK,n)
|
||||
+endif
|
||||
+
|
||||
+CFG_ARM64_core ?= y
|
||||
+
|
||||
+CFG_ARM_GICV3 = y
|
||||
+
|
||||
+# ARM debugger needs this
|
||||
+platform-cflags-debug-info = -gdwarf-4
|
||||
+platform-aflags-debug-info = -gdwarf-4
|
||||
+
|
||||
+CFG_CORE_SEL1_SPMC = y
|
||||
+CFG_WITH_ARM_TRUSTED_FW = y
|
||||
+
|
||||
+$(call force,CFG_GIC,y)
|
||||
+$(call force,CFG_PL011,y)
|
||||
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
|
||||
+
|
||||
+CFG_CORE_HEAP_SIZE = 0x32000 # 200kb
|
||||
+
|
||||
+CFG_TEE_CORE_NB_CORE = 4
|
||||
+CFG_TZDRAM_START ?= 0xDE000000
|
||||
+CFG_TZDRAM_SIZE ?= 0x02000000
|
||||
+
|
||||
+CFG_SHMEM_START ?= 0x83000000
|
||||
+CFG_SHMEM_SIZE ?= 0x00210000
|
||||
+# DRAM1 is defined above 4G
|
||||
+$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
|
||||
+$(call force,CFG_CORE_ARM64_PA_BITS,36)
|
||||
diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
|
||||
new file mode 100644
|
||||
index 000000000..38212d84c
|
||||
--- /dev/null
|
||||
+++ b/core/arch/arm/plat-n1sdp/main.c
|
||||
@@ -0,0 +1,53 @@
|
||||
+// SPDX-License-Identifier: BSD-2-Clause
|
||||
+/*
|
||||
+ * Copyright (c) 2022, Arm Limited.
|
||||
+ */
|
||||
+
|
||||
+#include <arm.h>
|
||||
+#include <console.h>
|
||||
+#include <drivers/gic.h>
|
||||
+#include <drivers/pl011.h>
|
||||
+#include <drivers/tzc400.h>
|
||||
+#include <initcall.h>
|
||||
+#include <keep.h>
|
||||
+#include <kernel/boot.h>
|
||||
+#include <kernel/interrupt.h>
|
||||
+#include <kernel/misc.h>
|
||||
+#include <kernel/notif.h>
|
||||
+#include <kernel/panic.h>
|
||||
+#include <kernel/spinlock.h>
|
||||
+#include <kernel/tee_time.h>
|
||||
+#include <mm/core_memprot.h>
|
||||
+#include <mm/core_mmu.h>
|
||||
+#include <platform_config.h>
|
||||
+#include <sm/psci.h>
|
||||
+#include <stdint.h>
|
||||
+#include <string.h>
|
||||
+#include <trace.h>
|
||||
+
|
||||
+static struct pl011_data console_data __nex_bss;
|
||||
+
|
||||
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
|
||||
+
|
||||
+register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
||||
+
|
||||
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
|
||||
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
|
||||
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
|
||||
+
|
||||
+void main_init_gic(void)
|
||||
+{
|
||||
+ gic_init(GICC_BASE, GICD_BASE);
|
||||
+}
|
||||
+
|
||||
+void main_secondary_init_gic(void)
|
||||
+{
|
||||
+ gic_init_per_cpu();
|
||||
+}
|
||||
+
|
||||
+void console_init(void)
|
||||
+{
|
||||
+ pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
|
||||
+ CONSOLE_BAUDRATE);
|
||||
+ register_serial_console(&console_data.chip);
|
||||
+}
|
||||
diff --git a/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S
|
||||
new file mode 100644
|
||||
index 000000000..439d4e675
|
||||
--- /dev/null
|
||||
+++ b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
+/*
|
||||
+ * Copyright (c) 2022, Arm Limited
|
||||
+ */
|
||||
+
|
||||
+#include <asm.S>
|
||||
+#include <arm.h>
|
||||
+#include "platform_config.h"
|
||||
+
|
||||
+FUNC get_core_pos_mpidr , :
|
||||
+ mov x4, x0
|
||||
+
|
||||
+ /*
|
||||
+ * The MT bit in MPIDR is always set for n1sdp and the
|
||||
+ * affinity level 0 corresponds to thread affinity level.
|
||||
+ */
|
||||
+
|
||||
+ /* Extract individual affinity fields from MPIDR */
|
||||
+ ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
+ ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
+ ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
+ ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
+
|
||||
+ /* Compute linear position */
|
||||
+ mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
|
||||
+ madd x2, x3, x4, x2
|
||||
+ mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
|
||||
+ madd x1, x2, x4, x1
|
||||
+ mov x4, #N1SDP_MAX_PE_PER_CPU
|
||||
+ madd x0, x1, x4, x0
|
||||
+ ret
|
||||
+END_FUNC get_core_pos_mpidr
|
||||
diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
new file mode 100644
|
||||
index 000000000..81b994091
|
||||
--- /dev/null
|
||||
+++ b/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
@@ -0,0 +1,49 @@
|
||||
+/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
+/*
|
||||
+ * Copyright (c) 2022, Arm Limited
|
||||
+ */
|
||||
+
|
||||
+#ifndef PLATFORM_CONFIG_H
|
||||
+#define PLATFORM_CONFIG_H
|
||||
+
|
||||
+#include <mm/generic_ram_layout.h>
|
||||
+#include <stdint.h>
|
||||
+
|
||||
+/* Make stacks aligned to data cache line length */
|
||||
+#define STACK_ALIGNMENT 64
|
||||
+
|
||||
+ /* N1SDP topology related constants */
|
||||
+#define N1SDP_MAX_CPUS_PER_CLUSTER U(2)
|
||||
+#define PLAT_ARM_CLUSTER_COUNT U(2)
|
||||
+#define PLAT_N1SDP_CHIP_COUNT U(2)
|
||||
+#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2)
|
||||
+#define N1SDP_MAX_PE_PER_CPU U(1)
|
||||
+
|
||||
+#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \
|
||||
+ PLAT_ARM_CLUSTER_COUNT * \
|
||||
+ N1SDP_MAX_CPUS_PER_CLUSTER * \
|
||||
+ N1SDP_MAX_PE_PER_CPU)
|
||||
+
|
||||
+#define GIC_BASE 0x2c010000
|
||||
+
|
||||
+#define UART1_BASE 0x1C0A0000
|
||||
+#define UART1_CLK_IN_HZ 24000000 /*24MHz*/
|
||||
+
|
||||
+#define CONSOLE_UART_BASE UART1_BASE
|
||||
+#define CONSOLE_UART_CLK_IN_HZ UART1_CLK_IN_HZ
|
||||
+
|
||||
+#define DRAM0_BASE 0x80000000
|
||||
+#define DRAM0_SIZE 0x80000000
|
||||
+
|
||||
+#define GICD_BASE 0x30000000
|
||||
+#define GICC_BASE 0x2C000000
|
||||
+#define GICR_BASE 0x300C0000
|
||||
+
|
||||
+#ifndef UART_BAUDRATE
|
||||
+#define UART_BAUDRATE 115200
|
||||
+#endif
|
||||
+#ifndef CONSOLE_BAUDRATE
|
||||
+#define CONSOLE_BAUDRATE UART_BAUDRATE
|
||||
+#endif
|
||||
+
|
||||
+#endif /*PLATFORM_CONFIG_H*/
|
||||
diff --git a/core/arch/arm/plat-n1sdp/sub.mk b/core/arch/arm/plat-n1sdp/sub.mk
|
||||
new file mode 100644
|
||||
index 000000000..a0b49da14
|
||||
--- /dev/null
|
||||
+++ b/core/arch/arm/plat-n1sdp/sub.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
+global-incdirs-y += .
|
||||
+srcs-y += main.c
|
||||
+srcs-y += n1sdp_core_pos.S
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@@ -0,0 +1,32 @@
|
||||
Upstream-Status: Pending [upstreamed differently in 280b6a3]
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
|
||||
From b3fde6c2e1a950214f760ab9f194f3a6572292a8 Mon Sep 17 00:00:00 2001
|
||||
From: Balint Dobszay <balint.dobszay@arm.com>
|
||||
Date: Fri, 15 Jul 2022 13:45:54 +0200
|
||||
Subject: [PATCH] Handle logging syscall
|
||||
|
||||
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
|
||||
Change-Id: Ib8151cc9c66aea8bcc8fe8b1ecdc3f9f9c5f14e4
|
||||
|
||||
|
||||
diff --git a/core/arch/arm/kernel/spmc_sp_handler.c b/core/arch/arm/kernel/spmc_sp_handler.c
|
||||
index e0fa0aa6..c7a45387 100644
|
||||
--- a/core/arch/arm/kernel/spmc_sp_handler.c
|
||||
+++ b/core/arch/arm/kernel/spmc_sp_handler.c
|
||||
@@ -1277,6 +1277,13 @@ void spmc_sp_msg_handler(struct thread_smc_args *args,
|
||||
sp_enter(args, caller_sp);
|
||||
break;
|
||||
|
||||
+ case 0xdeadbeef:
|
||||
+ ts_push_current_session(&caller_sp->ts_sess);
|
||||
+ IMSG("%s", (char *)args->a1);
|
||||
+ ts_pop_current_session();
|
||||
+ sp_enter(args, caller_sp);
|
||||
+ break;
|
||||
+
|
||||
default:
|
||||
EMSG("Unhandled FFA function ID %#"PRIx32,
|
||||
(uint32_t)args->a0);
|
||||
--
|
||||
2.17.1
|
||||
@@ -0,0 +1,52 @@
|
||||
Upstream-Status: Pending [Not submitted to upstream yet]
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
|
||||
From 2eb1da30564428551ca687d456d848129105abac Mon Sep 17 00:00:00 2001
|
||||
From: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
Date: Tue, 25 Oct 2022 19:08:49 +0100
|
||||
Subject: [PATCH] plat-n1sdp: register DRAM1 to optee-os
|
||||
|
||||
N1SDP supports two DRAM's. This change is to add 2nd DRAM
|
||||
starting at 0x8080000000 address.
|
||||
|
||||
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
|
||||
|
||||
diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk
|
||||
index 06b4975a..5374e406 100644
|
||||
--- a/core/arch/arm/plat-n1sdp/conf.mk
|
||||
+++ b/core/arch/arm/plat-n1sdp/conf.mk
|
||||
@@ -38,4 +38,4 @@ CFG_SHMEM_START ?= 0x83000000
|
||||
CFG_SHMEM_SIZE ?= 0x00210000
|
||||
# DRAM1 is defined above 4G
|
||||
$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
|
||||
-$(call force,CFG_CORE_ARM64_PA_BITS,36)
|
||||
+$(call force,CFG_CORE_ARM64_PA_BITS,42)
|
||||
diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
|
||||
index cfb7f19b..bb951ce6 100644
|
||||
--- a/core/arch/arm/plat-n1sdp/main.c
|
||||
+++ b/core/arch/arm/plat-n1sdp/main.c
|
||||
@@ -33,6 +33,7 @@ static struct pl011_data console_data __nex_bss;
|
||||
register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
|
||||
|
||||
register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
||||
+register_ddr(DRAM1_BASE, DRAM1_SIZE);
|
||||
|
||||
register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
|
||||
register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
|
||||
diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
index 81b99409..bf0a3c83 100644
|
||||
--- a/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
+++ b/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
@@ -35,6 +35,9 @@
|
||||
#define DRAM0_BASE 0x80000000
|
||||
#define DRAM0_SIZE 0x80000000
|
||||
|
||||
+#define DRAM1_BASE 0x8080000000ULL
|
||||
+#define DRAM1_SIZE 0x80000000ULL
|
||||
+
|
||||
#define GICD_BASE 0x30000000
|
||||
#define GICC_BASE 0x2C000000
|
||||
#define GICR_BASE 0x300C0000
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
Upstream-Status: Pending [Not submitted to upstream yet]
|
||||
Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
|
||||
|
||||
From 1a9aeedda58228893add545e49d2d6cd4c316b4f Mon Sep 17 00:00:00 2001
|
||||
From: Emekcan <emekcan.aras@arm.com>
|
||||
Date: Tue, 13 Dec 2022 13:45:06 +0000
|
||||
Subject: [PATCH] plat-n1sdp: add external device tree base and size
|
||||
|
||||
Adds external device tree address and size. It also
|
||||
register this physical memory so optee can read the device tree.
|
||||
---
|
||||
core/arch/arm/plat-n1sdp/main.c | 1 +
|
||||
core/arch/arm/plat-n1sdp/platform_config.h | 3 +++
|
||||
2 files changed, 4 insertions(+)
|
||||
|
||||
diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
|
||||
index bb951ce6b..ab76f60c6 100644
|
||||
--- a/core/arch/arm/plat-n1sdp/main.c
|
||||
+++ b/core/arch/arm/plat-n1sdp/main.c
|
||||
@@ -31,6 +31,7 @@ static struct gic_data gic_data __nex_bss;
|
||||
static struct pl011_data console_data __nex_bss;
|
||||
|
||||
register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
|
||||
+register_phys_mem_pgdir(MEM_AREA_EXT_DT, EXT_DT_BASE, EXT_DT_SIZE);
|
||||
|
||||
register_ddr(DRAM0_BASE, DRAM0_SIZE);
|
||||
register_ddr(DRAM1_BASE, DRAM1_SIZE);
|
||||
diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
index bf0a3c834..8741a2503 100644
|
||||
--- a/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
+++ b/core/arch/arm/plat-n1sdp/platform_config.h
|
||||
@@ -42,6 +42,9 @@
|
||||
#define GICC_BASE 0x2C000000
|
||||
#define GICR_BASE 0x300C0000
|
||||
|
||||
+#define EXT_DT_BASE 0x04001600
|
||||
+#define EXT_DT_SIZE 0x200
|
||||
+
|
||||
#ifndef UART_BAUDRATE
|
||||
#define UART_BAUDRATE 115200
|
||||
#endif
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
{
|
||||
"op-tee" : {
|
||||
"image": "tee-pager_v2.bin",
|
||||
"pm": "optee_sp_manifest.dts"
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user