Fix Type 1 AMF bitfield and add real FIR/IIR test ROMs
- Fix Type 1 multifunction: AMF=bits17-13, DD=bits19-18, PD=bits21-20 (was off by one bit, causing wrong MAC decode on real firmware) - Add FIR filter ROM (fir.bin): 52 instructions, assembled from AD example - Add IIR biquad ROM (iir.bin): 28 instructions, assembled from AD example - Add open21xx-compatible source files (build/fir.dsp, build/iir.dsp) - Both ROMs disassemble correctly showing expected DSP patterns: MAC+dual-read kernels, DO UNTIL loops, ASHIFT scaling, RTS(DB) - Full regression: isa_test.bin unchanged
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@@ -83,15 +83,18 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask)
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}
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/* Type 1: Compute | DM | PM (11xxxx) */
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/* PD=bits21-20, DD=bits19-18, AMF=bits17-13, YOP=bits12-11,
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XOP=bits10-8, PMI=bits7-6, PMM=bits5-4, DMI=bits3-2, DMM=bits1-0 */
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if (b23_22 == 3)
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{
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ut32 amf = (ins >> 12) & 0x1F;
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const char *f = (amf < 16) ? amf_mac[amf] : amf_alu[amf-16];
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ut32 amf = (ins >> 13) & 0x1F;
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const char *f = (amf < 16) ? amf_mac[amf] : amf_alu[amf - 16];
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int dmi = (ins >> 2) & 3, dmm = ins & 3;
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int pmi = (ins >> 6) & 3, pmm = (ins >> 4) & 3;
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int dd = (ins >> 17) & 3, pd = (ins >> 19) & 3;
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int dd = (ins >> 18) & 3, pd = (ins >> 20) & 3;
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op->mnemonic = r_str_newf ("%s, %s=DM(I%d+=M%d), %s=PM(I%d+=M%d)",
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f, reg0[dd], dmi, dmm, reg0[pd+4], pmi+4, pmm+4);
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f, reg0[dd], dmi, dmm,
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reg0[pd + 4], pmi + 4, pmm + 4);
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return true;
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}
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