Fix Type 1 AMF bitfield and add real FIR/IIR test ROMs

- Fix Type 1 multifunction: AMF=bits17-13, DD=bits19-18, PD=bits21-20
  (was off by one bit, causing wrong MAC decode on real firmware)
- Add FIR filter ROM (fir.bin): 52 instructions, assembled from AD example
- Add IIR biquad ROM (iir.bin): 28 instructions, assembled from AD example
- Add open21xx-compatible source files (build/fir.dsp, build/iir.dsp)
- Both ROMs disassemble correctly showing expected DSP patterns:
  MAC+dual-read kernels, DO UNTIL loops, ASHIFT scaling, RTS(DB)
- Full regression: isa_test.bin unchanged
This commit is contained in:
Dr. Christian Giessen
2026-04-22 19:47:12 +00:00
parent 13521048bc
commit 6849a701d4
9 changed files with 126 additions and 4 deletions

View File

@@ -83,15 +83,18 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask)
}
/* Type 1: Compute | DM | PM (11xxxx) */
/* PD=bits21-20, DD=bits19-18, AMF=bits17-13, YOP=bits12-11,
XOP=bits10-8, PMI=bits7-6, PMM=bits5-4, DMI=bits3-2, DMM=bits1-0 */
if (b23_22 == 3)
{
ut32 amf = (ins >> 12) & 0x1F;
const char *f = (amf < 16) ? amf_mac[amf] : amf_alu[amf-16];
ut32 amf = (ins >> 13) & 0x1F;
const char *f = (amf < 16) ? amf_mac[amf] : amf_alu[amf - 16];
int dmi = (ins >> 2) & 3, dmm = ins & 3;
int pmi = (ins >> 6) & 3, pmm = (ins >> 4) & 3;
int dd = (ins >> 17) & 3, pd = (ins >> 19) & 3;
int dd = (ins >> 18) & 3, pd = (ins >> 20) & 3;
op->mnemonic = r_str_newf ("%s, %s=DM(I%d+=M%d), %s=PM(I%d+=M%d)",
f, reg0[dd], dmi, dmm, reg0[pd+4], pmi+4, pmm+4);
f, reg0[dd], dmi, dmm,
reg0[pd + 4], pmi + 4, pmm + 4);
return true;
}