Fix Type 1 AMF bitfield and add real FIR/IIR test ROMs

- Fix Type 1 multifunction: AMF=bits17-13, DD=bits19-18, PD=bits21-20
  (was off by one bit, causing wrong MAC decode on real firmware)
- Add FIR filter ROM (fir.bin): 52 instructions, assembled from AD example
- Add IIR biquad ROM (iir.bin): 28 instructions, assembled from AD example
- Add open21xx-compatible source files (build/fir.dsp, build/iir.dsp)
- Both ROMs disassemble correctly showing expected DSP patterns:
  MAC+dual-read kernels, DO UNTIL loops, ASHIFT scaling, RTS(DB)
- Full regression: isa_test.bin unchanged

examples/build/fir.dsp

@@ -0,0 +1,69 @@
+/*
+ * fir.dsp -- ADSP-2191 FIR filter adapted for open21xx assembler.
+ * Based on Analog Devices application note.
+ */
+	.section/PM program0;
+	.global _start;
+_start:
+	/* Setup DAGs */
+	i0 = 0x0100;	/* delay line */
+	i1 = 0x0200;	/* input samples */
+	i2 = 0x0300;	/* output */
+	i4 = 0x0400;	/* coefficients (PM) */
+	l0 = 31;	/* circular buffer length */
+	l4 = 31;
+	m0 = 1;
+	m1 = 1;
+	m3 = -1;
+	m4 = 1;
+
+	/* FIR kernel */
+	mr = 0, mx0 = dm(i1,m1), my0 = pm(i4,m4);
+	dm(i0,m3) = mx0;
+	cntr = 40;
+	do _mult_acc until ce;
+
+	/* Inner loop: 30 taps (unrolled) */
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m3), my0=pm(i4,m4);
+
+	/* Last tap + output chain */
+	mr=mr+mx0*my0(ss), mx0=dm(i0,m1), my0=pm(i4,m4);
+	sr=ashift mr2 (hi), mx0=dm(i1,m1);
+	sr=sr or lshift mr1 (lo), dm(i0,m3) = mx0;
+_mult_acc:
+	mr = 0, dm(i2,m1) = sr0;
+	rts (db);
+	mx0 = dm(i0,m1);
+	mx0 = dm(i1,m3);
+
+_halt:
+	jump _halt;

examples/build/iir.dsp

@@ -0,0 +1,41 @@
+/*
+ * iir.dsp -- ADSP-2191 IIR biquad filter for open21xx.
+ * Based on Analog Devices application note.
+ */
+	.section/PM program0;
+	.global _start;
+_start:
+	/* Setup */
+	i0 = 0x0100;	/* delay line */
+	i1 = 0x0200;	/* input */
+	i2 = 0x0300;	/* output */
+	i4 = 0x0400;	/* coefficients (PM) */
+	l0 = 4;	/* 2 * biquad_secs */
+	l4 = 8;	/* 4 coeffs per biquad * 2 */
+	m0 = 1;
+	m1 = 1;
+	m3 = -1;
+	m4 = 1;
+
+	se = 0;
+	cntr = 256;
+	do _filtering until ce;
+	mx0 = dm(i1,m3);
+	my0 = 0x2000;
+	cntr = 2;
+	mr = mx0*my0(su), mx0 = dm(i0,m3), my0 = pm(i4,m4);
+	do _quads until ce;
+	mr = mr+mx0*my0(ss), mx1 = dm(i0,m3), my0 = pm(i4,m4);
+	mr = mr+mx1*my0(ss), my0 = pm(i4,m4);
+	sr = ashift mr1 (hi), my1 = pm(i4,m4);
+	mr = mr+mx0*my0(ss), mx0 = dm(i0,m0), my0 = pm(i4,m4);
+_quads:
+	dm(i0,m3) = sr1, mr = mr+mx1*my1(ss);
+_filtering:
+	dm(i2,m3) = mr1;
+	rts (db);
+	nop;
+	nop;
+
+_halt:
+	jump _halt;

examples/build/link.ldf

@@ -0,0 +1,9 @@
+MEMORY
+{
+    int_pm { TYPE(PM RAM) START(0x000000) LENGTH(0x004000) WIDTH(24) }
+    int_dm { TYPE(DM RAM) START(0x000000) LENGTH(0x004000) WIDTH(16) }
+}
+SECTIONS
+{
+    program0 { INPUT_SECTIONS( $OBJECTS(program0) ) } > int_pm
+}

r2plugin/asm_adsp219x.c

@@ -83,15 +83,18 @@ decode (RArchSession *as, RAnalOp *op, RAnalOpMask mask)
     }
 
   /* Type 1: Compute | DM | PM (11xxxx) */
+  /* PD=bits21-20, DD=bits19-18, AMF=bits17-13, YOP=bits12-11,
+     XOP=bits10-8, PMI=bits7-6, PMM=bits5-4, DMI=bits3-2, DMM=bits1-0 */
   if (b23_22 == 3)
     {
-      ut32 amf = (ins >> 12) & 0x1F;
+      ut32 amf = (ins >> 13) & 0x1F;
-      const char *f = (amf < 16) ? amf_mac[amf] : amf_alu[amf-16];
+      const char *f = (amf < 16) ? amf_mac[amf] : amf_alu[amf - 16];
       int dmi = (ins >> 2) & 3, dmm = ins & 3;
       int pmi = (ins >> 6) & 3, pmm = (ins >> 4) & 3;
-      int dd = (ins >> 17) & 3, pd = (ins >> 19) & 3;
+      int dd = (ins >> 18) & 3, pd = (ins >> 20) & 3;
       op->mnemonic = r_str_newf ("%s, %s=DM(I%d+=M%d), %s=PM(I%d+=M%d)",
-                                 f, reg0[dd], dmi, dmm, reg0[pd+4], pmi+4, pmm+4);
+                                 f, reg0[dd], dmi, dmm,
+                                 reg0[pd + 4], pmi + 4, pmm + 4);
       return true;
     }