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Add real ADSP-2191 assembly examples + open21xx assembler test

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examples/adsp-2191_iir/ADSP-2191 IIR.dpj Normal file
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examples/adsp-2191_iir/ADSP-2191 IIR.txt Normal file
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****************************************************************************
IIR.asm Infinite impulse response filter (IIR)
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
23-JUNE-2001 BJM
This directory contains an example ADSP-2191, single-core Infinite
Impulse Response (IIR) filter.
The IIR code uses coefficients, in an ordered array and applies them to
the filter. A detailed discussion of the IIR algorithm can be found
in the source header comments of "IIR.ASM".
Files contained in this directory:
iir.asm ADSP-2191 source for an example IIR filter
iir_test.asm ADSP-2191 source to call iir.asm
adsp-2191.ldf Linker description file for the IIR example
iir.dpj The VDSP project file for the IIR example.
inreal_256.dat Input data for IIR example in 1.15 format.
coefs_hex.dat Coefficients for IIR example in 1.15 format.
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The IIR filter code executes a canonical form (also called direct form II)
realization structure. The equation of the canonical form is
w(n)=x(n) + b1*w(n-1) + b2*w(n-2)
y(n)=w(n) + a1*w(n-1) + a2*w(n-2)
The input sample is x(n) and the output is y(n). The term w(n) is the
intermediate value; w(n-1) is the previous value and w(n-2) the one before
that. The variables a and b are the coefficients for the filter.
This example of canonical equation uses a variant that limits the summation
in the canonical form to two. This type of IIR is called a biquad and is a
second order filter. Higher order filters can be achieved by cascading several
sections of biquads together.
II. IMPLEMENTATION DESCRIPTION
The assembly language module IIR_TEST.ASM initializes the input and
coefficient buffers and then calls IIR.ASM.
The first buffer declared, INBUF, is N_samp sample locations long.
The next buffer declared, OUTBUF, is also N_samp samples long, and stores the
output of the filter.
DLINE is the third buffer declared. This buffer holds the delay line for each
biquad. That is w(n-1) and w(n-2) for each biquad section of the filter. Since
there are two past intermediate vales for each stage of the biquad, the length of
this buffer is twice as long as the stages.
The coefficient buffer, COEFS, contains the IIR filter coefficients. The
coefficients are typically generated by a filter
design software package.
The linker descriptive file is ADSP-2191.LDF, which describes the hardware in
terms of memory spaces and peripherals.
Because there is no data dependency between DSP cores, it is possible
to do perform an IIR in DSP core 1, while also performing an IIR in DSP core 2
on separate input data, using different coefficients.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
This IIR routine expects input data which conforms to the following criteria:
Generate input data such that an array of input fixed point values are
in 1.15 format, with the data being arranged in the following order:
INPUT DATA
indata(0)
indata(1)
indata(2)
indata(3)
etc...
2. COEFFICIENT DATA:
-----------------------
This IIR routine expects [Biquad_secs*4] fixed point values to be used as coefficients.
COEFFICIENT DATA
A2(0)
A1(0)
B2(0)
B1(0)
...
...
...

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examples/adsp-2191_iir/ADSP-2191.ldf Normal file
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ARCHITECTURE(ADSP-2191)
$OBJECTS = $COMMAND_LINE_OBJECTS;
// This memory map is set up to facilite testing of the tool
// chain -- code and data area are as large as possible.
MEMORY
{
seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) }
seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) }
seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) }
seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x0088ff) WIDTH(16) }
seg_buf1 { TYPE(DM RAM) START(0x008900) END(0x0095ff) WIDTH(16) }
seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) }
seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) }
seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) }
seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) }
}
PROCESSOR p0
{
LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST)
OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
SECTIONS
{
sec_dmy
{
INPUT_SECTIONS( $OBJECTS(IVreset))
} > seg_dmy
sec_itab
{
INPUT_SECTIONS( $OBJECTS(IVpwrdwn))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVkernel))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVstackint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVmailboxint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVtimerint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVringint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVpcibmint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVdspdspint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint13))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint14))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVac97frint))
. = .+0x1;
} > seg_itab
seg_code
{
INPUT_SECTIONS( $OBJECTS(program) )
} >seg_code
sec_buf1
{
INPUT_SECTIONS($OBJECTS(seg_buf1) )
}>seg_buf1
sec_buf2
{
INPUT_SECTIONS($OBJECTS(seg_buf2) )
}>seg_buf2
sec_data1
{
INPUT_SECTIONS( $OBJECTS(data1) )
} >seg_data1
sec_data2
{
INPUT_SECTIONS( $OBJECTS(data2) )
INPUT_SECTIONS( $OBJECTS(program2) )
} >seg_data2
// support for initialization, including C++
sec_ctor
{
INPUT_SECTIONS( $OBJECTS(ctor))
} >seg_data1
// provide linker variables describing the stack (grows down)
// ldf_stack_limit is the lowest address in the stack
// ldf_stack_base is the highest address in the stack
sec_stack
{
ldf_stack_limit = .;
ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1;
} >seg_stack
sec_heap
{
.heap = .;
.heap_size = MEMORY_SIZEOF(seg_heap);
.heap_end = . + MEMORY_SIZEOF(seg_heap) - 1;
} >seg_heap
}
}

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examples/adsp-2191_iir/ADSP-2191_IIR.txt Normal file
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****************************************************************************
IIR.asm Infinite impulse response filter (IIR)
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
23-JUNE-2001 BJM
This directory contains an example ADSP-2191, single-core Infinite
Impulse Response (IIR) filter.
The IIR code uses coefficients, in an ordered array and applies them to
the filter. A detailed discussion of the IIR algorithm can be found
in the source header comments of "IIR.ASM".
Files contained in this directory:
iir.asm ADSP-2191 source for an example IIR filter
iir_test.asm ADSP-2191 source to call iir.asm
adsp-2191.ldf Linker description file for the IIR example
iir.dpj The VDSP project file for the IIR example.
inreal_256.dat Input data for IIR example in 1.15 format.
coefs_hex.dat Coefficients for IIR example in 1.15 format.
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The IIR filter code executes a canonical form (also called direct form II)
realization structure. The equation of the canonical form is
w(n)=x(n) + b1*w(n-1) + b2*w(n-2)
y(n)=w(n) + a1*w(n-1) + a2*w(n-2)
The input sample is x(n) and the output is y(n). The term w(n) is the
intermediate value; w(n-1) is the previous value and w(n-2) the one before
that. The variables a and b are the coefficients for the filter.
This example of canonical equation uses a variant that limits the summation
in the canonical form to two. This type of IIR is called a biquad and is a
second order filter. Higher order filters can be achieved by cascading several
sections of biquads together.
II. IMPLEMENTATION DESCRIPTION
The assembly language module IIR_TEST.ASM initializes the input and
coefficient buffers and then calls IIR.ASM.
The first buffer declared, INBUF, is N_samp sample locations long.
The next buffer declared, OUTBUF, is also N_samp samples long, and stores the
output of the filter.
DLINE is the third buffer declared. This buffer holds the delay line for each
biquad. That is w(n-1) and w(n-2) for each biquad section of the filter. Since
there are two past intermediate vales for each stage of the biquad, the length of
this buffer is twice as long as the stages.
The coefficient buffer, COEFS, contains the IIR filter coefficients. The
coefficients are typically generated by a filter
design software package.
The linker descriptive file is ADSP-2191.LDF, which describes the hardware in
terms of memory spaces and peripherals.
Because there is no data dependency between DSP cores, it is possible
to do perform an IIR in DSP core 1, while also performing an IIR in DSP core 2
on separate input data, using different coefficients.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
This IIR routine expects input data which conforms to the following criteria:
Generate input data such that an array of input fixed point values are
in 1.15 format, with the data being arranged in the following order:
INPUT DATA
indata(0)
indata(1)
indata(2)
indata(3)
etc...
2. COEFFICIENT DATA:
-----------------------
This IIR routine expects [Biquad_secs*4] fixed point values to be used as coefficients.
COEFFICIENT DATA
A2(0)
A1(0)
B2(0)
B1(0)
...
...
...

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examples/adsp-2191_iir/coef_hex.dat Normal file
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0xce58,
0x113e,
0x7fff,
0x7fff,
0xd7cf,
0xf7ce,
0x7fff,
0x7fff

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examples/adsp-2191_iir/iir.asm Normal file
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/**************************************************************
File Name: IIR.asm
Date Modified: 6/21/01 BJM
Description:
Subroutine that implements a IIR Filter given
coefficients and samples.
Equation:
w(n) = x(n) + A1*w(n-1) + A2*w(n-2)
y(n) = w(n) + B1*w(n-1) + B2*w(n-2) (single biquad structure)
Calling Parameters:
b0,i0 = address of delay line buffer
l0 = length of delay line buffer
b1,i1 = address of input samples buffer
b4,i4 = address of coefficients buffer
l4 = length of coefficients buffer
b2,i2 = address of output buffer
Assumptions:
The coefficient buffer should be in the order A2, A1, B2, B1 for each
biquad section.
Delay line, Output and Input buffers stored in DM Block(16-bit).
Instructions, and Coefficients stored in PM Block(24-bit).
Block 0:
Coefficient buffer = { A2[0],A1[0],B2[0],B1[0],A2[1],A1[1],B2[1],... }
Block 1:
Input buffer ={ In[0],In[1],In[2],... }
Output buffer ={ Out[0],Out[1],Out[2],... }
Return Values:
i2 = output buffer
i0 = delay line pointer
Registers Affected:
i0,i1,i2,i4,MX,MY,MR,SR
Cycle Count:
Memory Usage:
Instructions Words (24-bits):
17 (IIR) + 6 (Dline Init) instruction words
Data Words (16 or 24-bits):
Coefs = Number of locations for coefficients (24-bits)
2*Biquad_secs = Number of locations for the delay line (16-bits)
N_samp = Number of samples locations for the input (16-bits)
N_samp = Number of samples locations for the output (16-bits)
Notes:
**************************************************************/
#define N_samp 256
#define Biquad_secs 2
.GLOBAL IIR, Zero_Dline;
.EXTERN Dline, Coefs, Outbuf;
.section/pm program;
IIR:
SE = 0;
CNTR = N_samp; /* Set CNTR for N input samples */
DO filtering UNTIL CE;
MX0 = DM(I1,M3); /* Read Input sample */
MY0 = 0x2000;
CNTR = Biquad_secs; /* Loop for each biquad */
MR = MX0*MY0(SU),MX0 = DM(I0,M3), MY0 = PM(I4,M4); /* Scale input, fetch current biquad A2 */
DO quads UNTIL CE;
MR = MR+MX0*MY0(SS), MX1 = DM(I0,M3), MY0 = PM(I4,M4); /* Fetch current biquad A1 */
MR = MR+MX1*MY0(SS), MY0 = PM(I4,M4); /* Fetch current biquad B2 */
SR = ASHIFT MR1(HI), MY1 = PM(I4,M4); /* Fetch current biquad B1 */
MR = MR+MX0*MY0(SS), MX0 = DM(I0,M0), MY0 = PM(I4,M4); /* Fetch next biquad A2 */
quads:
DM(I0,M3) = SR1, MR = MR+MX1*MY1(SS);
filtering:
DM(I2,M3) = MR1; /* Write filtered output */
rts (db);
nop;nop;
.section/pm program;
Zero_Dline:
CNTR=LENGTH(Dline);
DO zero UNTIL CE;
zero: DM(I0,M0)=0; /* Zero the delay line */
rts (db);
nop;nop;

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examples/adsp-2191_iir/iir_test.asm Normal file
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/************************************************************************
File Name: IIR_test.asm
Date Modified: 6/21/01 BJM
Description: ADSP-2192 single-core program to call
IIR.asm. IIR.asm implements a Cascaded
Biquad IIR filter. All data values and
coefficients are assumed to be in 1.15
format.
************************************************************************/
#define N_samp 256
#define Biquad_secs 2
#define Coef_Length 4*Biquad_secs + 1
.EXTERN IIR, Zero_Dline;
.GLOBAL Dline, Coefs, Outbuf;
/* A2 A1 B2 B1 A2 A1 B2 B1 */
/* A21, A11, B21, B11, A22, A12, B22, B12*/
.section/pm data2;
.VAR Coefs[4 * Biquad_secs] = "coef_hex.dat";
.section/data data1;
.VAR Inbuf[N_samp] = "inreal_256.dat";
.VAR Dline[2 * Biquad_secs];
.VAR Outbuf[N_samp]; /* Filtered sample buffer */
/* PM interrupt vector code */
.section/pm IVreset;
JUMP start; NOP; NOP; NOP; /* Interupt vector table */
/* Program memory code */
.section/pm program;
start:
DMPG2 = page(Coefs);
I0=Dline; /* Initialize delay line pointer */
I1 = Inbuf; /* Initialize input data pointer */
I2 = Outbuf; /* Initialize output data pointer */
I4 = Coefs;
M0=1;
M3 = 1;
M4 = 1;
AX0 = I0;
reg(B0) = AX0; /* Initialize pointer to delay line */
AX0 = I4;
reg(B4) = AX0; /* Initialize pointer to delay line */
CALL Zero_Dline (db); /* Call zero delay function */
L0 = length(Dline); /* Initialize delay line circular buffer */
L1 = 0; /* Initialize for modulo addressing */
CALL IIR (db); /* Call IIR filter function */
M0 = 0;
L4 = Coef_Length; /* Initialize for modulo addressing */
looping: JUMP looping; /* Loop upon itself */

256
examples/adsp-2191_iir/inreal_256.dat Normal file
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@@ -0,0 +1,256 @@
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