Add real ADSP-2191 assembly examples + open21xx assembler test
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Siggi
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examples/adsp-2191_viterbi_decoder/VITERBI.asm
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examples/adsp-2191_viterbi_decoder/VITERBI.asm
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/**************************************************************
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File Name: Viterbi.asm
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Date Modified: 6/23/01 BJM
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Description:
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ADSP-2192 single core subroutine that implements the
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1/2 rate GSM soft decision Viterbi decoder.
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Assumptions:
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The class 1 bits are encoded with the 1/2 rate convolutional code defined by
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the polynomials:
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G0 = 1 + D3+ D4
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G1 = 1 + D + D3+ D4
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Encoded outputs are transmitted as signed antipodal analog signals. They are recieved at
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the decoder and quantized. The quantized number is represented in a 2's
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compliment giving the range of -8 to 7. The process of quantizing a binary analog signal
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with a multi-bit qunatizer is called soft decision. This soft decision is represented by
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the array 'SOFT_DEC_INPUT'
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Registers Affected:
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I0,I1,I2,I3,I4
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M0,M1,M2,M3,M4,M5,M6,M7
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L0,L1,L2,L3,L4
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B1,B3,B4
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AX0,AX1,AY0,AY1
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AR,AF,SR,SI,SE
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MX0
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Cycle Count:
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30751 Cycles
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Memory Usage:
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Instructions Words (24-bits):
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107 instruction words
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Data Words (16 or 24-bits):
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2*N_out = Number of soft decisions (16-bit)
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N_out = Number of state transitions (16-bit)
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16 = Number of New and Old metrics (16-bit)
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N_Words = Decoded output of GSM frame (16-bit)
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8 = Metric Table (16-bit)
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Notes:
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**************************************************************/
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#define N_out 189
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#define N_words 12
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#define N_mod_16 13
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/* DM data */
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.section/data data1;
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.VAR soft_dec_input[2*N_out] = "gsm_rec.dat";
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.VAR state_trans[N_out];
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.VAR old_acc_metric[16];
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.VAR new_acc_metric[16];
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.VAR decoded_output[N_words+4];
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.VAR met_table[8];
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/* PM interrupt vector code */
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.section/pm IVreset;
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JUMP start; NOP; NOP; NOP; /* Interupt vector table */
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/* Program memory code */
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.section/pm program;
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start:
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I0 = soft_dec_input; /* Initialize soft_dec_input pointer */
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L0 = 0; /* Initialize for modulo addressing */
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I1 = old_acc_metric; /* Initialize old_acc_metric pointer */
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L1 = length(old_acc_metric); /* Initialize old_acc_metric circular buffer */
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AX0 = I1;
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reg(B1) = AX0; /* Initialize pointer to old_acc_metric */
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I2 = state_trans; /* Initialize state_trans pointer */
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L2 = 0; /* Initialize for modulo addressing */
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I3 = met_table; /* Initialize met_table pointer */
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L3 = length(met_table); /* Initialize met_table circular buffer */
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AX0 = I3;
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reg(B3) = AX0; /* Initialize pointer to met_table */
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I4 = new_acc_metric; /* Initialize new_acc_metric pointer */
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L4 = length(new_acc_metric); /* Initialize new_acc_metric circular buffer */
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AX0 = I4;
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reg(B4) = AX0; /* Initialize pointer to new_acc_metric */
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M0 = -8;
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M1 = 1;
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M2 = -16;
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M3 = 0;
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M4 = 8;
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M5 = -7;
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M6 = -8;
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M7 = -1;
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SE = 1; /* Setup bit shift */
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SI = 0X8000;
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SR0 = 0;
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SR1 = 0;
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CNTR = 16;
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DO zero_metric UNTIL CE;
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zero_metric: dm(I1,M1) = M3; /* Initialize accumulated metric array */
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CNTR = N_out; /* FOR (k=0; k<N_out; k++) */
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DO add_compare UNTIL CE;
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AX0 = dm(I0,M1);
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AY0 = dm(I0,M1);
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AR = AX0 + AY0;
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dm(I3,M1) = AR, AR = -AR;
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dm(I3,M1) = AR, AR = -AR;
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dm(I3,M1) = AR, AR = -AR;
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dm(I3,M1) = AR, AR = AX0 - AY0;
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dm(I3,M1) = AR, AR = -AR;
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dm(I3,M1) = AR, AR = -AR;
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dm(I3,M1) = AR, AR = -AR;
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dm(I3,M1) = AR;
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CNTR = 8; /* FOR (i=0; i<8; i++) */
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DO calc_metric UNTIL CE;
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AY0 = dm(I3,M1);
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AX1 = dm(I1,M1);
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AF = AX1 + AY0, AX0 = dm(I1,M1); /* AF = old_acc_metric[2*i] + Met_table */
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AR = AX0 - AY0; /* AR = old_acc_metric[2*i+1] - Met_table */
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SR = LSHIFT SR1 (HI); /* State_trans[k] = state_trans[k] << by 1 */
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NONE = AR - AF;
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IF GT SR = SR OR LSHIFT SI (LO); /* Then state_trans[k] = state_trans[k]<<1 | 1 */
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IF LT AR = PASS AF;
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dm(I4,M4) = AR, AF = AX1 - AY0; /* AF = old_acc_metric[2*i] - Met_table */
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AR = AX0 + AY0; /* AR = old_acc_metric[2*i+1] + (-Met_table) */
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SR = LSHIFT SR1 (HI); /* State_trans[k] = state_trans[k] << by 1 */
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NONE = AR - AF;
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IF GT SR = SR OR LSHIFT SI (LO); /* Then state_trans[k] = state_trans[k]<<1 | 1 */
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IF LT AR = PASS AF;
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calc_metric: dm(I4,M5) = AR; /* New_acc_metric[i+2] = AR */
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modify(I4,M6); /* Reset I4 to new_acc_metirc */
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AX1 = I1; /* AX1 = old_acc_metric */
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I1 = I4; /* Old_acc_metric = new_acc_metric */
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AX0 = I1;
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reg(B1) = AX0; /* Initialize pointer to old_acc_metric */
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I4 = AX1; /* New_acc_metric = AX1 */
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reg(B4) = AX1; /* Initialize pointer to new_acc_metric */
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add_compare: dm(I2,M1) = SR1; /* Store state_trans[k] */
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M1 = -1;
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I3 = decoded_output + N_words; /* Initialize decoded_output + N_words pointer */
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L3 = 0; /* Initialize for modulo addressing */
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AY0 = -15;
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AY1 = 15;
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MR0 = N_out - 1;
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MR1 = 0;
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SI = dm(I2,M1); /* Save previous state_trans */
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AX0 = 0;
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MX0 = N_mod_16; /* First word only has 13 valid bits */
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CNTR = N_words;
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DO trace_back UNTIL CE;
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CNTR = MX0;
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DO state_bits UNTIL CE;
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SR = LSHIFT MR1 by 1(LO); /* SR0 = State << 1 */
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AR = CLRBIT 4 OF SR0;
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AX1 = AR;
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AF = TSTBIT 4 OF SR0;
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IF NE AR = SETBIT 0 OF AR;
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AR = AR + AY0, SI = dm(I2,M1); /* Bit_Pos = 15 - rotate(State) */
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SE = AR;
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SR = LSHIFT SI (LO);
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AR = TSTBIT 0 OF SR0;
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AR = AR OR AX1; /* AR = state_trans[k] >> Bit_Pos */
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MR2 = AR, AR = MR0 AND AY1;
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SR = LSHIFT MR1 by - 3(LO);
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SE = AR;
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AR = TSTBIT 0 OF SR0;
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SI = AR;
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SR = LSHIFT SI (LO);
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AR = AX0 OR SR0;
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AX0 = AR;
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AR = MR0 -1; /* Decoded_output |= ((State & 8) >> 3) << (k & 15) */
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MR0 = AR;
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state_bits:
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MR1 = MR2; /* State = new_acc_metric */
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MX0 = 16;
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dm(I3,M1) = AX0;
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trace_back:
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AX0 = 0;
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looping: JUMP looping; /* Loop upon itself */
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