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Add real ADSP-2191 assembly examples + open21xx assembler test

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Siggi
2026-04-12 18:10:08 +00:00
parent d325e04765
commit d7f0569a47
34 changed files with 6283 additions and 0 deletions
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115
examples/adsp-2191_complex_rad2_fft/ADSP-2191.ldf Normal file
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ARCHITECTURE(ADSP-2191)
$OBJECTS = $COMMAND_LINE_OBJECTS;
// This memory map is set up to facilite testing of the tool
// chain -- code and data area are as large as possible.
MEMORY
{
seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) }
seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) }
seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) }
seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x008fff) WIDTH(16) }
seg_buf1 { TYPE(DM RAM) START(0x009000) END(0x0095ff) WIDTH(16) }
seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) }
seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) }
seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) }
seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) }
}
PROCESSOR p0
{
LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST)
OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
SECTIONS
{
sec_dmy
{
INPUT_SECTIONS( $OBJECTS(IVreset))
} > seg_dmy
sec_itab
{
INPUT_SECTIONS( $OBJECTS(IVpwrdwn))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVkernel))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVstackint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVmailboxint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVtimerint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVringint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVpcibmint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVdspdspint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint13))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint14))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVac97frint))
. = .+0x1;
} > seg_itab
seg_code
{
INPUT_SECTIONS( $OBJECTS(program) )
} >seg_code
sec_buf1
{
INPUT_SECTIONS($OBJECTS(seg_buf1) )
}>seg_buf1
sec_buf2
{
INPUT_SECTIONS($OBJECTS(seg_buf2) )
}>seg_buf2
sec_data1
{
INPUT_SECTIONS( $OBJECTS(data1) )
} >seg_data1
sec_data2
{
INPUT_SECTIONS( $OBJECTS(data2) )
INPUT_SECTIONS( $OBJECTS(program2) )
} >seg_data2
// support for initialization, including C++
sec_ctor
{
INPUT_SECTIONS( $OBJECTS(ctor))
} >seg_data1
// provide linker variables describing the stack (grows down)
// ldf_stack_limit is the lowest address in the stack
// ldf_stack_base is the highest address in the stack
sec_stack
{
ldf_stack_limit = .;
ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1;
} >seg_stack
sec_heap
{
.heap = .;
.heap_size = MEMORY_SIZEOF(seg_heap);
.heap_end = . + MEMORY_SIZEOF(seg_heap) - 1;
} >seg_heap
}
}

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examples/adsp-2191_complex_rad2_fft/ADSP-2191_Complex_Rad2_FFT.txt Normal file
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****************************************************************************
Cfft2_2191_Px.asm Example 2191 complex radix-2 FFT Program
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
23-JUNE-2001 BJM
This directory contains an example ADSP-2191 single-core subroutine
that implements radix-2 FFT of length 64 or greater on input data x(n). A
detailed discussion of the complex radix-2 FFT algorithm can be found in the
source header comments of "CFFT2_2191.ASM".
Files contained in this directory:
CFFT2_2191.ASM ADSP-2191 source for a complex radix-2 FFT example.
ADSP-2191.LDF Linker description file for the CFFT2_2191.ASM example
CFFT2_2191.DPJ The VisualDSP project file for the complex radix-2 FFT.
INPUTREAL.DAT Real part of complex input data
INPUTIMAG.DAT Imaginary part of complex input data
TWID_SIN.DAT Sin array FFT twiddle factors
TWID_COS.DAT Cos array FFT twiddle factors
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
1. Input Samples
2. Twiddle factors
_______________________________________________________________
I. FUNCTION/ALGORITHM DESCRIPTION
The program CFFT2_2191.ASM is an implementation of a complex input radix-2 DIT
FFT.
This radix-2 FFT routine will take data lengths that are any power of two (>= 64
points).
II. IMPLEMENTATION DESCRIPTION
This FFT implementation takes advantage of the architecture of the
ADSP-2191.
The following table of variables and their location is presented, where "N" is
the length of the FFT:
Input Output
Routine DM PM DM PM
-------------------------------------------------------------------------------
CFFT2_2191:
inputreal[N] refft[N] inputreal[N]
inputimag[N]
twid_imag[N/2]
twid_real[N/2]
--------------------------------------------------------------------------------
inputreal[N] Real part of normal-ordered complex input stored in DM
inputimag[N] Imaginary part of normal-ordered complex input stored in PM
refft[N] Real part of frequency domain data (fft output) stored in DM
twid_imag[N] Sin table stored in DM
twid_real[N] Cos table stored in DM
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
This FFT routine expects input data which conforms to the following criteria:
Gather input data such that an array of complex fixed point values are
arranged in the following order:
inputreal[N]:
real(0)
real(1)
real(2)
etc...
inputimag[N]:
imag(0)
imag(1)
imag(2)
etc...
2. TWIDDLE FACTOR DATA:
-----------------------
This FFT routine expects N/2 fixed point values of one half period of a
sine waveform and N/2 fixed point values of a one half period of a cosine
waveform to be used as twiddle factors. These twiddles should be in
a bit-reversed order.
Generate twiddle data such that an array of twiddle factor values are
arranged in the following order:
cos(0)
cos(1)
cos(2)
...
...
...
cos(N/2)
sin(0)
sin(1)
sin(2)
...
...
...
sin(N/2)
Then, bit reverse these sin and cosine twiddle arrays. This can be done by
writing a small bit reversal program which utilizes the bit reversed
addressing mode of DAG1 of the ADSP-2191.
The bit reversed array of twiddle factor values are arranged in the following
order:
twid_real[N]:
cos(0)
cos(N/4)
cos(N/8)
...
...
...
cos(N/2)
twid_imag[N]:
sin(0
sin(N/4)
sin(N/8)
...
...
...
sin(N/2)
2191 - Complex Radix-2 FFT (Cfft2_2191.asm)
In order to perform FFTs of different lengths, the following code changes are
necessary:
(The rules/relations described in the source code must be followed!)
- Modify N to reflect the length of the FFT to be performed (N must be a power of 2)
- Modify log2n such that STAGES = (log2(N))
- Mofify Mod_Value such that Mod_Value = ( 2^(16-LOG2N) )
- Modifiy Refft_Bitrev and Inputreal_Bitrev to represent the bit reversed
address of the output real and imaginary buffers
Cfft2_2191.asm code excerpt shown below:
/**********The constants below must be changed for different length FFTs*******
N = number of points in the FFT, must be a power of 2
log2N = log2(N)
Mod_Value = 2^(16-LOG2N)
Refft_Bitrev = bitrev addr of output real in dm
Inputreal_Bitrev = bitrev addr of output imag in dm
******************************************************************************/
/* Set Constants for N-point FFT */
#define N 1024
#define Ndiv2 (N/2)
#define log2N 10
#define Mod_Value 64
#define Refft_Bitrev 0x0001
#define Inputreal_Bitrev 0x0009

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examples/adsp-2191_complex_rad2_fft/Cfft2_2191.asm Normal file
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/******************************************************************************
Cfft2_2191.ASM ADSP-2191 Radix-2 DIT Complex FFT
Performs a radix-2 DIT FFT of length 64 or greater on input data x(n).
N Real part of normal-ordered complex input stored in DM
N Imaginary part of normal-ordered complex input stored in PM
N Real part of fft stored in DM
N/2 Sin table stored in DM
N/2 Cos table stored in PM
Calling Information:
pm(twid_real[N/2]) - sin(2pi*n/N) table in bitreversed order
dm(twid_imag[N/2]) - cos(2pi*n/N) table in bitreversed order
dm(Inputreal[N]) - Real part of complex input array stored in dm
pm(Inputimag[N]) - Imaginary part of complex input array stored in pm
Results:
dm(Refft[N]) - Real FFT results ordered sequentially
dm(Inputreal[N]) - Imaginary FFT results ordered sequentially
Benchmarks:
FFT Length cycles time (us) 160MHz
---------- ------------- ---------------
1024 24160 151
Memory Usage:
PM code(24-bit) = 92 words
PM data(24-bit) = N + 2 + N/2 words
DM data(16-bit) = 2N + 4 + N + 1 words
******************************************************************************/
/**********The constants below must be changed for different length FFTs*******
N = number of points in the FFT, must be a power of 2
log2N = log2(N)
Mod_Value = 2^(16-LOG2N)
Refft_Bitrev = bitrev addr of output real in dm
Inputreal_Bitrev = bitrev addr of output imag in dm
******************************************************************************/
/* Set Constants for N-point FFT */
#define N 1024
#define Ndiv2 (N/2)
#define log2N 10
#define Mod_Value 64
#define Refft_Bitrev 0x0001
#define Inputreal_Bitrev 0x0009
/* DM data */
.section/data data1;
.VAR twid_imag [Ndiv2] = "twid_sin.dat";
.VAR groups = 1;
.VAR node_space = Ndiv2;
/* DM data */
.section/data seg_buf1;
.VAR Inputreal [N+2] = "inreal.dat";
/* DM data */
.section/data seg_buf2;
.VAR Refft[N+2];
/* PM data */
.section/pm data2;
.VAR/init24 twid_real [Ndiv2] = "twid_cos.dat";
.VAR Inputimag [N+2] = "inimag.dat";
/* PM interrupt vector code */
.section/pm IVreset;
JUMP start; NOP; NOP;
/* Program Code */
.section/pm program;
start:
dmpg2 = page(twid_real); /* Initialize page for PM data */
M0 = 0;
L0 = length(twid_imag); /* Initialize twid_imag circular buffer */
AX1 = twid_imag;
REG(b0) = AX1; /* Initialize pointer to twid_imag */
M1 = 1;
L1 = 0; /* Initialize for modulo addressing */
M4 = 0;
L4 = length(twid_real); /* Initialize twid_real circular buffer */
AX1 = twid_real;
REG(b4) = AX1; /* Initialize pointer to twid_real */
M5 = 1;
L5 = 0; /* Initialize for modulo addressing */
M6 = -1;
L6 = 0; /* Initialize for modulo addressing */
L2 = 0;
L3 = 0;
L7 = 0;
CNTR = log2N -1; /* Initialize Stage Counter */
DO stage_loop UNTIL CE; /* Compute all stages in FFT */
I0 = twid_imag; /* I0 --> (-S) of W0 */
I1 = Inputreal; /* I1 --> x1 in 1st group of stage */
I2 = Inputreal; /* I2 --> x0 in 1st group of stage */
I4 = twid_real; /* I4 --> C of W0 */
I5 = Inputimag; /* I5 --> y1 in 1st group of stage */
I6 = Inputimag; /* I6 --> y0 in 1st group of stage */
SI = DM(groups);
CNTR = SI; /* CNTR = # of groups in stage */
SR = LSHIFT SI BY 1(LO);
DM(groups) = SR0;
SI = DM(node_space); /* SI = node_space modifier */
M2 =SI;
M7 =SI;
MODIFY(I1,M2); /* I1 --> x1 in 1st group of stage */
MODIFY(I5,M7); /* I5 --> y1 in 1st group of stage */
DO group_loop UNTIL CE;
MY0 = PM(I4,M5), MX0 = DM(I1,M0); /* MY0=C, MX0=x1 */
MR = MX0*MY0(SS), MX1 = PM(I5,M4); /* MR=C*x1,MX1=y1 */
MY1 = DM(I0,M1); /* MY1 = (-S) */
CNTR = SI; /* CNTR = butterfly counter */
DO bfly_loop UNTIL CE;
MR = MR-MX1*MY1(RND), AY0 = DM(I2,M0); /* MR=x1*C-y1*-S, AY0=x0 */
AR = MR1+AY0, AX1 = PM(I5,M5); /* AR=x0'=x0+(x1*C-y1*-S) */
DM(I2,M1) = AR, AR = AY0-MR1; /* DM=x0', AR=x1'=x0-(x1*C-y1*(-S)) */
MR = MX0*MY1(SS), DM(I1,M1) = AR; /* MR=x1*(-S), DM=x1' */
MR = MR+MX1*MY0(RND), AY1 = PM(I6,M4), MX0 = DM(I1,M0); /*MR=x1*(-S)+y1*C, AY1=y0, MX0=next x1*/
AR = MR1+AY1, MX1 = PM(I5,M6); /* AR=y0'=y0+(y1*C+x1*(-S)), MX1= next y1 */
PM(I6,M5) = AR, AR = AY1-MR1; /* PM=y0', AR=y1'=y0-(y1*C+x1*(-S)) */
bfly_loop:
MR = MX0*MY0(SS), PM(I5,M5) = AR; /* PM=y1' */
MY0 = PM(I5,M7), MX0 = DM(I1,M2);
group_loop:
MY0=PM(I6,M7), MX0=DM(I2,M2);
SR=ASHIFT SI BY -1 (LO);
stage_loop:
DM(node_space)=SR0;
I0 = twid_imag; /* I0 --> (-S) */
I1 = Inputreal; /* I1 --> x1 */
I2 = Inputreal; /* I2 --> x0 */
M2 = 2;
I3 = Refft_Bitrev; /* Refft bitreversed */
M3 = Mod_Value; /* Bitreversed modifier */
I4 = twid_real; /* I4 --> C */
I5 = Inputimag; /* I5 --> y1 */
I6 = Inputimag; /* I6 --> y0 */
M6 = 2;
MODIFY(I1,M1); /* I1 -->x1 */
MODIFY(I5,M5); /* I5 -->y1 */
MY0 = PM(I4,M5), MX0 = DM(I1,M2); /* MY0=C, MX0=x1 */
MR = MX0*MY0(SS), MX1 = PM(I5,M6); /* MR = C*x1, MX1 = y1 */
MY1 = DM(I0,M1); /* MY1 = (-S) */
CNTR = Ndiv2;
DO last_loop UNTIL CE;
MR = MR-MX1*MY1(RND), AY0 = DM(I2,M2); /* MR=x1*C-y1*(-S), AY0=x0 */
AR = MR1+AY0, AY1 = PM(I6,M4); /* AR=x0'=x0+(x1*C-y1*(-S)), AY1=y0 */
ENA BIT_REV;
DM(I3,M3) = AR, AR = AY0-MR1; /* Read real data */
MR = MX0*MY1(SS), DM(I3,M3) = AR; /* Place in sequential order(using bit-reversal) */
DIS BIT_REV;
MR = MR+MX1*MY0(RND), MY0 = PM(I4,M5), MX0 = DM(I1,M2);
AR = MR1+AY1, MX1 = PM(I5,M6); /* AR=y0'=y0+(y1*C+x1*(-S)), MX1= next y1 */
PM(I6,M5) = AR, AR = AY1-MR1; /* PM=y0', AR=y1'=y0-(y1*C+x1*(-S)) */
MY1 = DM(I0,M1); /* MY1 = (-S) */
last_loop:
MR = MX0*MY0(SS), PM(I6,M5) = AR; /*PM=y1' */
I3 = Inputreal_Bitrev;
M3 = Mod_Value; /* Bitreversed modifier */
I5 = Inputimag;
ENA BIT_REV;
CNTR = N;
DO bit_rev_imag UNTIL CE;
AX0 = PM(I5,M5); /* Read imaginary data */
bit_rev_imag: DM(I3,M3) = AX0; /* Place in sequential order */
DIS BIT_REV;
looping: JUMP looping;

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examples/adsp-2191_complex_rad2_fft/Cfft2_2191.dpj Normal file
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examples/adsp-2191_complex_rad2_fft/inimag.dat Normal file
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examples/adsp-2191_complex_rad2_fft/twid_cos.dat Normal file
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0xEF8D00
0x4E2100
0x9A9C00
0x6EFB00
0xC03A00
0x216200
0x846E00
0x794A00
0xD71B00
0x38D900
0x8D5100
0x606800
0xABCD00
0x08A200
0x804B00
0x7F9800
0xF5CD00
0x530300
0x9E9100
0x71FA00
0xC5C000
0x276800
0x863700
0x7B2700
0xDD1B00
0x3E6800
0x903E00
0x646C00
0xB0A200
0x0EE400
0x80DE00
0x7DFB00
0xE95800
0x490F00
0x96E600
0x6BB800
0xBADC00
0x1B4700
0x82F100
0x772300
0xD13400
0x332700
0x8AAA00
0x5C2900
0xA72C00
0x025B00
0x800600
0x7FFA00
0xFDA500
0x58D400
0xA3D700
0x755600
0xCCD900
0x2ECC00
0x88DD00
0x7D0F00
0xE4B900
0x452400
0x944800
0x691A00
0xB6F100
0x16A800
0x820500
0x7F2200
0xF11C00
0x4F5E00
0x9B9400
0x6FC200
0xC19800
0x22E500
0x84D900
0x79C900
0xD89800
0x3A4000
0x8E0600
0x616F00
0xACFD00
0x0A3300
0x806800
0x7FB500
0xF75E00
0x543300
0x9F9800
0x72AF00
0xC72700
0x28E500
0x86B600
0x7B9200
0xDE9E00
0x3FC600
0x910500
0x656400
0xB1DF00
0x107300
0x811000
0x7E3F00
0xEAE400
0x4A5800
0x97CE00
0x6C8F00
0xBC2F00
0x1CD000
0x834900
0x77B400
0xD2AB00
0x349700
0x8B4D00
0x5D3E00
0xA84F00
0x03ED00
0x800F00
0x7FE200
0xFA8100
0x568A00
0xA1B000
0x740B00
0xC9FC00
0x2BDC00
0x87C000
0x7C5A00
0xE1A900
0x427A00
0x929E00
0x674700
0xB46200
0x138F00
0x818100
0x7EBA00
0xEDFF00
0x4CE100
0x99A900
0x6E3100
0xBEDF00
0x1FDD00
0x840700
0x78C800
0xD59E00
0x377000
0x8CA100
0x5F5E00
0xAAA000
0x071100
0x803200
0x7F7500
0xF43C00
0x51CF00
0x9D8E00
0x714100
0xC45B00
0x25E800
0x85BE00
0x7AB700
0xDB9900
0x3D0800
0x8F7D00
0x637100
0xAF6800
0x0D5400
0x80B200
0x7DB100
0xE7CD00
0x47C400
0x960300
0x6ADD00
0xB98B00
0x19BE00
0x829D00
0x768E00
0xCFBE00
0x31B500
0x8A0C00
0x5B1000
0xA60C00
0x00C900
0x800100

512
examples/adsp-2191_complex_rad2_fft/twid_sin.dat Normal file
View File

@@ -0,0 +1,512 @@
0x0000
0x7FFF
0x5A82
0x5A82
0x30FC
0x7642
0x7642
0x30FC
0x18F9
0x7D8A
0x6A6E
0x471D
0x471D
0x6A6E
0x7D8A
0x18F9
0x0C8C
0x7F62
0x62F2
0x5134
0x3C57
0x70E3
0x7A7D
0x2528
0x2528
0x7A7D
0x70E3
0x3C57
0x5134
0x62F2
0x7F62
0x0C8C
0x0648
0x7FD9
0x5ED7
0x55F6
0x36BA
0x73B6
0x7885
0x2B1F
0x1F1A
0x7C2A
0x6DCA
0x41CE
0x4C40
0x66D0
0x7E9D
0x12C8
0x12C8
0x7E9D
0x66D0
0x4C40
0x41CE
0x6DCA
0x7C2A
0x1F1A
0x2B1F
0x7885
0x73B6
0x36BA
0x55F6
0x5ED7
0x7FD9
0x0648
0x0324
0x7FF6
0x5CB4
0x5843
0x33DF
0x7505
0x776C
0x2E11
0x1C0C
0x7CE4
0x6C24
0x447B
0x49B4
0x68A7
0x7E1E
0x15E2
0x0FAB
0x7F0A
0x64E9
0x4EC0
0x3F17
0x6F5F
0x7B5D
0x2224
0x2827
0x798A
0x7255
0x398D
0x539B
0x60EC
0x7FA7
0x096B
0x096B
0x7FA7
0x60EC
0x539B
0x398D
0x7255
0x798A
0x2827
0x2224
0x7B5D
0x6F5F
0x3F17
0x4EC0
0x64E9
0x7F0A
0x0FAB
0x15E2
0x7E1E
0x68A7
0x49B4
0x447B
0x6C24
0x7CE4
0x1C0C
0x2E11
0x776C
0x7505
0x33DF
0x5843
0x5CB4
0x7FF6
0x0324
0x0192
0x7FFE
0x5B9D
0x5964
0x326E
0x75A6
0x76D9
0x2F87
0x1A83
0x7D3A
0x6B4B
0x45CD
0x486A
0x698C
0x7DD6
0x176E
0x0E1C
0x7F38
0x63EF
0x4FFB
0x3DB8
0x7023
0x7AEF
0x23A7
0x26A8
0x7A06
0x719E
0x3AF3
0x5269
0x61F1
0x7F87
0x0AFB
0x07D9
0x7FC2
0x5FE4
0x54CA
0x3825
0x7308
0x790A
0x29A4
0x209F
0x7BC6
0x6E97
0x4074
0x4D81
0x65DE
0x7ED6
0x113A
0x1455
0x7E60
0x67BD
0x4AFB
0x4326
0x6CF9
0x7C89
0x1D93
0x2C99
0x77FB
0x7460
0x354E
0x571E
0x5DC8
0x7FEA
0x04B6
0x04B6
0x7FEA
0x5DC8
0x571E
0x354E
0x7460
0x77FB
0x2C99
0x1D93
0x7C89
0x6CF9
0x4326
0x4AFB
0x67BD
0x7E60
0x1455
0x113A
0x7ED6
0x65DE
0x4D81
0x4074
0x6E97
0x7BC6
0x209F
0x29A4
0x790A
0x7308
0x3825
0x54CA
0x5FE4
0x7FC2
0x07D9
0x0AFB
0x7F87
0x61F1
0x5269
0x3AF3
0x719E
0x7A06
0x26A8
0x23A7
0x7AEF
0x7023
0x3DB8
0x4FFB
0x63EF
0x7F38
0x0E1C
0x176E
0x7DD6
0x698C
0x486A
0x45CD
0x6B4B
0x7D3A
0x1A83
0x2F87
0x76D9
0x75A6
0x326E
0x5964
0x5B9D
0x7FFE
0x0192
0x00C9
0x7FFF
0x5B10
0x59F4
0x31B5
0x75F4
0x768E
0x3042
0x19BE
0x7D63
0x6ADD
0x4675
0x47C4
0x69FD
0x7DB1
0x1833
0x0D54
0x7F4E
0x6371
0x5098
0x3D08
0x7083
0x7AB7
0x2467
0x25E8
0x7A42
0x7141
0x3BA5
0x51CF
0x6272
0x7F75
0x0BC4
0x0711
0x7FCE
0x5F5E
0x5560
0x3770
0x735F
0x78C8
0x2A62
0x1FDD
0x7BF9
0x6E31
0x4121
0x4CE1
0x6657
0x7EBA
0x1201
0x138F
0x7E7F
0x6747
0x4B9E
0x427A
0x6D62
0x7C5A
0x1E57
0x2BDC
0x7840
0x740B
0x3604
0x568A
0x5E50
0x7FE2
0x057F
0x03ED
0x7FF1
0x5D3E
0x57B1
0x3497
0x74B3
0x77B4
0x2D55
0x1CD0
0x7CB7
0x6C8F
0x43D1
0x4A58
0x6832
0x7E3F
0x151C
0x1073
0x7EF0
0x6564
0x4E21
0x3FC6
0x6EFB
0x7B92
0x2162
0x28E5
0x794A
0x72AF
0x38D9
0x5433
0x6068
0x7FB5
0x08A2
0x0A33
0x7F98
0x616F
0x5303
0x3A40
0x71FA
0x79C9
0x2768
0x22E5
0x7B27
0x6FC2
0x3E68
0x4F5E
0x646C
0x7F22
0x0EE4
0x16A8
0x7DFB
0x691A
0x490F
0x4524
0x6BB8
0x7D0F
0x1B47
0x2ECC
0x7723
0x7556
0x3327
0x58D4
0x5C29
0x7FFA
0x025B
0x025B
0x7FFA
0x5C29
0x58D4
0x3327
0x7556
0x7723
0x2ECC
0x1B47
0x7D0F
0x6BB8
0x4524
0x490F
0x691A
0x7DFB
0x16A8
0x0EE4
0x7F22
0x646C
0x4F5E
0x3E68
0x6FC2
0x7B27
0x22E5
0x2768
0x79C9
0x71FA
0x3A40
0x5303
0x616F
0x7F98
0x0A33
0x08A2
0x7FB5
0x6068
0x5433
0x38D9
0x72AF
0x794A
0x28E5
0x2162
0x7B92
0x6EFB
0x3FC6
0x4E21
0x6564
0x7EF0
0x1073
0x151C
0x7E3F
0x6832
0x4A58
0x43D1
0x6C8F
0x7CB7
0x1CD0
0x2D55
0x77B4
0x74B3
0x3497
0x57B1
0x5D3E
0x7FF1
0x03ED
0x057F
0x7FE2
0x5E50
0x568A
0x3604
0x740B
0x7840
0x2BDC
0x1E57
0x7C5A
0x6D62
0x427A
0x4B9E
0x6747
0x7E7F
0x138F
0x1201
0x7EBA
0x6657
0x4CE1
0x4121
0x6E31
0x7BF9
0x1FDD
0x2A62
0x78C8
0x735F
0x3770
0x5560
0x5F5E
0x7FCE
0x0711
0x0BC4
0x7F75
0x6272
0x51CF
0x3BA5
0x7141
0x7A42
0x25E8
0x2467
0x7AB7
0x7083
0x3D08
0x5098
0x6371
0x7F4E
0x0D54
0x1833
0x7DB1
0x69FD
0x47C4
0x4675
0x6ADD
0x7D63
0x19BE
0x3042
0x768E
0x75F4
0x31B5
0x59F4
0x5B10
0x7FFF
0x00C9

BIN
examples/adsp-2191_fir/ADSP-2191 FIR.dpj Normal file
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101
examples/adsp-2191_fir/ADSP-2191 FIR.txt Normal file
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****************************************************************************
fir.asm N-tap finite impulse response filter (FIR)
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
23-JUNE-2001 BJM
This directory contains an example ADSP-2191, single-core subroutine
that implements a N-tap finite impulse response filter (FIR) using coefficients.
Files contained in this directory:
fir.dpj VisualDSP project file
fir.asm ADSP-2191 source for FIR
fir_test.asm Calling function for fic.asm
ADSP-2191.ldf Linker description file
input_dec.dat Sample data for FIR
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The project fir.dpj contains an implementation of a single-core subroutine
that implements a N-tap finite impulse response filter (FIR). This
routine has been optimized to take advantage of the repetitive multiply
accumulates inherent to the algorithm.
y(n) = Summation from k=0 to M of h(k)*x(n-k)
II. IMPLEMENTATION DESCRIPTION
The assembly language module FIR_TEST.ASM initializes the input and
coefficient buffers and then calls FIR.ASM.
The first buffer declared, IN, is Num_Samp locations long.
The next buffer declared, OUT, is also Num_Samp long, and stores the
output of the filter.
Delay_Line is the third buffer declared. This buffer holds the delay line.
Since there are past intermediate values for each stage of the FIR, the length of
this buffer is as long as the number of Taps.
The coefficient buffer, COEFF, contains the FIR filter coefficients. The
coefficients are typically generated by a filter design software package.
The linker descriptive file is ADSP-2191.LDF, which describes the hardware in
terms of memory spaces and peripherals.
Because there is no data dependency between DSP cores, it is possible
to do perform an FIR in DSP core 1, while also performing an FIR in DSP core 2
on separate input data, using different coefficients.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
This FIR routine expects input data which conforms to the following criteria:
Generate input data such that an array of input fixed point values are arranged
in the following order:
INPUT DATA
indata(0)
indata(1)
indata(2)
indata(3)
...
...
...
2. COEFFICIENT DATA:
-----------------------
This FIR routine expects TAPS 1.15 fixed point values to be used as coefficients.
COEFFICIENT DATA
coef(0)
coef(1)
coef(2)
coef(3)
...
...
...

115
examples/adsp-2191_fir/ADSP-2191.ldf Normal file
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ARCHITECTURE(ADSP-2191)
$OBJECTS = $COMMAND_LINE_OBJECTS;
// This memory map is set up to facilite testing of the tool
// chain -- code and data area are as large as possible.
MEMORY
{
seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) }
seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) }
seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) }
seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x0088ff) WIDTH(16) }
seg_buf1 { TYPE(DM RAM) START(0x008900) END(0x0095ff) WIDTH(16) }
seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) }
seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) }
seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) }
seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) }
}
PROCESSOR p0
{
LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST)
OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
SECTIONS
{
sec_dmy
{
INPUT_SECTIONS( $OBJECTS(IVreset))
} > seg_dmy
sec_itab
{
INPUT_SECTIONS( $OBJECTS(IVpwrdwn))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVkernel))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVstackint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVmailboxint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVtimerint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVringint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVpcibmint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVdspdspint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint13))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint14))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVac97frint))
. = .+0x1;
} > seg_itab
seg_code
{
INPUT_SECTIONS( $OBJECTS(program) )
} >seg_code
sec_buf1
{
INPUT_SECTIONS($OBJECTS(seg_buf1) )
}>seg_buf1
sec_buf2
{
INPUT_SECTIONS($OBJECTS(seg_buf2) )
}>seg_buf2
sec_data1
{
INPUT_SECTIONS( $OBJECTS(data1) )
} >seg_data1
sec_data2
{
INPUT_SECTIONS( $OBJECTS(data2) )
INPUT_SECTIONS( $OBJECTS(program2) )
} >seg_data2
// support for initialization, including C++
sec_ctor
{
INPUT_SECTIONS( $OBJECTS(ctor))
} >seg_data1
// provide linker variables describing the stack (grows down)
// ldf_stack_limit is the lowest address in the stack
// ldf_stack_base is the highest address in the stack
sec_stack
{
ldf_stack_limit = .;
ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1;
} >seg_stack
sec_heap
{
.heap = .;
.heap_size = MEMORY_SIZEOF(seg_heap);
.heap_end = . + MEMORY_SIZEOF(seg_heap) - 1;
} >seg_heap
}
}

101
examples/adsp-2191_fir/ADSP-2191_FIR.txt Normal file
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@@ -0,0 +1,101 @@
****************************************************************************
fir.asm N-tap finite impulse response filter (FIR)
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
23-JUNE-2001 BJM
This directory contains an example ADSP-2191, single-core subroutine
that implements a N-tap finite impulse response filter (FIR) using coefficients.
Files contained in this directory:
fir.dpj VisualDSP project file
fir.asm ADSP-2191 source for FIR
fir_test.asm Calling function for fic.asm
ADSP-2191.ldf Linker description file
input_dec.dat Sample data for FIR
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The project fir.dpj contains an implementation of a single-core subroutine
that implements a N-tap finite impulse response filter (FIR). This
routine has been optimized to take advantage of the repetitive multiply
accumulates inherent to the algorithm.
y(n) = Summation from k=0 to M of h(k)*x(n-k)
II. IMPLEMENTATION DESCRIPTION
The assembly language module FIR_TEST.ASM initializes the input and
coefficient buffers and then calls FIR.ASM.
The first buffer declared, IN, is Num_Samp locations long.
The next buffer declared, OUT, is also Num_Samp long, and stores the
output of the filter.
Delay_Line is the third buffer declared. This buffer holds the delay line.
Since there are past intermediate values for each stage of the FIR, the length of
this buffer is as long as the number of Taps.
The coefficient buffer, COEFF, contains the FIR filter coefficients. The
coefficients are typically generated by a filter design software package.
The linker descriptive file is ADSP-2191.LDF, which describes the hardware in
terms of memory spaces and peripherals.
Because there is no data dependency between DSP cores, it is possible
to do perform an FIR in DSP core 1, while also performing an FIR in DSP core 2
on separate input data, using different coefficients.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
This FIR routine expects input data which conforms to the following criteria:
Generate input data such that an array of input fixed point values are arranged
in the following order:
INPUT DATA
indata(0)
indata(1)
indata(2)
indata(3)
...
...
...
2. COEFFICIENT DATA:
-----------------------
This FIR routine expects TAPS 1.15 fixed point values to be used as coefficients.
COEFFICIENT DATA
coef(0)
coef(1)
coef(2)
coef(3)
...
...
...

31
examples/adsp-2191_fir/Coeff_l.dat Normal file
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@@ -0,0 +1,31 @@
86,
115,
-77,
-103,
24,
187,
18,
-248,
-132,
319,
327,
-374,
-744,
412,
2564,
3671,
2564,
412,
-744,
-374,
327,
319,
-132,
-248,
18,
187,
24,
-103,
-77,
115,
86

81
examples/adsp-2191_fir/Fir.asm Normal file
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@@ -0,0 +1,81 @@
/**************************************************************
File Name: FIR.asm
Date Modified: 6/22/01 BM
Description:
Subroutine that implements a FIR Filter given
coefficients and samples.
Equation: y(n) = Summation from k=0 to M of h(k)*x(n-k)
Calling Parameters:
b0,i0 = address of delay line buffer
l0 = length of delay line buffer
b1,i1 = address of input samples buffer
b4,i4 = address of coefficients buffer
l4 = length of coefficients buffer
b2,i2 = address of output buffer
m1 = 1
m3 = -1
m4 = 1
Assumptions:
Delay line must be of length TAPS
Delay line , Output and Input buffers stored in DM Block.
Instructions, and Coefficients stored in PM Block.
Return Values:
i2 = output buffer
i0 = delay line pointer
Registers Affected:
i0,i1,i2,i4,MX,MY,MR,SR
Cycle Count:
7 + Bin_Samp(Taps-1 + 4) + cache misses
Memory Usage:
Instructions Words (24-bits):
11 + Taps-1 instruction words
Data Words (16 or 24-bits):
Number of taps locations for coefficients (24-bits)
Number of taps locations for the delay line buffer (16-bits)
Number of samples locations for the input buffer (16-bits)
Number of samples locations for the output buffer (16-bits)
Notes:
**************************************************************/
#define Samps_per_Bin 40 /* Number of Input samples in each bin */
#define Taps 31 /* Number of filter taps */
.GLOBAL fir;
/* program memory code */
.section/pm program;
fir:
MR = 0, MX0 = DM(I1,M1), MY0 = PM(I4,m4); /* Read Input sample and coefficient */
DM(I0,M3) = MX0; /* Put Input sample in delay line */
CNTR=Samps_per_Bin; /* Set CNTR to Samps_per_Bin for each bin */
DO mult_acc UNTIL CE;
.repeat (Taps-1);
MR=MR+MX0*MY0(SS), MX0=DM(I0,M3), MY0=PM(I4,M4);
.end_repeat;
MR=MR+MX0*MY0(SS), MX0=DM(I0,M1), MY0=PM(I4,M4);
SR=ASHIFT MR2 (HI), MX0=DM(I1,M1);
SR=SR OR LSHIFT MR1 (LO), DM(I0,M3) = MX0;
mult_acc:
MR = 0, DM(I2,M1)=SR0; /* Write to output */
rts (db);
MX0 = DM(I0,M1); /* Update delay pointer */
MX0 = DM(I1,M3);

76
examples/adsp-2191_fir/Fir_test.asm Normal file
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@@ -0,0 +1,76 @@
/************************************************************************
File Name: Fir_test.asm
Date Modified: 6/22/01 BM
Purpose: Demonstrate initialization and operation of
FIR.asm on the ADSP-2192. FIR.asm is a
single precision direct form FIR filter. All
coefficients and data values are assumed to
be in 1.15 format.
************************************************************************/
#define Num_Samp 512 /* NUmber of Input samples */
#define Taps 31 /* Number of filter taps */
#define Shift 2 /* Number of shifts */
#define Samps_per_Bin 40 /* Number of Input samples in each bin */
#define Num_Bins (Num_Samp/Samps_per_Bin) /* Number of bins */
.EXTERN fir;
/* DM data */
.section/data data1;
.VAR IN[Num_Samp] = "input_dec.dat"; /* Input buffer */
.VAR OUT[Num_Samp]; /* Output buffer */
.VAR Delay_Line[Taps]; /* Delay line */
/* PM data */
.section/pm data2;
.VAR COEFF[Taps] = "coeff_l.dat";
/* PM interrupt vector code */
.section/pm IVreset;
JUMP start; NOP; NOP; NOP;
/* Program memory code */
.section/pm program;
start:
I0=Delay_Line; /* Initialize delay line pointer */
M1 = 1;
I1 = IN; /* Initialize Input pointer */
I2 = OUT; /* Initialize Output pointer */
L1=0; /* Initialize for modulo addressing */
L2=0; /* Initialize for modulo addressing */
M3=-1;
M4=1;
SE = Shift;
DMPG2=page(COEFF);
L0=LENGTH (Delay_Line); /* Initialize delay line circular buffer */
ax0 = Delay_Line;
REG(b0) = ax0; /* Initialize pointer to delay line */
L4=length(COEFF); /* Initialize coeficient circular buffer */
ax0 = COEFF;
reg(b4) = ax0; /* Initialize pointer to coeficient */
CNTR=Taps; /* 'Taps' location delay line */
DO zero UNTIL CE;
zero: dm(I0,M1)=L0; /* Delay_line = 0 */
CNTR = Num_Bins; /* Num_Bins to process Num_Samp */
do per_bin until CE;
call fir (db);
I4=COEFF; /* Load Coeff buffer pointer */
nop;
per_bin:
nop;
looping: JUMP looping; /* Loop upon itself */
/************************************************************************/

512
examples/adsp-2191_fir/input_dec.dat Normal file
View File

@@ -0,0 +1,512 @@
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BIN
examples/adsp-2191_iir/ADSP-2191 IIR.dpj Normal file
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115
examples/adsp-2191_iir/ADSP-2191 IIR.txt Normal file
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****************************************************************************
IIR.asm Infinite impulse response filter (IIR)
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
23-JUNE-2001 BJM
This directory contains an example ADSP-2191, single-core Infinite
Impulse Response (IIR) filter.
The IIR code uses coefficients, in an ordered array and applies them to
the filter. A detailed discussion of the IIR algorithm can be found
in the source header comments of "IIR.ASM".
Files contained in this directory:
iir.asm ADSP-2191 source for an example IIR filter
iir_test.asm ADSP-2191 source to call iir.asm
adsp-2191.ldf Linker description file for the IIR example
iir.dpj The VDSP project file for the IIR example.
inreal_256.dat Input data for IIR example in 1.15 format.
coefs_hex.dat Coefficients for IIR example in 1.15 format.
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The IIR filter code executes a canonical form (also called direct form II)
realization structure. The equation of the canonical form is
w(n)=x(n) + b1*w(n-1) + b2*w(n-2)
y(n)=w(n) + a1*w(n-1) + a2*w(n-2)
The input sample is x(n) and the output is y(n). The term w(n) is the
intermediate value; w(n-1) is the previous value and w(n-2) the one before
that. The variables a and b are the coefficients for the filter.
This example of canonical equation uses a variant that limits the summation
in the canonical form to two. This type of IIR is called a biquad and is a
second order filter. Higher order filters can be achieved by cascading several
sections of biquads together.
II. IMPLEMENTATION DESCRIPTION
The assembly language module IIR_TEST.ASM initializes the input and
coefficient buffers and then calls IIR.ASM.
The first buffer declared, INBUF, is N_samp sample locations long.
The next buffer declared, OUTBUF, is also N_samp samples long, and stores the
output of the filter.
DLINE is the third buffer declared. This buffer holds the delay line for each
biquad. That is w(n-1) and w(n-2) for each biquad section of the filter. Since
there are two past intermediate vales for each stage of the biquad, the length of
this buffer is twice as long as the stages.
The coefficient buffer, COEFS, contains the IIR filter coefficients. The
coefficients are typically generated by a filter
design software package.
The linker descriptive file is ADSP-2191.LDF, which describes the hardware in
terms of memory spaces and peripherals.
Because there is no data dependency between DSP cores, it is possible
to do perform an IIR in DSP core 1, while also performing an IIR in DSP core 2
on separate input data, using different coefficients.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
This IIR routine expects input data which conforms to the following criteria:
Generate input data such that an array of input fixed point values are
in 1.15 format, with the data being arranged in the following order:
INPUT DATA
indata(0)
indata(1)
indata(2)
indata(3)
etc...
2. COEFFICIENT DATA:
-----------------------
This IIR routine expects [Biquad_secs*4] fixed point values to be used as coefficients.
COEFFICIENT DATA
A2(0)
A1(0)
B2(0)
B1(0)
...
...
...

115
examples/adsp-2191_iir/ADSP-2191.ldf Normal file
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ARCHITECTURE(ADSP-2191)
$OBJECTS = $COMMAND_LINE_OBJECTS;
// This memory map is set up to facilite testing of the tool
// chain -- code and data area are as large as possible.
MEMORY
{
seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) }
seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) }
seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) }
seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x0088ff) WIDTH(16) }
seg_buf1 { TYPE(DM RAM) START(0x008900) END(0x0095ff) WIDTH(16) }
seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) }
seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) }
seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) }
seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) }
}
PROCESSOR p0
{
LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST)
OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
SECTIONS
{
sec_dmy
{
INPUT_SECTIONS( $OBJECTS(IVreset))
} > seg_dmy
sec_itab
{
INPUT_SECTIONS( $OBJECTS(IVpwrdwn))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVkernel))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVstackint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVmailboxint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVtimerint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVringint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVpcibmint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVdspdspint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint13))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint14))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVac97frint))
. = .+0x1;
} > seg_itab
seg_code
{
INPUT_SECTIONS( $OBJECTS(program) )
} >seg_code
sec_buf1
{
INPUT_SECTIONS($OBJECTS(seg_buf1) )
}>seg_buf1
sec_buf2
{
INPUT_SECTIONS($OBJECTS(seg_buf2) )
}>seg_buf2
sec_data1
{
INPUT_SECTIONS( $OBJECTS(data1) )
} >seg_data1
sec_data2
{
INPUT_SECTIONS( $OBJECTS(data2) )
INPUT_SECTIONS( $OBJECTS(program2) )
} >seg_data2
// support for initialization, including C++
sec_ctor
{
INPUT_SECTIONS( $OBJECTS(ctor))
} >seg_data1
// provide linker variables describing the stack (grows down)
// ldf_stack_limit is the lowest address in the stack
// ldf_stack_base is the highest address in the stack
sec_stack
{
ldf_stack_limit = .;
ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1;
} >seg_stack
sec_heap
{
.heap = .;
.heap_size = MEMORY_SIZEOF(seg_heap);
.heap_end = . + MEMORY_SIZEOF(seg_heap) - 1;
} >seg_heap
}
}

115
examples/adsp-2191_iir/ADSP-2191_IIR.txt Normal file
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@@ -0,0 +1,115 @@
****************************************************************************
IIR.asm Infinite impulse response filter (IIR)
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
23-JUNE-2001 BJM
This directory contains an example ADSP-2191, single-core Infinite
Impulse Response (IIR) filter.
The IIR code uses coefficients, in an ordered array and applies them to
the filter. A detailed discussion of the IIR algorithm can be found
in the source header comments of "IIR.ASM".
Files contained in this directory:
iir.asm ADSP-2191 source for an example IIR filter
iir_test.asm ADSP-2191 source to call iir.asm
adsp-2191.ldf Linker description file for the IIR example
iir.dpj The VDSP project file for the IIR example.
inreal_256.dat Input data for IIR example in 1.15 format.
coefs_hex.dat Coefficients for IIR example in 1.15 format.
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The IIR filter code executes a canonical form (also called direct form II)
realization structure. The equation of the canonical form is
w(n)=x(n) + b1*w(n-1) + b2*w(n-2)
y(n)=w(n) + a1*w(n-1) + a2*w(n-2)
The input sample is x(n) and the output is y(n). The term w(n) is the
intermediate value; w(n-1) is the previous value and w(n-2) the one before
that. The variables a and b are the coefficients for the filter.
This example of canonical equation uses a variant that limits the summation
in the canonical form to two. This type of IIR is called a biquad and is a
second order filter. Higher order filters can be achieved by cascading several
sections of biquads together.
II. IMPLEMENTATION DESCRIPTION
The assembly language module IIR_TEST.ASM initializes the input and
coefficient buffers and then calls IIR.ASM.
The first buffer declared, INBUF, is N_samp sample locations long.
The next buffer declared, OUTBUF, is also N_samp samples long, and stores the
output of the filter.
DLINE is the third buffer declared. This buffer holds the delay line for each
biquad. That is w(n-1) and w(n-2) for each biquad section of the filter. Since
there are two past intermediate vales for each stage of the biquad, the length of
this buffer is twice as long as the stages.
The coefficient buffer, COEFS, contains the IIR filter coefficients. The
coefficients are typically generated by a filter
design software package.
The linker descriptive file is ADSP-2191.LDF, which describes the hardware in
terms of memory spaces and peripherals.
Because there is no data dependency between DSP cores, it is possible
to do perform an IIR in DSP core 1, while also performing an IIR in DSP core 2
on separate input data, using different coefficients.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
This IIR routine expects input data which conforms to the following criteria:
Generate input data such that an array of input fixed point values are
in 1.15 format, with the data being arranged in the following order:
INPUT DATA
indata(0)
indata(1)
indata(2)
indata(3)
etc...
2. COEFFICIENT DATA:
-----------------------
This IIR routine expects [Biquad_secs*4] fixed point values to be used as coefficients.
COEFFICIENT DATA
A2(0)
A1(0)
B2(0)
B1(0)
...
...
...

8
examples/adsp-2191_iir/coef_hex.dat Normal file
View File

@@ -0,0 +1,8 @@
0xce58,
0x113e,
0x7fff,
0x7fff,
0xd7cf,
0xf7ce,
0x7fff,
0x7fff

97
examples/adsp-2191_iir/iir.asm Normal file
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@@ -0,0 +1,97 @@
/**************************************************************
File Name: IIR.asm
Date Modified: 6/21/01 BJM
Description:
Subroutine that implements a IIR Filter given
coefficients and samples.
Equation:
w(n) = x(n) + A1*w(n-1) + A2*w(n-2)
y(n) = w(n) + B1*w(n-1) + B2*w(n-2) (single biquad structure)
Calling Parameters:
b0,i0 = address of delay line buffer
l0 = length of delay line buffer
b1,i1 = address of input samples buffer
b4,i4 = address of coefficients buffer
l4 = length of coefficients buffer
b2,i2 = address of output buffer
Assumptions:
The coefficient buffer should be in the order A2, A1, B2, B1 for each
biquad section.
Delay line, Output and Input buffers stored in DM Block(16-bit).
Instructions, and Coefficients stored in PM Block(24-bit).
Block 0:
Coefficient buffer = { A2[0],A1[0],B2[0],B1[0],A2[1],A1[1],B2[1],... }
Block 1:
Input buffer ={ In[0],In[1],In[2],... }
Output buffer ={ Out[0],Out[1],Out[2],... }
Return Values:
i2 = output buffer
i0 = delay line pointer
Registers Affected:
i0,i1,i2,i4,MX,MY,MR,SR
Cycle Count:
Memory Usage:
Instructions Words (24-bits):
17 (IIR) + 6 (Dline Init) instruction words
Data Words (16 or 24-bits):
Coefs = Number of locations for coefficients (24-bits)
2*Biquad_secs = Number of locations for the delay line (16-bits)
N_samp = Number of samples locations for the input (16-bits)
N_samp = Number of samples locations for the output (16-bits)
Notes:
**************************************************************/
#define N_samp 256
#define Biquad_secs 2
.GLOBAL IIR, Zero_Dline;
.EXTERN Dline, Coefs, Outbuf;
.section/pm program;
IIR:
SE = 0;
CNTR = N_samp; /* Set CNTR for N input samples */
DO filtering UNTIL CE;
MX0 = DM(I1,M3); /* Read Input sample */
MY0 = 0x2000;
CNTR = Biquad_secs; /* Loop for each biquad */
MR = MX0*MY0(SU),MX0 = DM(I0,M3), MY0 = PM(I4,M4); /* Scale input, fetch current biquad A2 */
DO quads UNTIL CE;
MR = MR+MX0*MY0(SS), MX1 = DM(I0,M3), MY0 = PM(I4,M4); /* Fetch current biquad A1 */
MR = MR+MX1*MY0(SS), MY0 = PM(I4,M4); /* Fetch current biquad B2 */
SR = ASHIFT MR1(HI), MY1 = PM(I4,M4); /* Fetch current biquad B1 */
MR = MR+MX0*MY0(SS), MX0 = DM(I0,M0), MY0 = PM(I4,M4); /* Fetch next biquad A2 */
quads:
DM(I0,M3) = SR1, MR = MR+MX1*MY1(SS);
filtering:
DM(I2,M3) = MR1; /* Write filtered output */
rts (db);
nop;nop;
.section/pm program;
Zero_Dline:
CNTR=LENGTH(Dline);
DO zero UNTIL CE;
zero: DM(I0,M0)=0; /* Zero the delay line */
rts (db);
nop;nop;

64
examples/adsp-2191_iir/iir_test.asm Normal file
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@@ -0,0 +1,64 @@
/************************************************************************
File Name: IIR_test.asm
Date Modified: 6/21/01 BJM
Description: ADSP-2192 single-core program to call
IIR.asm. IIR.asm implements a Cascaded
Biquad IIR filter. All data values and
coefficients are assumed to be in 1.15
format.
************************************************************************/
#define N_samp 256
#define Biquad_secs 2
#define Coef_Length 4*Biquad_secs + 1
.EXTERN IIR, Zero_Dline;
.GLOBAL Dline, Coefs, Outbuf;
/* A2 A1 B2 B1 A2 A1 B2 B1 */
/* A21, A11, B21, B11, A22, A12, B22, B12*/
.section/pm data2;
.VAR Coefs[4 * Biquad_secs] = "coef_hex.dat";
.section/data data1;
.VAR Inbuf[N_samp] = "inreal_256.dat";
.VAR Dline[2 * Biquad_secs];
.VAR Outbuf[N_samp]; /* Filtered sample buffer */
/* PM interrupt vector code */
.section/pm IVreset;
JUMP start; NOP; NOP; NOP; /* Interupt vector table */
/* Program memory code */
.section/pm program;
start:
DMPG2 = page(Coefs);
I0=Dline; /* Initialize delay line pointer */
I1 = Inbuf; /* Initialize input data pointer */
I2 = Outbuf; /* Initialize output data pointer */
I4 = Coefs;
M0=1;
M3 = 1;
M4 = 1;
AX0 = I0;
reg(B0) = AX0; /* Initialize pointer to delay line */
AX0 = I4;
reg(B4) = AX0; /* Initialize pointer to delay line */
CALL Zero_Dline (db); /* Call zero delay function */
L0 = length(Dline); /* Initialize delay line circular buffer */
L1 = 0; /* Initialize for modulo addressing */
CALL IIR (db); /* Call IIR filter function */
M0 = 0;
L4 = Coef_Length; /* Initialize for modulo addressing */
looping: JUMP looping; /* Loop upon itself */

256
examples/adsp-2191_iir/inreal_256.dat Normal file
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@@ -0,0 +1,256 @@
-5,
231,
-69,
118,
-112,
98,
-152,
56,
-260,
-42,
226,
-24,
130,
-69,
123,
-112,
104,
-211,
-33,
229,
0,
80,
-69,
87,
-127,
71,
-208,
-73,
194,
32,
49,
-42,
58,
-97,
62,
-197,
-112,
168,
78,
35,
20,
54,
-53,
50,
-152,
-125,
159,
133,
3,
44,
7,
-32,
10,
-118,
-150,
126,
157,
-31,
69,
-49,
-18,
-45,
-98,
-185,
97,
185,
-68,
102,
-52,
48,
-41,
-26,
-198,
79,
220,
-77,
122,
-77,
77,
-74,
10,
-216,
53,
232,
-84,
138,
-94,
103,
-96,
49,
-215,
35,
243,
-87,
115,
-125,
94,
-141,
33,
-270,
-24,
233,
-57,
127,
-101,
111,
-141,
60,
-254,
-27,
239,
-25,
118,
-73,
123,
-118,
84,
-232,
-43,
222,
-1,
93,
-52,
96,
-111,
86,
-215,
-84,
192,
29,
48,
-36,
62,
-100,
60,
-194,
-106,
179,
88,
31,
5,
33,
-71,
41,
-156,
-121,
153,
109,
-23,
15,
-20,
-51,
-4,
-131,
-163,
114,
149,
-44,
62,
-37,
-4,
-28,
-80,
-175,
112,
203,
-53,
112,
-54,
35,
-57,
-40,
-203,
65,
209,
-76,
120,
-86,
70,
-77,
9,
-219,
47,
240,
-75,
126,
-115,
79,
-121,
20,
-245,
11,
230,
-78,
135,
-102,
112,
-119,
75,
-226,
12,
256,
-42,
142,
-91,
117,
-126,
88,
-223,
-8,
244,
-24,
118,
-81,
113,
-131,
73,
-245,
-62,
207,
-22,
57,
-84,
76,
-121,
79,
-222,
-80,
203,
43,
54,
-34,
67,
-94,
72,
-177,
-88,
192,
84,
17,
-5,
22,
-90,
11,
-189,
-153,
134,
105,
-34,
14,
-10,
-38,
11,
-119,
-145,
133

80
examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi Decoder.txt Normal file
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@@ -0,0 +1,80 @@
****************************************************************************
Viterbi.asm Soft Decision GSM Viterbi Decoder
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
21-JUNE-2001 BJM
This directory contains an example ADSP-2191 single-core subroutine
that implements a soft decision half-rate, soft-decision, GSM Viterbi decoder.
Files contained in this directory:
VITERBI.dpj VisualDSP project file
VITERBI.asm ADSP-2191 source for Viterbi
ADSP-2191.ldf Linker description file
GSM_REC.dat Soft decision data for Viterbi
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The project Viterbi.dpj contains an implementation of a single-core
subroutine that implements a half-rate, soft-decision, GSM Vitertbi decoder.
II. IMPLEMENTATION DESCRIPTION
1. METRIC UPDATE:
-----------------
The metric update section accumulates branch distance metrics into path metrics.
The lowest path metric at the end of processing is considered to denote the
path most likely to contain the correct decoding of the input.
Each element of the state_trans[] array represents a state transition.
Each of the 16-bits in an element of state_trans[] represents one of the
16 possible new states, and indicates which of two possible states
is the most likely previous state.
2. TRACE BACK:
--------------
The traceback traces back through the state_trans[] array. Starting
with a new state, the bits of "state" are rotated to compute the
position of the bit in the current state_trans[] array element that
represents this new state. This bit indicates which state was previous.
We update the state to the previous state using this bit.
During any state transition, the most significant of the four bits in
"state" is the most recent input bit to the convolutional encoder.
This is the bit which is added to the output of the decoder.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
The Viterbi decoder routine expects input data which conforms to the following criteria:
The class 1 bits are encoded with the 1/2 rate convolutional code defined by
the polynomials:
G0 = 1 + D3+ D4
G1 = 1 + D + D3+ D4
Encoded outputs are transmitted as signed antipodal analog signals. They are received at
the decoder and quantized. The quantized number is represented in a 2's
compliment giving the range of -8 to 7. The process of quantizing a binary analog signal
with a multi-bit qunatizer is called soft decision. This soft decision is stored in the
array 'SOFT_DEC_INPUT'.

BIN
examples/adsp-2191_viterbi_decoder/ADSP-2191 Viterbi.dpj Normal file
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Binary file not shown.

115
examples/adsp-2191_viterbi_decoder/ADSP-2191.ldf Normal file
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@@ -0,0 +1,115 @@
ARCHITECTURE(ADSP-2191)
$OBJECTS = $COMMAND_LINE_OBJECTS;
// This memory map is set up to facilite testing of the tool
// chain -- code and data area are as large as possible.
MEMORY
{
seg_dmy { TYPE(PM RAM) START(0x000000) END(0x000003) WIDTH(24) }
seg_itab { TYPE(PM RAM) START(0x000004) END(0x00003f) WIDTH(24) }
seg_code { TYPE(PM RAM) START(0x000040) END(0x003fff) WIDTH(24) }
seg_buf2 { TYPE(DM RAM) START(0x008000) END(0x0088ff) WIDTH(16) }
seg_buf1 { TYPE(DM RAM) START(0x008900) END(0x0095ff) WIDTH(16) }
seg_data1 { TYPE(DM RAM) START(0x009600) END(0x00afff) WIDTH(16) }
seg_data2 { TYPE(PM RAM) START(0x004000) END(0x006bff) WIDTH(24) }
seg_heap { TYPE(DM RAM) START(0x00f200) END(0x00f9ff) WIDTH(16) }
seg_stack { TYPE(DM RAM) START(0x00fa00) END(0x00ffff) WIDTH(16) }
}
PROCESSOR p0
{
LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST)
OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
SECTIONS
{
sec_dmy
{
INPUT_SECTIONS( $OBJECTS(IVreset))
} > seg_dmy
sec_itab
{
INPUT_SECTIONS( $OBJECTS(IVpwrdwn))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVkernel))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVstackint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVmailboxint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVtimerint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVringint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVpcibmint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVdspdspint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo0rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1tmitint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVfifo1rcveint))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint13))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVint14))
. = .+0x1;
INPUT_SECTIONS( $OBJECTS(IVac97frint))
. = .+0x1;
} > seg_itab
seg_code
{
INPUT_SECTIONS( $OBJECTS(program) )
} >seg_code
sec_buf1
{
INPUT_SECTIONS($OBJECTS(seg_buf1) )
}>seg_buf1
sec_buf2
{
INPUT_SECTIONS($OBJECTS(seg_buf2) )
}>seg_buf2
sec_data1
{
INPUT_SECTIONS( $OBJECTS(data1) )
} >seg_data1
sec_data2
{
INPUT_SECTIONS( $OBJECTS(data2) )
INPUT_SECTIONS( $OBJECTS(program2) )
} >seg_data2
// support for initialization, including C++
sec_ctor
{
INPUT_SECTIONS( $OBJECTS(ctor))
} >seg_data1
// provide linker variables describing the stack (grows down)
// ldf_stack_limit is the lowest address in the stack
// ldf_stack_base is the highest address in the stack
sec_stack
{
ldf_stack_limit = .;
ldf_stack_base = . + MEMORY_SIZEOF(seg_stack) - 1;
} >seg_stack
sec_heap
{
.heap = .;
.heap_size = MEMORY_SIZEOF(seg_heap);
.heap_end = . + MEMORY_SIZEOF(seg_heap) - 1;
} >seg_heap
}
}

80
examples/adsp-2191_viterbi_decoder/ADSP-2191_Viterbi_Decoder.txt Normal file
View File

@@ -0,0 +1,80 @@
****************************************************************************
Viterbi.asm Soft Decision GSM Viterbi Decoder
Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062
21-JUNE-2001 BJM
This directory contains an example ADSP-2191 single-core subroutine
that implements a soft decision half-rate, soft-decision, GSM Viterbi decoder.
Files contained in this directory:
VITERBI.dpj VisualDSP project file
VITERBI.asm ADSP-2191 source for Viterbi
ADSP-2191.ldf Linker description file
GSM_REC.dat Soft decision data for Viterbi
_________________________________________________________________
CONTENTS
I. FUNCTION/ALGORITHM DESCRIPTION
II. IMPLEMENTATION DESCRIPTION
III. DESCRIPTION OF INPUT DATA
I. FUNCTION/ALGORITHM DESCRIPTION
The project Viterbi.dpj contains an implementation of a single-core
subroutine that implements a half-rate, soft-decision, GSM Vitertbi decoder.
II. IMPLEMENTATION DESCRIPTION
1. METRIC UPDATE:
-----------------
The metric update section accumulates branch distance metrics into path metrics.
The lowest path metric at the end of processing is considered to denote the
path most likely to contain the correct decoding of the input.
Each element of the state_trans[] array represents a state transition.
Each of the 16-bits in an element of state_trans[] represents one of the
16 possible new states, and indicates which of two possible states
is the most likely previous state.
2. TRACE BACK:
--------------
The traceback traces back through the state_trans[] array. Starting
with a new state, the bits of "state" are rotated to compute the
position of the bit in the current state_trans[] array element that
represents this new state. This bit indicates which state was previous.
We update the state to the previous state using this bit.
During any state transition, the most significant of the four bits in
"state" is the most recent input bit to the convolutional encoder.
This is the bit which is added to the output of the decoder.
III. DESCRIPTION OF INPUT DATA
1. INPUT SAMPLES:
-----------------
The Viterbi decoder routine expects input data which conforms to the following criteria:
The class 1 bits are encoded with the 1/2 rate convolutional code defined by
the polynomials:
G0 = 1 + D3+ D4
G1 = 1 + D + D3+ D4
Encoded outputs are transmitted as signed antipodal analog signals. They are received at
the decoder and quantized. The quantized number is represented in a 2's
compliment giving the range of -8 to 7. The process of quantizing a binary analog signal
with a multi-bit qunatizer is called soft decision. This soft decision is stored in the
array 'SOFT_DEC_INPUT'.

378
examples/adsp-2191_viterbi_decoder/GSM_rec.dat Normal file
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@@ -0,0 +1,378 @@
4,
0,
-3,
-6,
1,
-4,
-5,
-4,
3,
-2,
2,
-6,
1,
-6,
1,
-6,
-1,
-4,
0,
-4,
4,
1,
-5,
6,
3,
3,
-1,
1,
0,
-5,
0,
-1,
-7,
0,
-5,
-3,
-2,
5,
-6,
2,
0,
-4,
2,
-1,
1,
5,
4,
5,
0,
1,
3,
0,
6,
6,
-5,
-3,
-1,
-1,
5,
2,
6,
3,
4,
0,
-6,
-6,
-1,
2,
2,
-1,
-4,
-1,
1,
2,
3,
2,
-5,
6,
6,
-4,
0,
-6,
-5,
-6,
6,
-5,
1,
-7,
-7,
-6,
6,
4,
4,
6,
-7,
6,
-4,
3,
2,
-2,
0,
-1,
-2,
0,
-6,
5,
0,
-4,
-2,
6,
0,
-4,
0,
3,
-2,
3,
-3,
-7,
-6,
0,
1,
-3,
0,
-1,
5,
4,
-5,
6,
2,
-3,
-7,
3,
2,
6,
5,
2,
0,
2,
6,
-3,
3,
2,
0,
2,
-7,
4,
6,
6,
-5,
-4,
0,
4,
1,
-7,
4,
6,
4,
6,
0,
-6,
0,
-4,
2,
4,
2,
0,
-2,
-1,
0,
5,
2,
0,
-2,
5,
2,
-6,
3,
-4,
5,
0,
6,
0,
0,
2,
6,
-7,
1,
5,
-4,
-2,
-2,
-5,
1,
6,
-5,
-7,
-4,
1,
0,
1,
-3,
5,
1,
6,
-7,
-6,
1,
-6,
3,
-5,
-7,
-3,
-2,
0,
6,
-5,
-4,
1,
-2,
6,
0,
1,
2,
3,
-4,
-6,
6,
4,
4,
3,
6,
5,
5,
0,
-7,
-7,
0,
5,
4,
-3,
-2,
-3,
6,
6,
-6,
-1,
-4,
-2,
-7,
2,
0,
4,
1,
-7,
2,
-7,
3,
1,
2,
5,
0,
-5,
-4,
-6,
-7,
4,
-3,
5,
-5,
5,
-2,
-5,
-4,
2,
2,
-5,
3,
-1,
-1,
3,
2,
-5,
5,
0,
6,
3,
-3,
-3,
3,
5,
-5,
-6,
6,
-6,
1,
6,
-7,
-4,
5,
6,
5,
-4,
6,
3,
-6,
-4,
3,
2,
3,
-3,
4,
0,
1,
0,
-7,
4,
1,
3,
-5,
-5,
-6,
-3,
5,
3,
-4,
-7,
6,
-2,
2,
3,
4,
3,
0,
4,
0,
2,
5,
4,
2,
-5,
3,
-4,
-6,
-6,
-2,
-2,
-3,
6,
-4,
-3,
-7,
4,
-1,
0,
-5,
-3,
2,
5,
4,
-5,
5,
5,
-7,
-5,
-7,
-2,
-1,
-4,
0,
2,
4,
-6,
-1,
-2,
4,
1,
-4,
-7

189
examples/adsp-2191_viterbi_decoder/VITERBI.asm Normal file
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@@ -0,0 +1,189 @@
/**************************************************************
File Name: Viterbi.asm
Date Modified: 6/23/01 BJM
Description:
ADSP-2192 single core subroutine that implements the
1/2 rate GSM soft decision Viterbi decoder.
Assumptions:
The class 1 bits are encoded with the 1/2 rate convolutional code defined by
the polynomials:
G0 = 1 + D3+ D4
G1 = 1 + D + D3+ D4
Encoded outputs are transmitted as signed antipodal analog signals. They are recieved at
the decoder and quantized. The quantized number is represented in a 2's
compliment giving the range of -8 to 7. The process of quantizing a binary analog signal
with a multi-bit qunatizer is called soft decision. This soft decision is represented by
the array 'SOFT_DEC_INPUT'
Registers Affected:
I0,I1,I2,I3,I4
M0,M1,M2,M3,M4,M5,M6,M7
L0,L1,L2,L3,L4
B1,B3,B4
AX0,AX1,AY0,AY1
AR,AF,SR,SI,SE
MX0
Cycle Count:
30751 Cycles
Memory Usage:
Instructions Words (24-bits):
107 instruction words
Data Words (16 or 24-bits):
2*N_out = Number of soft decisions (16-bit)
N_out = Number of state transitions (16-bit)
16 = Number of New and Old metrics (16-bit)
N_Words = Decoded output of GSM frame (16-bit)
8 = Metric Table (16-bit)
Notes:
**************************************************************/
#define N_out 189
#define N_words 12
#define N_mod_16 13
/* DM data */
.section/data data1;
.VAR soft_dec_input[2*N_out] = "gsm_rec.dat";
.VAR state_trans[N_out];
.VAR old_acc_metric[16];
.VAR new_acc_metric[16];
.VAR decoded_output[N_words+4];
.VAR met_table[8];
/* PM interrupt vector code */
.section/pm IVreset;
JUMP start; NOP; NOP; NOP; /* Interupt vector table */
/* Program memory code */
.section/pm program;
start:
I0 = soft_dec_input; /* Initialize soft_dec_input pointer */
L0 = 0; /* Initialize for modulo addressing */
I1 = old_acc_metric; /* Initialize old_acc_metric pointer */
L1 = length(old_acc_metric); /* Initialize old_acc_metric circular buffer */
AX0 = I1;
reg(B1) = AX0; /* Initialize pointer to old_acc_metric */
I2 = state_trans; /* Initialize state_trans pointer */
L2 = 0; /* Initialize for modulo addressing */
I3 = met_table; /* Initialize met_table pointer */
L3 = length(met_table); /* Initialize met_table circular buffer */
AX0 = I3;
reg(B3) = AX0; /* Initialize pointer to met_table */
I4 = new_acc_metric; /* Initialize new_acc_metric pointer */
L4 = length(new_acc_metric); /* Initialize new_acc_metric circular buffer */
AX0 = I4;
reg(B4) = AX0; /* Initialize pointer to new_acc_metric */
M0 = -8;
M1 = 1;
M2 = -16;
M3 = 0;
M4 = 8;
M5 = -7;
M6 = -8;
M7 = -1;
SE = 1; /* Setup bit shift */
SI = 0X8000;
SR0 = 0;
SR1 = 0;
CNTR = 16;
DO zero_metric UNTIL CE;
zero_metric: dm(I1,M1) = M3; /* Initialize accumulated metric array */
CNTR = N_out; /* FOR (k=0; k<N_out; k++) */
DO add_compare UNTIL CE;
AX0 = dm(I0,M1);
AY0 = dm(I0,M1);
AR = AX0 + AY0;
dm(I3,M1) = AR, AR = -AR;
dm(I3,M1) = AR, AR = -AR;
dm(I3,M1) = AR, AR = -AR;
dm(I3,M1) = AR, AR = AX0 - AY0;
dm(I3,M1) = AR, AR = -AR;
dm(I3,M1) = AR, AR = -AR;
dm(I3,M1) = AR, AR = -AR;
dm(I3,M1) = AR;
CNTR = 8; /* FOR (i=0; i<8; i++) */
DO calc_metric UNTIL CE;
AY0 = dm(I3,M1);
AX1 = dm(I1,M1);
AF = AX1 + AY0, AX0 = dm(I1,M1); /* AF = old_acc_metric[2*i] + Met_table */
AR = AX0 - AY0; /* AR = old_acc_metric[2*i+1] - Met_table */
SR = LSHIFT SR1 (HI); /* State_trans[k] = state_trans[k] << by 1 */
NONE = AR - AF;
IF GT SR = SR OR LSHIFT SI (LO); /* Then state_trans[k] = state_trans[k]<<1 | 1 */
IF LT AR = PASS AF;
dm(I4,M4) = AR, AF = AX1 - AY0; /* AF = old_acc_metric[2*i] - Met_table */
AR = AX0 + AY0; /* AR = old_acc_metric[2*i+1] + (-Met_table) */
SR = LSHIFT SR1 (HI); /* State_trans[k] = state_trans[k] << by 1 */
NONE = AR - AF;
IF GT SR = SR OR LSHIFT SI (LO); /* Then state_trans[k] = state_trans[k]<<1 | 1 */
IF LT AR = PASS AF;
calc_metric: dm(I4,M5) = AR; /* New_acc_metric[i+2] = AR */
modify(I4,M6); /* Reset I4 to new_acc_metirc */
AX1 = I1; /* AX1 = old_acc_metric */
I1 = I4; /* Old_acc_metric = new_acc_metric */
AX0 = I1;
reg(B1) = AX0; /* Initialize pointer to old_acc_metric */
I4 = AX1; /* New_acc_metric = AX1 */
reg(B4) = AX1; /* Initialize pointer to new_acc_metric */
add_compare: dm(I2,M1) = SR1; /* Store state_trans[k] */
M1 = -1;
I3 = decoded_output + N_words; /* Initialize decoded_output + N_words pointer */
L3 = 0; /* Initialize for modulo addressing */
AY0 = -15;
AY1 = 15;
MR0 = N_out - 1;
MR1 = 0;
SI = dm(I2,M1); /* Save previous state_trans */
AX0 = 0;
MX0 = N_mod_16; /* First word only has 13 valid bits */
CNTR = N_words;
DO trace_back UNTIL CE;
CNTR = MX0;
DO state_bits UNTIL CE;
SR = LSHIFT MR1 by 1(LO); /* SR0 = State << 1 */
AR = CLRBIT 4 OF SR0;
AX1 = AR;
AF = TSTBIT 4 OF SR0;
IF NE AR = SETBIT 0 OF AR;
AR = AR + AY0, SI = dm(I2,M1); /* Bit_Pos = 15 - rotate(State) */
SE = AR;
SR = LSHIFT SI (LO);
AR = TSTBIT 0 OF SR0;
AR = AR OR AX1; /* AR = state_trans[k] >> Bit_Pos */
MR2 = AR, AR = MR0 AND AY1;
SR = LSHIFT MR1 by - 3(LO);
SE = AR;
AR = TSTBIT 0 OF SR0;
SI = AR;
SR = LSHIFT SI (LO);
AR = AX0 OR SR0;
AX0 = AR;
AR = MR0 -1; /* Decoded_output |= ((State & 8) >> 3) << (k & 15) */
MR0 = AR;
state_bits:
MR1 = MR2; /* State = new_acc_metric */
MX0 = 16;
dm(I3,M1) = AX0;
trace_back:
AX0 = 0;
looping: JUMP looping; /* Loop upon itself */

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/*
* isa_test.dsp -- ADSP-219x ISA coverage test for disassembler validation.
* Assembles with open21xx as219x.
*/
.section/PM program0;
.global _start;
_start:
/* Type 30: NOP */
nop;
/* Type 6: Dreg = Imm16 */
ax0 = 0x1234;
ax1 = 0x5678;
ay0 = 0xAAAA;
mx0 = 0x4000;
my0 = 0x2000;
/* Type 7: Reg1/Reg2 = Imm16 */
i0 = 0x0100;
i1 = 0x0200;
i4 = 0x0300;
m0 = 1;
m1 = 1;
m3 = -1;
m4 = 1;
l0 = 0;
l4 = 0;
cntr = 10;
/* Type 17: Reg = Reg */
ar = ax0;
si = ax1;
mr0 = mx0;
/* Type 9: Conditional Compute */
ar = ax0 + ay0;
ar = ax0 - ay0;
ar = ax0 and ay0;
ar = ax0 or ay0;
ar = ax0 xor ay0;
ar = pass ax0;
ar = -ax0;
ar = abs ax0;
mr = mx0 * my0 (ss);
/* Type 10: Direct Jump */
jump _skip1;
_skip1:
nop;
/* Type 10: Conditional Jump */
if eq jump _skip2;
_skip2:
nop;
/* Type 10: Call */
call _sub1;
jump _after_sub;
_sub1:
nop;
rts;
_after_sub:
/* Type 20: Return variants */
nop;
/* Type 11: DO UNTIL */
cntr = 4;
do _loop_end until ce;
nop;
_loop_end:
nop;
/* Type 15: Shift Immediate */
sr = lshift si by 4 (hi);
sr = ashift si by -2 (hi);
/* Type 18: Mode Control */
dis ar_sat;
ena ar_sat;
/* Type 25: Saturate */
sat mr;
/* Type 33: Reg3 = short constant */
se = 0;
/* Infinite loop */
_halt:
jump _halt;

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