6dd976fcf6
Type 12: SF is 4 bits (15-12), D is bit11 (not SF=3bits, D=bit12). Verified all 8 SF variants against assembler: LSHIFT/ASHIFT, HI/LO, plain/OR. FIR output scaling chain now correct. TESTING.md: Synced with actual verification status. 34 of 37 types now assembler-verified. Only Type 22/22a (2-word data write), Type 31 (IDLE), and Type 32a (DAG store+transfer) remain structural-only. Removed build artifacts (.o, .elf) from examples/build/.
3.5 KiB
3.5 KiB
Decoder Test Coverage
Verified = disassembly checked against open21xx assembler output. Structural = implemented from reference docs, no assembler test.
| Type | Description | Status | Test file |
|---|---|---|---|
| 1 | Compute + DM + PM | Verified | fir.bin, iir.bin |
| 3 | Direct memory read/write | Verified | fir.bin (DM writes) |
| 4 | Compute + DM/PM postmodify | Verified | fir.bin, iir.bin |
| 6 | Dreg = Imm16 | Verified | isa_test.bin |
| 7 | Reg1/Reg2 = Imm16 | Verified | isa_test.bin |
| 8 | Compute + Dreg move | Verified | type8_test.dsp |
| 9 | Conditional compute | Verified | type9_test.dsp |
| 9a | Unconditional register compute | Verified | type9_test.dsp |
| 10 | Conditional jump (13-bit rel) | Verified | isa_test.bin |
| 10a | Unconditional jump (16-bit) | Verified | isa_test.bin |
| 11 | DO UNTIL (12-bit rel) | Verified | isa_test.bin, fir.bin |
| 12 | Shift + DM/PM | Verified | shift_sf_test.dsp, fir |
| 14 | Shift + Dreg move | Verified | verify_gaps.dsp |
| 15 | Shift immediate | Verified | isa_test.bin |
| 16 | Conditional shift | Verified | verify_gaps.dsp |
| 17 | Reg = Reg | Verified | isa_test.bin |
| 18 | Mode control (ENA/DIS) | Verified | type18_test.dsp |
| 19 | Indirect jump/call | Verified | verify_gaps.dsp |
| 20 | RTS/RTI | Verified | isa_test.bin, fir.bin |
| 21 | MODIFY (Ireg += Mreg) | Verified | verify_gaps.dsp |
| 21a | MODIFY (Ireg += Imm8) | Verified | verify_gaps.dsp |
| 22 | DM = Data16 (2-word) | Structural | — |
| 22a | PM = Data24 (2-word) | Structural | — |
| 23 | DIVQ | Verified | verify_gaps.dsp |
| 24 | DIVS | Verified | verify_gaps.dsp |
| 25 | SAT MR/SR | Verified | isa_test.bin |
| 26 | Push/Pop/Flush Cache | Verified | verify_gaps.dsp |
| 29 | DM read/write imm modify | Verified | verify_gaps.dsp |
| 30 | NOP | Verified | isa_test.bin |
| 31 | IDLE | Structural | — |
| 32 | Any Reg <-> DM/PM (DAG) | Verified | verify_gaps.dsp |
| 32a | DAG reg store + transfer | Structural | — |
| 33 | Reg3 = Data12 | Verified | isa_test.bin |
| 34 | IO register read/write | Verified | verify_gaps.dsp |
| 35 | System register read/write | Verified | verify_gaps.dsp |
| 36 | Long jump/call (2-word) | Verified | verify_gaps.dsp |
| 37 | SETINT/CLRINT | Verified | verify_gaps.dsp |
Remaining structural-only types
- Type 22/22a: 2-word immediate data write. No open21xx syntax equivalent found for testing.
- Type 31: IDLE. Trivial encoding, low risk.
- Type 32a: DAG register store with transfer. Tightly constrained discriminator (bits 15=0, 12-11=11, 10=0), low overlap risk.