6af34837d2
- Standalone Python disassembler for 24-bit ADSP-219x instructions - Complete instruction set reference (PDFs + extracted text) - Architecture documentation and getting-started guide - Test ROM generator with packed (3-byte) and padded (4-byte) formats - r2pipe-based analysis script for radare2 integration
985 lines
35 KiB
Plaintext
985 lines
35 KiB
Plaintext
5 SHIFTER INSTRUCTIONS
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Figure 5-0.
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Table 5-0.
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Listing 5-0.
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The instruction set provides shifter instructions for performing shift oper-
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ations on 16-bit input to yield 40-bit output. Combining these functions,
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programs can efficiently implement numeric format control, including
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full floating-point representation. Shifter operations include:
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• “Arithmetic Shift” on page 5-6
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• “Arithmetic Shift Immediate” on page 5-8
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• “Logical Shift” on page 5-10
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• “Logical Shift Immediate” on page 5-12
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• “Normalize” on page 5-14
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• “Normalize Immediate” on page 5-17
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• “Exponent Derive” on page 5-20
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• “Exponent (Block) Adjust” on page 5-23
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This chapter describes the individual shifter instructions and the following
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related topics:
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• “Shifter Registers” on page 5-2
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• “Shifter Instruction Options” on page 5-3
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• “Shifter Status Flags” on page 5-5
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• “Denormalization” on page 5-26
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ADSP-219x Instruction Set Reference 5-1
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Shifter Instructions
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For details on condition codes, see “Condition Code (CCODE) Register”
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on page 2-6.
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Shifter Registers
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As shown in Table 5-1, the shifter has five registers.
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Table 5-1. Summary of shifter registers
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Name Size Description
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SR0 16 bits Shifter Result register (low word). SR denotes SR0, SR1, and SR2 combined,
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which hold the 40-bit shifter result.
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SR1 16 bits Shifter Result register (middle word). This register also functions as the mul-
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tiplier’s y-input feedback register. SR denotes SR0, SR1, and SR2 combined,
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which hold the 40-bit shifter result.
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SR2 16/8 bits Shifter Result register (high byte). SR denotes SR0, SR1, and SR2 combined,
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which hold the 40-bit shifter result. Although this register is 16 bits wide, for
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shifter operations, only the lower eight bits are used.
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SB 16/5 bits Shifter Block exponent register. Although this register is 16 bits wide, for
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shifter operations, only the lower five bits are used.
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Contains the effective exponent derived from the number with greatest mag-
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nitude in a block of numbers. This value provides the shift code for all num-
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bers in the block in subsequent NORM or xSHIFT instructions.
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The value in this register is sign-extended to form a 16-bit value when trans-
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ferred to memory or to other data registers.
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Nonshifter instructions can use SB for a 16-bit scratch register.
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5-2 ADSP-219x Instruction Set Reference
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Shifter Instruction Options
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Table 5-1. Summary of shifter registers (Cont’d)
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Name Size Description
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SE 16/8 bits Shifter Exponent register. Although this register is 16 bits wide, for shifter
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operations, only the lower eight bits are used.
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Contains the effective exponent derived from the input data. This value pro-
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vides the shift code for a subsequent NORM or xSHIFT instruction.
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The value in this register is sign-extended to form a 16-bit value when trans-
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ferred to memory or to other data registers.
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Nonshifter instructions can use SE for a 16-bit scratch register.
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SI 16 bits Shifter Input register. Provides single-precision twos-complement input to
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shifter instructions.
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When a shifter operation writes data to SR1, it sign extends the value into
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SR2, overwriting the previous contents of SR2.
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The SB and SE registers are the result registers for the block exponent
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adjust (EXPADJ) operation and derive exponent (EXP) operation, respec-
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tively. The shifter input register SI supplies single-precision input data to
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any shifter operation, except EXPADJ. To input the result from an ALU or
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MAC operation directly, you use the appropriate result register—SR, AR,
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or MR.
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Shifter Instruction Options
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Almost all shifter instructions have two to three options: (HI), (LO), and
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(HIX). Each option enables a different exponent detector mode that oper-
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ates only while the instruction executes. The shifter interprets and handles
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the input data according to the selected mode.
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For the derive exponent (EXP) and block exponent adjust ( EXPADJ) opera-
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tions, the shifter calculates the shift code—the direction and number of
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bits to shift—then stores that value in the SE register. For the ASHIFT,
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LSHIFT, and NORM operations, the user can supply the value of the shift
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ADSP-219x Instruction Set Reference 5-3
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Shifter Instructions
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code directly to the SE or SB registers or use the result of a previous EXP or
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EXPADJ operation.
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For the ASHIFT, LSHIFT, and NORM operations:
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(HI) Operation references the upper half of the output field.
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(LO) Operation references the lower half of the output field.
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For the exponent derive (EXP) operation:
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(HIX) Use this mode for shifts and normalization of results from ALU
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operations.
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Input data is the result of an add or subtract operation that may
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have overflowed. The shifter examines the ALU overflow bit AV. If
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AV=1, the effective exponent of the input is +1 (this value indicates
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that overflowed occurred before the EXP operation executed). If
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AV=0, no overflow occurred and the shifter performs the same oper-
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ations as the (HI) mode.
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(HI) Input data is a single-precision signed number or the upper half of
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a double-precision signed number. The number of leading sign bits
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in the input operand, which equals the number of sign bits minus
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one, determines the shift code.
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(By default, the EXPADJ operation always operates in this mode.)
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(LO) Input data is the lower half of a double-precision signed number.
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To derive the exponent on a double-precision number, you must
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perform the EXP operation twice, once on the upper half of the
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input, and once on the lower half. For details, “Exponent Derive”
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on page 5-20.
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5-4 ADSP-219x Instruction Set Reference
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Shifter Status Flags
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Shifter Status Flags
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Two status flags in the ASTAT register, SS and SV, record the status of
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shifter operations.
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SS Records the sign of the shifter input operand
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SS = 0 positive (+) input
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SS = 1 negative (−) input
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SV Records overflow or underflow status
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SV = 0 no overflow or underflow occurred
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SV = 1 overflow or underflow occurred
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ADSP-219x Instruction Set Reference 5-5
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Shifter Instructions
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Arithmetic Shift
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[IF COND] SR = [SR OR] ASHIFT DREG ( HI ) ;
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LO
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FUNCTION
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Arithmetically shifts the bits of the operand by the amount (number of
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bits) and direction specified by the shift code (value) in the SE register. A
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positive value produces a left (up) shift, and a negative value produces a
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right (down) shift. Optionally, the shift can be based on a half of the
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32-bit output field being shifted. For more information on output
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options, see “Shifter Instruction Options” on page 5-3.
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If execution is based on a condition, the shifter performs the operation
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only if the condition evaluates true, and it performs a NOP operation if the
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condition evaluates false. Omitting the condition forces unconditional
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execution of the instruction.
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With the SR OR option selected, the shifter ORs the shifted output with
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the current contents of the SR register and stores that value in SR. Other-
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wise, it overwrites the current contents of the SR register with the shifted
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output.
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INPUT
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The input operand, the value to shift, is supplied in a data register. You
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can use any of these data registers for the DREG inputs:
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Register File
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AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
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OUTPUT
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SR Shifter result register contains 40-bit result.
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5-6 ADSP-219x Instruction Set Reference
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Arithmetic Shift
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STATUS FLAGS
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Affected Flags–set or cleared by the operation Unaffected Flags
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SV AZ, AN, AV, AC, AS, AQ, SS, MV
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For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
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DETAILS
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The shifter sign-extends the 40-bit result to the left, replicating the MSB
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of the input, and it zero-fills the 40-bit result from the right. Bits shifted
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out past either boundary (SR39 or SR0) are dropped.
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To shift a double-precision number, you shift both halves of the input
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data separately, using the same shift code value for both halves. You
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ASHIFT the upper half of the input data but LSHIFT the lower half. The
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first cycle, you ASHIFT the upper half of the input using the (HI) option.
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The second cycle, you LSHIFT the lower half using both the (LO) and SR OR
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options. Using these options prevents the shifter from sign-extending the
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MSB of the low word and from overwriting the output (upper word) from
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the previous ASHIFT operation.
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EXAMPLES
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AR = 3; SE = AR; /* shift code, left shift 3 bits */
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SI = 0xB6A3; /* value of upper word of input data */
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SR = ASHIFT SI (HI); /* arithmetically shift high word */
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SEE ALSO
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• “Type 16: Shift Reg0” on page 9-38
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• “Condition Code (CCODE) Register” on page 2-6
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• “Mode Status (MSTAT) Register” on page 2-11
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ADSP-219x Instruction Set Reference 5-7
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Shifter Instructions
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Arithmetic Shift Immediate
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SR = [SR OR] ASHIFT DREG BY <imm8> ( HI ) ;
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LO
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FUNCTION
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Arithmetically shifts the bits of the operand by the amount (number of
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bits) and direction specified by the immediate value. Valid immediate val-
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ues range from −128 to 127. A positive value produces a left (up) shift, and
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a negative value produces a right (down) shift. Optionally, the shift can be
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based on a half of the 32-bit output field being shifted. For more informa-
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tion on output options, see “Shifter Instruction Options” on page 5-3.
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With the SR OR option selected, the shifter ORs the shifted output with
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the current contents of the SR register and stores that value in SR. Other-
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wise, it overwrites the current contents of the SR register with the shifted
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output.
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INPUT
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The input operand, the value to shift, is supplied in a data register. You
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can use any of these data registers for the DREG inputs:
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Register File
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AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
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OUTPUT
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SR Shifter result register contains 40-bit result.
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5-8 ADSP-219x Instruction Set Reference
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Arithmetic Shift Immediate
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STATUS FLAGS
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Affected Flags–set or cleared by the operation Unaffected Flags
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SV AZ, AN, AV, AC, AS, AQ, SS, MV
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For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
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DETAILS
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The shifter sign-extends the 40-bit result to the left, replicating the MSB
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of the input, and it zero-fills the 40-bit result from the right. Bits shifted
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out past either boundary (SR39 or SR0) are dropped.
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To shift a double-precision number, you shift both halves of the input
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data separately, using the same immediate value for both halves. You ASH-
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IFT the upper half of the input data but LSHIFT the lower half. The first
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cycle, you ASHIFT the upper half of the input using the (HI) option. The
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second cycle, you LSHIFT the lower half using both the (LO) and SR OR
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options. Using these options prevents the shifter from sign-extending the
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MSB of the low word and from overwriting the output (upper word) from
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the previous ASHIFT operation.
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EXAMPLES
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SI = 0xB6A3; /* value of upper word of input data */
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SR = ASHIFT SI BY 3 (HI);/* arithmetically shift upper word */
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SEE ALSO
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• “Type 15: Shift Data8” on page 9-37
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• “Condition Code (CCODE) Register” on page 2-6
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• “Mode Status (MSTAT) Register” on page 2-11
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ADSP-219x Instruction Set Reference 5-9
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Shifter Instructions
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Logical Shift
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[IF COND] SR = [SR OR] LSHIFT DREG ( HI ) ;
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LO
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FUNCTION
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Logically shifts the bits of the operand by the amount (number of bits)
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and direction specified by the shift code (value) in the SE register. A posi-
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tive value produces a left (up) shift, and a negative value produces a right
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(down) shift. Optionally, the shift can be based on a half of the 32-bit
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output field being shifted. For more information on output options, see
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“Shifter Instruction Options” on page 5-3.
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If execution is based on a condition, the shifter performs the operation
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only if the condition evaluates true, and it performs a NOP operation if the
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condition evaluates false. Omitting the condition forces unconditional
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execution of the instruction.
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With the SR OR option selected, the shifter ORs the shifted output with
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the current contents of the SR register and stores that value in SR. Other-
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wise, it overwrites the current contents of the SR register with the shifted
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output.
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INPUT
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The input operand, the value to shift, is supplied in a data register. You
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can use any of these data registers for the DREG inputs:
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Register File
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AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
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OUTPUT
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SR Shifter result register contains 40-bit result.
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5-10 ADSP-219x Instruction Set Reference
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Logical Shift
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STATUS FLAGS
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Affected Flags–set or cleared by the operation Unaffected Flags
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SV AZ, AN, AV, AC, AS, AQ, SS, MV
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For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
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DETAILS
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For left shifts (positive shift code), the shifter zero-fills the 40-bit result
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from the right. Bits shifted out past the high-order boundary (SR39) are
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dropped.
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For right shifts (negative shift code), the shifter zero-fills the 40-bit result
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from the left. Bits shifted out past the low-order boundary (SR0) are
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dropped.
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To shift a double-precision number, you shift both halves of the input
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data separately, using the same shift code value for both halves. The first
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cycle, you LSHIFT the upper half of the input using the (HI) option. The
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second cycle, you LSHIFT the lower half using both the (LO) and SR OR
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options. Using these options prevents the shifter from overwriting the
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result (upper word) from the previous LSHIFT operation.
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EXAMPLES
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AR = 3; SE = AR; /* shift code left shift 3 bits */
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AX0 = 0x765D; /* value of lower word of input data */
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SR = SR OR LSHIFT AX0(LO);/* logically shift low word */
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SEE ALSO
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• “Type 16: Shift Reg0” on page 9-38
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• “Condition Code (CCODE) Register” on page 2-6
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• “Mode Status (MSTAT) Register” on page 2-11
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ADSP-219x Instruction Set Reference 5-11
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Shifter Instructions
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Logical Shift Immediate
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SR = [SR OR] LSHIFT BY <imm8> ( HI ) ;
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LO
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FUNCTION
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Logically shifts the bits of the operand by the amount (number of bits)
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and direction specified by the immediate value. Valid immediate values
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range from −128 to 127. A positive value produces a left (up) shift, and a
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negative value produces a right (down) shift. Optionally, the shift can be
|
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based on a half of the 32-bit output field being shifted. For more informa-
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tion on output options, see “Shifter Instruction Options” on page 5-3.
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With the SR OR option selected, the shifter ORs the shifted output with
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the current contents of the SR register and stores that value in SR. Other-
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wise, it overwrites the current contents of the SR register with the shifted
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output.
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INPUT
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The input operand, the value to shift, is supplied in a data register. You
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can use any of these data registers for the DREG inputs:
|
||
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Register File
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AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
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OUTPUT
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SR Shifter result register contains 40-bit result.
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5-12 ADSP-219x Instruction Set Reference
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Logical Shift Immediate
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STATUS FLAGS
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Affected Flags–set or cleared by the operation Unaffected Flags
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SV AZ, AN, AV, AC, AS, AQ, SS, MV
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For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
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DETAILS
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For left shifts (positive shift code), the shifter zero-fills the 40-bit result
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from the right. Bits shifted out past the high-order boundary (SR39) are
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dropped.
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For right shifts (negative shift code), the shifter zero-fills the 40-bit result
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from the left. Bits shifted out past the low-order boundary (SR0) are
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dropped.
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To shift a double-precision number, you shift both halves of the input
|
||
data separately, using the same shift code value for both halves. The first
|
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cycle, you LSHIFT the upper half of the input using the (HI) option. The
|
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second cycle, you LSHIFT the lower half using both the (LO) and SR OR
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options. Using these options prevents the shifter from overwriting the
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result (upper word) from the previous LSHIFT operation.
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EXAMPLES
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SI = 0xFF6A; /* single-precision input */
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SR = SR OR LSHIFT SI BY 3 (LO); /* logically shift low word */
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SEE ALSO
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• “Type 15: Shift Data8” on page 9-37
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• “Condition Code (CCODE) Register” on page 2-6
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• “Mode Status (MSTAT) Register” on page 2-11
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ADSP-219x Instruction Set Reference 5-13
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Shifter Instructions
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Normalize
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[IF COND] SR = [SR OR] NORM DREG ( HI ) ;
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LO
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FUNCTION
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Normalization, in essence, is a fixed- to floating-point conversion opera-
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tion that produces an exponent and a mantissa. Optionally, the operation
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can be based on a half of the 32-bit output field being shifted. For more
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information on output options, see “Shifter Instruction Options” on page
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5-3.
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Normalization using this instruction is a two step process that requires:
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• The EXP instruction to derive the exponent for the shift code.
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• The NORM instruction to shift the twos-complement input by the cal-
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culated shift code, removing its redundant sign bits and aligning its
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true sign bit to the high-order bit of the output field.
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The EXP operation calculates the number of redundant sign bits in the
|
||
input and stores the negative of that value in SE. The NORM operation
|
||
negates the value in SE again to generate a positive shift code, ensuring
|
||
that the input is shifted left.
|
||
If execution is based on a condition, the shifter performs the operation
|
||
only if the condition evaluates true, and it performs a NOP operation if the
|
||
condition evaluates false. Omitting the condition forces unconditional
|
||
execution of the instruction.
|
||
With the SR OR option selected, the shifter ORs the shifted output with
|
||
the current contents of the SR register and stores that value in SR. Other-
|
||
wise, it overwrites the current contents of the SR register with the shifted
|
||
output.
|
||
|
||
|
||
|
||
|
||
5-14 ADSP-219x Instruction Set Reference
|
||
Normalize
|
||
|
||
|
||
|
||
|
||
INPUT
|
||
|
||
The input operand, the value to shift, is supplied in a data register. You
|
||
can use any of these data registers for the DREG inputs:
|
||
|
||
Register File
|
||
|
||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||
|
||
|
||
OUTPUT
|
||
|
||
SR Shifter result register contains 40-bit result.
|
||
STATUS FLAGS
|
||
|
||
|
||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||
|
||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||
|
||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||
|
||
|
||
DETAILS
|
||
|
||
The (HI) and (LO) options determine how unused bits in the 40-bit out-
|
||
put are filled. When the (HI) option is selected, the shifter zero-fills the
|
||
40-bit result from the right. When the (LO) option is selected, the shifter
|
||
zero-fills the 40-bit result to the left. Bits shifted out past the high-order
|
||
boundary (SR39) are dropped.
|
||
To normalize a double-precision number, you normalize both halves of
|
||
the input data separately, using the same shift code value for both halves.
|
||
First, you use the EXP instruction to derive the exponent to use for the
|
||
shift code. Then, in the first normalization cycle, you NORM the upper half
|
||
of the input using the (HI) option. The next cycle, you NORM the lower half
|
||
using both the (LO) and SR OR options. Using these options prevents the
|
||
|
||
|
||
|
||
|
||
ADSP-219x Instruction Set Reference 5-15
|
||
Shifter Instructions
|
||
|
||
|
||
|
||
|
||
shifter from overwriting the result (upper word) from the previous NORM
|
||
operation.
|
||
EXAMPLES
|
||
|
||
/* Normalize double-precision twos complement data: */
|
||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||
SE = EXP AX1 (HI); /* derive exponent on hi word */
|
||
SE = EXP AX0 (LO); /* derive exponent on lo word */
|
||
SR = NORM AX1 (HI); /* normalize hi word */
|
||
SR = SR OR NORM AX0 (LO); /* normalize lo word */
|
||
|
||
SEE ALSO
|
||
|
||
• “Type 16: Shift Reg0” on page 9-38
|
||
• “Denormalization” on page 5-26
|
||
• “Condition Code (CCODE) Register” on page 2-6
|
||
• “Mode Status (MSTAT) Register” on page 2-11
|
||
|
||
|
||
|
||
|
||
5-16 ADSP-219x Instruction Set Reference
|
||
Normalize Immediate
|
||
|
||
|
||
|
||
|
||
Normalize Immediate
|
||
|
||
SR = [SR OR] NORM DREG BY <imm8> ( HI ) ;
|
||
LO
|
||
|
||
|
||
FUNCTION
|
||
|
||
Normalization, in essence, is a fixed- to floating-point conversion opera-
|
||
tion that produces an exponent and a mantissa. Using a positive constant
|
||
for the shift code, it is a one step process that shifts the twos-complement
|
||
input left by the specified amount, removing its redundant sign bits and
|
||
aligning its true sign bit to the high-order bit of the output field. Option-
|
||
ally, the operation can be based on a half of the 32-bit output field being
|
||
shifted. For more information on output options, see “Shifter Instruction
|
||
Options” on page 5-3.
|
||
With the SR OR option selected, the shifter ORs the shifted output with
|
||
the current contents of the SR register and stores that value in SR. Other-
|
||
wise, it overwrites the current contents of the SR register with the shifted
|
||
output.
|
||
INPUT
|
||
|
||
The input operand, the value to shift, is supplied in a data register. You
|
||
can use any of these data registers for the DREG inputs:
|
||
|
||
Register File
|
||
|
||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||
|
||
|
||
OUTPUT
|
||
|
||
SR Shifter result register contains 40-bit result.
|
||
|
||
|
||
|
||
|
||
ADSP-219x Instruction Set Reference 5-17
|
||
Shifter Instructions
|
||
|
||
|
||
|
||
|
||
STATUS FLAGS
|
||
|
||
|
||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||
|
||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||
|
||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||
|
||
|
||
DETAILS
|
||
|
||
The (HI) and (LO) options determine how unused bits in the 40-bit out-
|
||
put are filled. When the (HI) option is selected, the shifter zero-fills the
|
||
40-bit result from the right. When the (LO) option is selected, the shifter
|
||
zero-fills the 40-bit result to the left. Bits shifted out past the high-order
|
||
boundary (SR39) are dropped.
|
||
To normalize a double-precision number, you normalize both halves of
|
||
the input data separately, using the immediate value for both halves. In
|
||
the first normalization cycle, you NORM the upper half of the input using
|
||
the (HI) option. The next cycle, you NORM the lower half using both the
|
||
(LO) and SR OR options. Using these options prevents the shifter from
|
||
overwriting the result (upper word) from the previous NORM operation.
|
||
EXAMPLES
|
||
|
||
/* Normalize a double-precision, twos-complement data: */
|
||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||
SR = NORM AX1 BY 2 (HI); /* normalize hi word */
|
||
SR = SR OR NORM AX0 BY 2 (LO);/* normalize lo word */
|
||
|
||
SEE ALSO
|
||
|
||
• “Type 15: Shift Data8” on page 9-37
|
||
• “Denormalization” on page 5-26
|
||
|
||
|
||
|
||
|
||
5-18 ADSP-219x Instruction Set Reference
|
||
Normalize Immediate
|
||
|
||
|
||
|
||
|
||
• “Condition Code (CCODE) Register” on page 2-6
|
||
• “Mode Status (MSTAT) Register” on page 2-11
|
||
|
||
|
||
|
||
|
||
ADSP-219x Instruction Set Reference 5-19
|
||
Shifter Instructions
|
||
|
||
|
||
|
||
|
||
Exponent Derive
|
||
|
||
[IF COND] SE = EXP DREG ( HIX ) ;
|
||
HI
|
||
LO
|
||
|
||
|
||
FUNCTION
|
||
|
||
Derives the effective exponent of the input operand to generate the shift
|
||
code value for use in a subsequent normalization operation. The instruc-
|
||
tion option, (HIX), (HI), or (LO), determines the resulting shift code. For
|
||
more information on output options, see “Shifter Instruction Options” on
|
||
page 5-3.
|
||
If execution is based on a condition, the shifter performs the operation
|
||
only if the condition evaluates true, and it performs a NOP operation if the
|
||
condition evaluates false. Omitting the condition forces unconditional
|
||
execution of the instruction.
|
||
INPUT
|
||
|
||
The input operand, the value to shift, is supplied in a data register. You
|
||
can use any of these data registers for the DREG inputs:
|
||
|
||
Register File
|
||
|
||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||
|
||
|
||
OUTPUT
|
||
|
||
SE Shifter exponent register contains the 8-bit shift code.
|
||
|
||
|
||
|
||
|
||
5-20 ADSP-219x Instruction Set Reference
|
||
Exponent Derive
|
||
|
||
|
||
|
||
|
||
STATUS FLAGS
|
||
|
||
|
||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||
|
||
SS (Affected by operations using the (HI) and AZ, AN, AV, AC, AS, AQ, MV, SV
|
||
(HIX) options only. Set by the MSB of the input
|
||
data when AV = 0. In (HIX) mode only, set by the
|
||
inverted MSB of the input data when AV = 1.)
|
||
|
||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||
|
||
|
||
DETAILS
|
||
|
||
You use the (LO) option only to derive the exponent for the low word in a
|
||
double-precision twos-complement number. But before you do, you must
|
||
derive the exponent on the high word using either the (HI) or the (HIX)
|
||
option. The result of the EXP operation on the upper half determines the
|
||
shift code of the lower half. Unless the upper half contains all sign bits,
|
||
the SE register contains the correct shift code to use for both EXP (HI/HIX)
|
||
and (LO) operations. If the upper half does contain all sign bits, EXP (LO)
|
||
totals the number of sign bits in the double-precision word and stores that
|
||
value in SE.
|
||
EXAMPLES
|
||
|
||
/* Normalize double-precision twos complement data: */
|
||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||
SE = EXP AX1 (HI); /* derive exponent on hi word */
|
||
SE = EXP AX0 (LO); /* derive exponent on lo word */
|
||
SR = NORM AX1 (HI); /* normalize hi word */
|
||
SR = SR OR NORM AX0 (LO); /* normalize lo word */
|
||
|
||
|
||
|
||
|
||
ADSP-219x Instruction Set Reference 5-21
|
||
Shifter Instructions
|
||
|
||
|
||
|
||
|
||
SEE ALSO
|
||
|
||
• “Type 16: Shift Reg0” on page 9-38
|
||
• “Condition Code (CCODE) Register” on page 2-6
|
||
• “Mode Status (MSTAT) Register” on page 2-11
|
||
|
||
|
||
|
||
|
||
5-22 ADSP-219x Instruction Set Reference
|
||
Exponent (Block) Adjust
|
||
|
||
|
||
|
||
|
||
Exponent (Block) Adjust
|
||
|
||
[IF COND] SB = EXPADJ DREG ;
|
||
|
||
|
||
FUNCTION
|
||
|
||
Derives the effective exponent of the number of largest magnitude in a
|
||
block of numbers. Using this value for the shift code in subsequent NORM
|
||
instructions, you can normalize each number in the block.
|
||
If execution is based on a condition, the shifter performs the operation
|
||
only if the condition evaluates true, and it performs a NOP operation if the
|
||
condition evaluates false. Omitting the condition forces unconditional
|
||
execution of the instruction.
|
||
INPUT
|
||
|
||
The input operand, the value to shift, is supplied in a data register. You
|
||
can use any of these data registers for the DREG inputs:
|
||
|
||
Register File
|
||
|
||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||
|
||
|
||
OUTPUT
|
||
|
||
SB Shifter block exponent register contains the 5-bit exponent value.
|
||
You must initialize SB to −16 before issuing the first EXPADJ instruc-
|
||
tion in the series.
|
||
|
||
|
||
|
||
|
||
ADSP-219x Instruction Set Reference 5-23
|
||
Shifter Instructions
|
||
|
||
|
||
|
||
|
||
STATUS FLAGS
|
||
|
||
|
||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||
|
||
AZ, AN, AV, AC, AS, AQ, SS, MV, SV
|
||
|
||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||
|
||
|
||
DETAILS
|
||
|
||
This instruction operates in (HI) mode to derive the exponent. It works
|
||
on double-precision twos-complement input only. Possible values for the
|
||
result of the EXPADJ operation range from −15 to 0.
|
||
To derive the effective exponent for a block of numbers, you
|
||
1. Initialize the SB register to −16.
|
||
SB = −16;
|
||
|
||
This value falls below the range of possible exponent values.
|
||
2. For each number in the block, derive the effective exponent.
|
||
SB = EXPADJ DREGx;
|
||
|
||
For the first operation, the shifter derives the exponent and stores it
|
||
in SB.
|
||
For each subsequent operation, the shifter derives the exponent
|
||
and compares the new value with the current value of SB. If the
|
||
new value is greater than the current value, the shifter stores the
|
||
new value in SB, overwriting the old value. Otherwise, the shifter
|
||
discards the new value and the contents of SB remain unchanged.
|
||
At the end of the last EXPADJ operation, SB contains the exponent
|
||
of the number of largest magnitude in the block.
|
||
|
||
|
||
|
||
|
||
5-24 ADSP-219x Instruction Set Reference
|
||
Exponent (Block) Adjust
|
||
|
||
|
||
|
||
|
||
3. Transfer the contents of SB to SE.
|
||
SE = SB;
|
||
|
||
SE now contains the shift code to use in subsequent NORM opera-
|
||
tions to normalize each of the numbers in the block. For details,
|
||
see “Normalize” on page 5-14.
|
||
Alternatively, you can save the exponent in a data register for use
|
||
later in your program.
|
||
EXAMPLES
|
||
|
||
/* Normalize double-precision twos complement data: */
|
||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||
SB = -16; /* initialize SB */
|
||
SB = EXPADJ AX1;
|
||
SB = EXPADJ AX0;
|
||
SE = SB; /* load block adjusted exp */
|
||
SR = NORM AX1 (HI); /* normalize hi word */
|
||
SR = SR OR NORM AX0 (LO); /* normalize lo word */
|
||
|
||
SEE ALSO
|
||
|
||
• “Type 16: Shift Reg0” on page 9-38
|
||
• “Condition Code (CCODE) Register” on page 2-6
|
||
• “Mode Status (MSTAT) Register” on page 2-11
|
||
|
||
|
||
|
||
|
||
ADSP-219x Instruction Set Reference 5-25
|
||
Shifter Instructions
|
||
|
||
|
||
|
||
|
||
Denormalization
|
||
FUNCTION
|
||
|
||
Denormalization is a shift function in which a predefined exponent
|
||
defines the amount and direction of the shift. In essence, denormalization
|
||
is a floating- to fixed-point conversion operation. It requires a series of
|
||
shifter operations:
|
||
• The EXP instruction to derive the exponent used for the shift code,
|
||
or SE explicitly loaded with the exponent value. SE must contain the
|
||
shift value; for denormalization, you cannot use ASHIFT/LSHIFT
|
||
with an immediate value.
|
||
• The ASHIFT instruction to shift a single-precision number or the
|
||
high word of a double-precision number.
|
||
• When denormalizing a double-precision number, the LSHIFT
|
||
instruction to shift the low word.
|
||
Denormalize a double-precision, twos-complement number:
|
||
MX1 = −3; /* generate shift code */
|
||
SE = MX1; /* load value in SE register */
|
||
AX1 = 0xB6A3; /* load high word of input */
|
||
AX0 = 0x765D; /* load low word of input */
|
||
SR = ASHIFT AX1(HI); /* arith shift high word */
|
||
SR = SR OR LSHIFT AX0(LO); /* logically shift low word */
|
||
|
||
You can reverse shift order, but you must always arithmetically shift the
|
||
high word of a double-precision number:
|
||
MX1 = −3; /* generate shift code */
|
||
SE = MX1; /* load value in SE register */
|
||
AX1 = 0xB6A3; /* load high word of input */
|
||
AX0 = 0x765D; /* load low word of input */
|
||
SR = LSHIFT AX0(LO); /* logically shift low word */
|
||
SR = SR OR ASHIFT AX1(HI); /* arith shift high word */
|
||
|
||
|
||
|
||
|
||
5-26 ADSP-219x Instruction Set Reference
|
||
|