Initial commit: ADSP-219x disassembler, docs, test ROMs, analysis tools
- Standalone Python disassembler for 24-bit ADSP-219x instructions - Complete instruction set reference (PDFs + extracted text) - Architecture documentation and getting-started guide - Test ROM generator with packed (3-byte) and padded (4-byte) formats - r2pipe-based analysis script for radare2 integration
This commit is contained in:
Siggi
45
analysis/analyze_rom.py
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45
analysis/analyze_rom.py
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import r2pipe
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import json
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import sys
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# Load local disasm from disassembler dir
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sys.path.append("../disassembler")
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from adsp219x_disasm import decode_24
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def analyze_rom(filename):
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"""
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Automated ROM analysis using radare2 + Python disassembler.
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"""
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r2 = r2pipe.open(filename)
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r2.cmd("e asm.arch = adsp219x") # Custom arch handled by our script logic
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r2.cmd("aa") # Basic analysis (will fail but good practice)
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# Iterate over file bytes
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file_info = json.loads(r2.cmd("iX"))
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size = file_info[0]["size"]
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print(f"Analyzing {filename} ({size} bytes)...")
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# 3-byte step for ADSP-219x
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for offset in range(0, size, 3):
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# Read 3 bytes
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chunk = r2.cmdj(f"pxj 3 @ {offset}")
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if not chunk or len(chunk) < 3: break
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opcode = (chunk[0] << 16) | (chunk[1] << 8) | chunk[2]
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disasm = decode_24(opcode)
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# Set flags, comments, etc., back into r2
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r2.cmd(f"CC {disasm} @ {offset}")
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print(f"0x{offset:04X}: {disasm}")
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# Output comment report
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print("\nAnalysis Summary:\n")
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print(r2.cmd("CC"))
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r2.quit()
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if __name__ == "__main__":
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if len(sys.argv) < 2:
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print("Usage: analyze_rom.py <rom.bin>")
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else:
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analyze_rom(sys.argv[1])
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147
disassembler/adsp219x_disasm.py
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147
disassembler/adsp219x_disasm.py
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import sys
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# AMF (ALU/Multiplier Function) codes (5 bits, 0-31)
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AMF_ALU = {
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0x10: "Y", 0x11: "Y+1", 0x12: "X+Y+C", 0x13: "X+Y",
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0x14: "NOT Y", 0x15: "-Y", 0x16: "X-Y+C-1", 0x17: "X-Y",
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0x18: "Y-1", 0x19: "Y-X", 0x1a: "Y-X+C-1", 0x1b: "NOT X",
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0x1c: "X AND Y", 0x1d: "X OR Y", 0x1e: "X XOR Y", 0x1f: "ABS X"
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}
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AMF_MAC = {
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0x00: "NOP", 0x01: "X * Y (RND)", 0x02: "MR + X * Y (RND)",
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0x03: "MR - X * Y (RND)", 0x04: "X * Y (SS)", 0x05: "X * Y (SU)",
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0x06: "X * Y (US)", 0x07: "X * Y (UU)", 0x08: "MR + X * Y (SS)",
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0x09: "MR + X * Y (SU)", 0x0a: "MR + X * Y (US)", 0x0b: "MR + X * Y (UU)",
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0x0c: "MR - X * Y (SS)", 0x0d: "MR - X * Y (SU)", 0x0e: "MR - X * Y (US)",
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0x0f: "MR - X * Y (UU)"
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}
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# Registers (RGP, Address)
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REG_MAP = {
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(0,0): "AX0", (0,1): "AX1", (0,2): "MX0", (0,3): "MX1",
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(0,4): "AY0", (0,5): "AY1", (0,6): "MY0", (0,7): "MY1",
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(0,8): "MR2", (0,9): "SR2", (0,10): "AR", (0,11): "SI",
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(0,12): "MR1", (0,13): "SR1", (0,14): "MR0", (0,15): "SR0",
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(1,0): "I0", (1,1): "I1", (1,2): "I2", (1,3): "I3",
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(1,4): "M0", (1,5): "M1", (1,6): "M2", (1,7): "M3",
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(1,8): "L0", (1,9): "L1", (1,10): "L2", (1,11): "L3",
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(1,12): "IMASK", (1,13): "IRPTL", (1,14): "ICNTL", (1,15): "STACKA",
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(2,0): "I4", (2,1): "I5", (2,2): "I6", (2,3): "I7",
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(2,4): "M4", (2,5): "M5", (2,6): "M6", (2,7): "M7",
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(2,8): "L4", (2,9): "L5", (2,10): "L6", (2,11): "L7",
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(2,12): "RSVD", (2,13): "CNTR", (2,14): "LPSTACKA", (2,15): "RSVD",
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(3,0): "ASTAT", (3,1): "MSTAT", (3,2): "SSTAT", (3,3): "LPSTACKP",
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(3,4): "CCODE", (3,5): "SE", (3,6): "SB", (3,7): "PX",
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(3,8): "DMPG1", (3,9): "DMPG2", (3,10): "IOPG", (3,11): "IJPG",
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(3,15): "STACKP"
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}
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# Condition Codes
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COND_CODES = {
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0x0: "EQ", 0x1: "NE", 0x2: "GT", 0x3: "LE", 0x4: "LT", 0x5: "GE",
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0x6: "AV", 0x7: "NOT AV", 0x8: "AC", 0x9: "NOT AC", 0xA: "SWCOND",
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0xB: "NOT SWCOND", 0xC: "MV", 0xD: "NOT MV", 0xE: "NOT CE", 0xF: "TRUE"
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}
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# XOP/YOP Code for ALU/MAC
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XOP_ALU = ["AX0", "AX1", "AR", "MR0", "MR1", "MR2", "SR0", "SR1"]
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YOP_ALU = ["AY0", "AY1", "AF", "0"] # 11 = 0
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XOP_MAC = ["MX0", "MX1", "AR", "MR0", "MR1", "MR2", "SR0", "SR1"]
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YOP_MAC = ["MY0", "MY1", "SR1", "0"]
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def get_reg_name(rgp, addr):
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return REG_MAP.get((rgp, addr), f"REG({rgp},{addr})")
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def decode_24(opcode):
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"""
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Decodes a 24-bit ADSP-219x instruction into its assembly string.
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"""
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# Type 1: 11xxxxxx (Compute | DregX←DM | DregY←PM)
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if (opcode >> 22) == 0b11:
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pd = (opcode >> 20) & 0x3
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dd = (opcode >> 18) & 0x3
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amf = (opcode >> 13) & 0x1F
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yop = (opcode >> 11) & 0x3
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xop = (opcode >> 8) & 0x7
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pmi = (opcode >> 6) & 0x3
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pmm = (opcode >> 4) & 0x3
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dmi = (opcode >> 2) & 0x3
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dmm = opcode & 0x3
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# Check for NOP multifunction (All AMF bits zero)
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if amf == 0:
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comp_str = "NOP"
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elif amf >= 0x10:
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comp_str = f"{AMF_ALU[amf]}({XOP_ALU[xop]}, {YOP_ALU[yop]})"
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else:
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comp_str = f"{AMF_MAC[amf]}({XOP_MAC[xop]}, {YOP_MAC[yop]})"
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return f"{comp_str}, {XOP_ALU[dd]} = DM(I{dmi} += M{dmm}), {YOP_ALU[pd]} = PM(I{pmi+4} += M{pmm+4})"
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# Type 3: Register read/write to immediate 16-bit address
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# Type 3 (Ireg/Mreg): 101 D addr16 IREG/MREG
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if (opcode >> 21) == 0b101:
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d = (opcode >> 20) & 0x1
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addr = (opcode >> 4) & 0xFFFF
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reg_code = opcode & 0xF
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reg_rgp = 1 if reg_code < 8 else 1 # Simple I/M mapping for type 3
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# In reality, Type 3 Ireg/Mreg uses a specific table. 0-7 are I0-I7, 8-15 are M0-M7.
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reg_name = f"I{reg_code}" if reg_code < 8 else f"M{reg_code-8}"
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if d: return f"DM(0x{addr:04X}) = {reg_name}"
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else: return f"{reg_name} = DM(0x{addr:04X})"
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# Type 6: 0100 Dreg Data16 (Dreg = Data16)
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if (opcode >> 20) == 0b0100:
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data = (opcode >> 4) & 0xFFFF
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dreg = opcode & 0xF
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reg_name = get_reg_name(0, dreg)
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return f"{reg_name} = 0x{data:04X}"
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# Type 10: 000110B addr13 COND (Jump relative)
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if (opcode >> 19) == 0b00011:
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type_bits = (opcode >> 17) & 0x7
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if type_bits == 0b110: # Type 10: 00011 0 delayed(B) ...
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b = (opcode >> 16) & 0x1
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addr = (opcode >> 4) & 0x1FFF
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cond = opcode & 0xF
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db = " (DB)" if b else ""
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cond_str = f"IF {COND_CODES[cond]} " if cond != 0xF else ""
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return f"{cond_str}JUMP 0x{addr:04X}{db}"
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elif type_bits == 0b100: # Type 12: Shift | Dreg ...
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pass # TODO
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# Type 30: 00000000 (NOP)
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if (opcode >> 12) == 0:
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return "NOP"
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return f"UNKNOWN (0x{opcode:06X})"
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def main():
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if len(sys.argv) < 2:
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print("Usage: adsp219x_disasm.py <rom.bin> [3|4 (packed|padded)]")
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return
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filename = sys.argv[1]
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format = int(sys.argv[2]) if len(sys.argv) > 2 else 3 # Default 3-byte packed
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with open(filename, "rb") as f:
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data = f.read()
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step = format
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for i in range(0, len(data), step):
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chunk = data[i:i+step]
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if len(chunk) < 3: break
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if format == 3:
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# Packed: B0 B1 B2
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opcode = (chunk[0] << 16) | (chunk[1] << 8) | chunk[2]
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else:
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# Padded 32-bit (assume leading zero or big-endian dump): 0x00 B0 B1 B2
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# or check your dump!
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opcode = (chunk[1] << 16) | (chunk[2] << 8) | chunk[3]
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addr = i // format
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print(f"0x{addr:04X}: 0x{opcode:06X} {decode_24(opcode)}")
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if __name__ == "__main__":
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main()
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BIN
docs/9x_ALUops.pdf
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docs/9x_ALUops.pdf
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docs/9x_flowops.pdf
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docs/9x_flowops.pdf
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docs/9x_flowops.txt
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2865
docs/9x_flowops.txt
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Load Diff
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docs/9x_intro.pdf
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docs/9x_intro.pdf
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361
docs/9x_intro.txt
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docs/9x_intro.txt
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1 INTRODUCTION
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Figure 1-0.
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Table 1-0.
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Listing 1-0.
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Purpose
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The ADSP-219x DSP Instruction Set Reference provides assembly syntax
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information for the ADSP-219x Digital Signal Processor (DSP). The syn-
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tax descriptions cover instructions that execute within the DSP’s processor
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core (processing elements, program sequencer, and data address genera-
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tors). For architecture and design information on the DSP, see the
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ADSP-219x/2191 DSP Hardware Reference.
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Audience
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DSP system designers and programmers who are familiar with signal pro-
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cessing concepts are the primary audience for this manual. This manual
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assumes that the audience has a working knowledge of microcomputer
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technology and DSP-related mathematics.
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DSP system designers and programmers who are unfamiliar with signal
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processing can use this manual, but should supplement this manual with
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other texts, describing DSP techniques.
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All readers, particularly programmers, should refer to the DSP’s develop-
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ment tools documentation for software development information. For
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additional suggested reading, see “For More Information About Analog
|
||||
Products” on page 1-6.
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ADSP-219x DSP Instruction Set Reference 1-1
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Contents Overview
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Contents Overview
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This reference presents instruction information organized by the type of
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the instruction. Instruction types relate to the machine language opcode
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for the instruction. On this DSP, the opcodes categorize the instructions
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by the portions of the DSP architecture that execute the instructions. The
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following chapters cover the different types of instructions:
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• “Instruction Set Summary” on page 2-1—This chapter provides a
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syntax summary of all instructions and describes the conventions
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that are used on the instruction reference pages.
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• “ALU Instructions” on page 3-1—These instruction specify opera-
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tions that occur in the DSP’s ALU.
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• “MAC Instructions” on page 4-1—These instructions specify oper-
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ations that occur in the DSP’s Multiply–Accumulator.
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• “Shifter Instructions” on page 5-1—These instructions specify
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operations that occur in the DSP’s Shifter.
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• “Multifunction Instructions” on page 6-1—These instructions
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specify parallel, single-cycle operations.
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• “Data Move Instructions” on page 7-1—These instructions specify
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memory and register access operations.
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• “Program Flow Instructions” on page 8-1—These instructions spec-
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ify program sequencer operations.
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• “Instruction Opcodes” on page 9-1—This chapter lists the instruc-
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tion encoding fields for all instructions.
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Each of the DSP’s instructions is specified in this text. The reference page
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for an instruction shows the syntax of the instruction, describes its func-
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tion, gives one or two assembly-language examples, and identifies fields of
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||||
its opcode. The instructions are referred to by type, ranging from 1 to 37.
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||||
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||||
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1-2 ADSP-219x DSP Instruction Set Reference
|
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Introduction
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||||
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These types correspond to the opcodes that ADSP-219x DSPs recognize,
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but are for reference only and have no bearing on programming.
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Some instructions have more than one syntactical form; for example,
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instruction “Type 9: Compute” on page 9-27 has many distinct forms.
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Many instructions can be conditional. These instructions are prefaced by
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IF COND; for example:
|
||||
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||||
If COND compute;
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||||
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||||
In a conditional instruction, the execution of the entire instruction is
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||||
based on the specified condition.
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||||
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||||
Development Tools
|
||||
The ADSP-219x is supported by VisualDSP®, an easy-to-use project
|
||||
management environment, comprised of an Integrated Development
|
||||
Environment (IDE) and Debugger. VisualDSP lets you manage projects
|
||||
from start to finish from within a single, integrated interface. Because the
|
||||
project development and debug environments are integrated, you can
|
||||
move easily between editing, building, and debugging activities.
|
||||
Flexible Project Management. The IDE provides flexible project manage-
|
||||
ment for the development of DSP applications. The IDE includes access
|
||||
to all the activities necessary to create and debug DSP projects. You can
|
||||
create or modify source files or view listing or map files with the IDE Edi-
|
||||
tor. This powerful Editor is part of the IDE and includes multiple
|
||||
language syntax highlighting, OLE drag and drop, bookmarks, and stan-
|
||||
dard editing operations such as undo/redo, find/replace, copy/paste/cut,
|
||||
and goto.
|
||||
Also, the IDE includes access to the C Compiler, C Runtime Library,
|
||||
Assembler, Linker, Loader, Simulator, and Splitter. You specify options
|
||||
for these Tools through Property Page dialogs. Property Page dialogs are
|
||||
easy to use, and make configuring, changing, and managing your projects
|
||||
|
||||
|
||||
|
||||
ADSP-219x DSP Instruction Set Reference 1-3
|
||||
Development Tools
|
||||
|
||||
|
||||
|
||||
|
||||
simple. These options control how the tools process inputs and generate
|
||||
outputs, and have a one-to-one correspondence to the tools’ command
|
||||
line switches. You can define these options once, or modify them to meet
|
||||
changing development needs. You can also access the Tools from the oper-
|
||||
ating system command line if you choose.
|
||||
Greatly Reduced Debugging Time. The Debugger has an easy-to-use,
|
||||
common interface for all processor simulators and emulators available
|
||||
through Analog Devices and third parties or custom developments. The
|
||||
Debugger has many features that greatly reduce debugging time. You can
|
||||
view C source interspersed with the resulting Assembly code. You can pro-
|
||||
file execution of a range of instructions in a program; set simulated watch
|
||||
points on hardware and software registers, program and data memory; and
|
||||
trace instruction execution and memory accesses. These features enable
|
||||
you to correct coding errors, identify bottlenecks, and examine DSP per-
|
||||
formance. You can use the custom register option to select any
|
||||
combination of registers to view in a single window. The Debugger can
|
||||
also generate inputs, outputs, and interrupts so you can simulate real
|
||||
world application conditions.
|
||||
Software Development Tools. Software Development Tools, which sup-
|
||||
port the ADSP-219x Family, allow you to develop applications that take
|
||||
full advantage of the DSP architecture, including shared memory and
|
||||
memory overlays. Software Development Tools include C Compiler, C
|
||||
Runtime Library, DSP and Math Libraries, Assembler, Linker, Loader,
|
||||
Simulator, and Splitter.
|
||||
C Compiler & Assembler. The C Compiler generates efficient code that is
|
||||
optimized for both code density and execution time. The C Compiler
|
||||
allows you to include Assembly language statements inline. Because of
|
||||
this, you can program in C and still use Assembly for time-critical loops.
|
||||
You can also use pretested Math, DSP, and C Runtime Library routines to
|
||||
help shorten your time to market. The ADSP-219x Family Assembly lan-
|
||||
guage is based on an algebraic syntax that is easy to learn, program, and
|
||||
|
||||
|
||||
|
||||
|
||||
1-4 ADSP-219x DSP Instruction Set Reference
|
||||
Introduction
|
||||
|
||||
|
||||
|
||||
|
||||
debug. The add instruction, for example, is written in the same manner as
|
||||
the actual equation (for example, AR = AX0 + AY0;).
|
||||
Linker & Loader. The Linker provides flexible system definition through
|
||||
Linker Description Files (.LDF). In a single LDF, you can define different
|
||||
types of executables for a single or multiprocessor system. The Linker
|
||||
resolves symbols over multiple executables, maximizes memory use, and
|
||||
easily shares common code among multiple processors. The Loader sup-
|
||||
ports creation of host (8- or 16-bit) port, SPI port, UART port, and
|
||||
PROM boot images. Along with the Linker, the Loader allows a variety of
|
||||
system configurations with smaller code and faster boot time.
|
||||
Simulator. The Simulator is a cycle-accurate, instruction-level simulator
|
||||
— allowing you to simulate your application in real time.
|
||||
3rd-Party Extensible. The VisualDSP environment enables third-party
|
||||
companies to add value using Analog Devices’ published set of Applica-
|
||||
tion Programming Interfaces (API). Third party products—runtime
|
||||
operating systems, emulators, high-level language compilers, multiproces-
|
||||
sor hardware —can interface seamlessly with VisualDSP thereby
|
||||
simplifying the tools integration task. VisualDSP follows the COM API
|
||||
format. Two API tools, Target Wizard and API Tester, are also available
|
||||
for use with the API set. These tools help speed the time-to-market for
|
||||
vendor products. Target Wizard builds the programming shell based on
|
||||
API features the vendor requires. The API tester exercises the individual
|
||||
features independently of VisualDSP. Third parties can use a subset of
|
||||
these APIs that meets their application needs. The interfaces are fully sup-
|
||||
ported and backward compatible.
|
||||
Further details and ordering information are available in the VisualDSP
|
||||
Development Tools data sheet. This data sheet can be requested from any
|
||||
Analog Devices sales office or distributor.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x DSP Instruction Set Reference 1-5
|
||||
For More Information About Analog Products
|
||||
|
||||
|
||||
|
||||
|
||||
For More Information About Analog
|
||||
Products
|
||||
Analog Devices is online on the internet at http://www.analog.com. Our
|
||||
Web pages provide information on the company and products, including
|
||||
access to technical information and documentation, product overviews,
|
||||
and product announcements.
|
||||
You may also obtain additional information about Analog Devices and its
|
||||
products in any of the following ways:
|
||||
• Visit our World Wide Web site at www.analog.com
|
||||
• FAX questions or requests for information to 1(781)461-3010.
|
||||
• Access the Computer Products Division File Transfer Protocol
|
||||
(FTP) site at ftp ftp.analog.com or ftp 137.71.23.21 or
|
||||
ftp://ftp.analog.com.
|
||||
|
||||
|
||||
|
||||
For Technical or Customer Support
|
||||
You can reach our Customer Support group in the following ways:
|
||||
• E-mail questions to dsp.support@analog.com or
|
||||
dsp.europe@analog.com (European customer support)
|
||||
|
||||
• Telex questions to 924491, TWX:710/394-6577
|
||||
• Cable questions to ANALOG NORWOODMASS
|
||||
• Contact your local ADI sales office or an authorized ADI distributor
|
||||
|
||||
|
||||
|
||||
|
||||
1-6 ADSP-219x DSP Instruction Set Reference
|
||||
Introduction
|
||||
|
||||
|
||||
|
||||
|
||||
• Send questions by mail to:
|
||||
Analog Devices, Inc.
|
||||
DSP Division
|
||||
One Technology Way
|
||||
P.O. Box 9106
|
||||
Norwood, MA 02062-9106
|
||||
USA
|
||||
|
||||
|
||||
|
||||
What’s New in This Manual
|
||||
This is the preliminary edition of the ADSP-219x DSP Instruction Set
|
||||
Reference. Summaries of changes between editions will start with the next
|
||||
edition.
|
||||
|
||||
|
||||
Related Documents
|
||||
For more information about Analog Devices DSPs and development
|
||||
products, see the following documents:
|
||||
• ADSP-2191 DSP Microcomputer Data Sheet
|
||||
• ADSP-219x/2191 DSP Hardware Reference
|
||||
• Getting Started Guide for VisualDSP & ADSP-219x Family DSPs
|
||||
• VisualDSP User's Guide for ADSP-219x Family DSPs
|
||||
• C Compiler & Library Manual for ADSP-219x Family DSPs
|
||||
• Assembler Manual for ADSP-219x Family DSPs
|
||||
• Linker & Utilities Manual for ADSP-219x Family DSPs
|
||||
All the manuals are included in the software distribution CD-ROM. To
|
||||
access these manuals, use the Help Topics command in the VisualDSP
|
||||
environment’s Help menu and select the Online Manuals book. From this
|
||||
|
||||
|
||||
|
||||
ADSP-219x DSP Instruction Set Reference 1-7
|
||||
Conventions
|
||||
|
||||
|
||||
|
||||
|
||||
Help topic, you can open any of the manuals, which are in Adobe Acrobat
|
||||
PDF format.
|
||||
|
||||
|
||||
Conventions
|
||||
The following are conventions that apply to all chapters. Note that addi-
|
||||
tional conventions, which apply only to specific chapters, appear
|
||||
throughout this document.
|
||||
|
||||
Table 1-1. Instruction set notation
|
||||
|
||||
Notation Meaning
|
||||
|
||||
UPPERCASE Explicit syntax—assembler keyword. (The assembler is case-
|
||||
insensitive.)
|
||||
|
||||
; A semicolon terminates an instruction line.
|
||||
|
||||
, A comma separates multiple, parallel instructions in the same
|
||||
instruction line.
|
||||
|
||||
// single line comment // or /* */ indicate comments or remarks that explain program code,
|
||||
/* multi line comment */ but that the assembler ignores. For more details, see the Assembler
|
||||
Manual for ADSP-219x Family DSPs.
|
||||
|
||||
| option1 | You must choose one of the items enclosed within two vertical bars.
|
||||
| option2 |
|
||||
|
||||
[ (DB) ] Brackets enclose an optional instruction component. The option’s
|
||||
syntax includes everything within the brackets, as shown. In this
|
||||
case, (DB) is the delayed branch option.
|
||||
|
||||
<imm#> Denotes an immediate value (data or address) of # bits.
|
||||
<data#>
|
||||
|
||||
COND Denotes a status condition.
|
||||
|
||||
|
||||
|
||||
|
||||
1-8 ADSP-219x DSP Instruction Set Reference
|
||||
Introduction
|
||||
|
||||
|
||||
|
||||
|
||||
Table 1-1. Instruction set notation (Cont’d)
|
||||
|
||||
Notation Meaning
|
||||
|
||||
TERM Denotes a loop termination condition. For details, see “Type 11: Do
|
||||
··· Until” on page 9-34.
|
||||
|
||||
Dreg Denotes an unrestricted (Group 0) data register used as either an x
|
||||
or y-input operand. For details, see “Core Registers” on page 7-2.
|
||||
|
||||
XOP Denotes a restricted data register used for the x-input operand in a
|
||||
compute instruction. For details, see “Input Registers” on page 3-2.
|
||||
|
||||
YOP Denotes a restricted data register used for the y-input operand in a
|
||||
compute operation. For details, see “Input Registers” on page 3-2.
|
||||
|
||||
Ireg DAG address register. Denotes an index register (I0–I7).
|
||||
|
||||
Mreg DAG address register. Denotes a modify register (M0–M7).
|
||||
|
||||
Lreg DAG address register. Denotes a length register (L0–L7).
|
||||
|
||||
Breg DAG address register. Denotes a base register (B0–B7).
|
||||
|
||||
(Ireg + Mreg) Indirect addressing mode. Denotes premodify addressing with no
|
||||
update. Same as (Mreg, Ireg) syntax.
|
||||
|
||||
(Ireg += Mreg) Indirect addressing mode. Denotes postmodify addressing with
|
||||
update. Same as (Ireg, Mreg) syntax.
|
||||
|
||||
0x Denotes number in hexidecimal format (0xFFFF).
|
||||
|
||||
h# Denotes number in hexidecimal format (h#FFFF).
|
||||
|
||||
b# Denotes number in binary format (b#0001000100010001).
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x DSP Instruction Set Reference 1-9
|
||||
Conventions
|
||||
|
||||
|
||||
|
||||
|
||||
1-10 ADSP-219x DSP Instruction Set Reference
|
||||
|
||||
BIN
docs/9x_is_IX.pdf
Normal file
BIN
docs/9x_is_IX.pdf
Normal file
Binary file not shown.
BIN
docs/9x_is_TC.pdf
Normal file
BIN
docs/9x_is_TC.pdf
Normal file
Binary file not shown.
BIN
docs/9x_iset.pdf
Normal file
BIN
docs/9x_iset.pdf
Normal file
Binary file not shown.
1021
docs/9x_iset.txt
Normal file
1021
docs/9x_iset.txt
Normal file
File diff suppressed because it is too large
Load Diff
BIN
docs/9x_mltops.pdf
Normal file
BIN
docs/9x_mltops.pdf
Normal file
Binary file not shown.
926
docs/9x_mltops.txt
Normal file
926
docs/9x_mltops.txt
Normal file
@@ -0,0 +1,926 @@
|
||||
4 MAC INSTRUCTIONS
|
||||
Figure 4-0.
|
||||
Table 4-0.
|
||||
Listing 4-0.
|
||||
|
||||
|
||||
|
||||
The instruction set provides MAC instructions for performing high-speed
|
||||
multiplication and multiply with cumulative add/subtract operations.
|
||||
MAC instructions include:
|
||||
• “Multiply” on page 4-8
|
||||
• “Multiply with Cumulative Add” on page 4-11
|
||||
• “Multiply with Cumulative Subtract” on page 4-14
|
||||
• “MAC Clear” on page 4-17
|
||||
• “MAC Round/Transfer” on page 4-19
|
||||
• “MAC Saturate” on page 4-21
|
||||
• “Generate MAC Status Only: NONE” on page 4-24
|
||||
This chapter describes the individual MAC instructions and the following
|
||||
related topics:
|
||||
• “MAC Input Registers” on page 4-2
|
||||
• “MAC Output Registers” on page 4-2
|
||||
• “Data Format Options” on page 4-3
|
||||
• “Status Flags” on page 4-7
|
||||
For details on condition codes and data input and output registers, see
|
||||
“Condition Codes” on page 9-11 and “Core Register Codes” on page
|
||||
9-13.
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-1
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
MAC Input Registers
|
||||
All unconditional, single-function multiply and multiply with accumula-
|
||||
tive add or subtract instructions can use any DREG data register for the x
|
||||
and y input operands (for details, see “Core Register Codes” on page
|
||||
9-13). So, the program can use, for example, the ALU registers for the
|
||||
multiplication or shifter operations, without issuing a separate data move
|
||||
instruction. This capability simplifies register allocation in algorithm cod-
|
||||
ing. For example, using the DSP’s dual accumulator:
|
||||
SR = SR + MX0 * MY0 (SS);
|
||||
|
||||
But in multifunction operations, you can use only certain registers for the
|
||||
x-input operand (AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1) and the y-input
|
||||
operand ( MY0, MY1, SR1, 0).
|
||||
All conditional MAC instructions must use the restricted xop and yop data
|
||||
registers for the x and y input operands, or an xop register for the x-input
|
||||
and 0 for the y-input.
|
||||
|
||||
MAC Output Registers
|
||||
All MAC instructions can use the multiplier MR output registers or the
|
||||
shifter SR output registers to receive the result of a multiplier operation.
|
||||
Availability of the shifter SR output registers for multiplier operations pro-
|
||||
vides dual accumulator functionality.
|
||||
When MR is the result register, results are directly available from MR0, MR1,
|
||||
or MR2 as the x-input operand into the very next multiplier operation.
|
||||
MR = MR + AX0 * AX0 (SS);
|
||||
|
||||
When SR is the result register, the 16-bit value in SR1 (bits 31:16 of the
|
||||
40-bit result) is directly available as the y-input operand into the very next
|
||||
multiplier operation. This functionality is most useful when shifting the
|
||||
|
||||
|
||||
|
||||
|
||||
4-2 ADSP-219x Instruction Set Reference
|
||||
Data Format Options
|
||||
|
||||
|
||||
|
||||
|
||||
results of a multiply/accumulate operation since it decreases the number
|
||||
of required data moves.
|
||||
SR = SR + AX0 * AY0 (SS);
|
||||
SR = SR + SR1 * AY0 (SS);
|
||||
|
||||
|
||||
Data Format Options
|
||||
Multiplier operations require the instruction to specify the data format of
|
||||
the input operands (either signed or unsigned) or specify that the multi-
|
||||
plier rounds (RND) the product of two signed operands.
|
||||
All data format options, except the round option ( RND), which affects the
|
||||
product stored in the result register, specify the format of both input oper-
|
||||
ands in x/y order. The data format options are:
|
||||
• (RND) Round value in result register.
|
||||
When overflow occurs, rounds the product to the most significant
|
||||
twenty-four bits—SR2/SR1 or MR2/MR1 represent the rounded 24-bit
|
||||
result. Otherwise, rounds bits 31:16 to sixteen bits—MR1 or SR1 con-
|
||||
tain the rounded 16-bit result.
|
||||
With (RND) selected, the multiplier considers both input operands
|
||||
signed (twos complement). If the DSP is in fractional mode
|
||||
(MSTAT:M_MODE = 0), the multiplier rounds the result after adjusting
|
||||
for fractional data format. For details, see “Numeric Format Modes”
|
||||
on page 4-6.
|
||||
The DSP provides two rounding modes, biased and unbiased, to
|
||||
support a variety of application algorithms. For details, see “Round-
|
||||
ing Modes” on page 4-4.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-3
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
• (SS) Both input operands are signed numbers. Signed numbers
|
||||
are in twos complement format.
|
||||
You use this option to multiply two signed single-precision numbers
|
||||
or to multiply the upper portions of two signed multiprecision
|
||||
numbers.
|
||||
• (SU) X-input operand is signed; y-input operand is unsigned.
|
||||
You use this option to multiply a signed single-precision number by
|
||||
an unsigned single-precision number.
|
||||
• (US) X-input operand is unsigned; y-input operand is signed.
|
||||
You use this option to multiply an unsigned single-precision num-
|
||||
ber by a signed single-precision number.
|
||||
• (UU) Both input operands are unsigned numbers. Unsigned num-
|
||||
bers are in ones complement format.
|
||||
You use this option to multiply two unsigned single-precision num-
|
||||
bers or to multiply the lower portions of two signed multiprecision
|
||||
numbers.
|
||||
|
||||
Rounding Modes
|
||||
Rounding operates on the boundary between bits 15 and 16 of the 40-bit
|
||||
adder result. The multiplier directs the rounded output to either the MR
|
||||
or the SR result registers.
|
||||
The ADSP-219x provides two modes for rounding. The rounding algo-
|
||||
rithm is the same for both modes, but the final results can differ when the
|
||||
product equals the midway value (MR0 = 0x8000).
|
||||
In both methods, the multiplier adds 1 to value of bit 15 in the adder
|
||||
chain. But when MR0 = 0x8000, the multiplier forces bit 16 in the result
|
||||
output to 0. Although applied on every rounding operation, the result of
|
||||
this algorithm is evident only when MR0 = 0x8000 in the adder chain.
|
||||
|
||||
|
||||
|
||||
4-4 ADSP-219x Instruction Set Reference
|
||||
Data Format Options
|
||||
|
||||
|
||||
|
||||
|
||||
The rounding mode determines the final result. The BIASRND bit in the
|
||||
ICNTL register selects the mode. BIASRND = 0 selects unbiased rounding,
|
||||
and BIASRND = 1 selects biased rounding.
|
||||
• Unbiased rounding Default mode. Rounds up only when
|
||||
MR1/SR1 set to an odd value; otherwise,
|
||||
rounds down. Yields a zero large-sample bias.
|
||||
• Biased rounding Always rounds up when MR0/SR0 is set to
|
||||
0x8000.
|
||||
|
||||
Table 4-1 shows the results of rounding for both modes.
|
||||
|
||||
Table 4-1. MR result values
|
||||
|
||||
MR Value before RND Biased RND Result Unbiased RND Result
|
||||
|
||||
00-0000-8000 00-0001-0000 00-0000-0000
|
||||
|
||||
00-0001-8000 00-0002-0000 00-0002-0000
|
||||
|
||||
00-0000-8001 00-0001-0001 00-0001-0001
|
||||
|
||||
00-0001-8001 00-0002-0001 00-0002-0001
|
||||
|
||||
00-0000-7FFF 00-0000-FFFF 00-0000-FFFF
|
||||
|
||||
00-0001-7FFF 00-0001-FFFF 00-0001- FFFF
|
||||
|
||||
|
||||
Unbiased rounding, preferred for most algorithms, yields a zero large-sam-
|
||||
ple bias, assuming uniformly distributed values. Biased rounding supports
|
||||
efficient implementation of bit-specified algorithms, such as GSM speech
|
||||
compression routines.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-5
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Numeric Format Modes
|
||||
The multiplier can operate on integers or fractions. The M_MODE bit in the
|
||||
MSTAT register selects the mode. M_MODE = 0 selects fractional mode, and
|
||||
M_MODE = 1 selects integer mode.
|
||||
|
||||
The mode determines whether the multiplier shifts the product before
|
||||
adding or subtracting it from the result register.
|
||||
• Integer mode 16.0 integer format
|
||||
The LSB of the 32-bit product is aligned with the LSB of MR0/SR0.
|
||||
In multiply and accumulate operations, the multiplier sign-extends
|
||||
the 32-bit product (8 bits) then adds or subtracts that value from the
|
||||
result register to form the new 40-bit result.
|
||||
The multiplier sets the MV/SV overflow bit when the result falls out-
|
||||
side the range of −1 to +1−231.
|
||||
• Fractional mode 1.15 fraction format
|
||||
Fractions range from −1 to +1−215. The MSB of the product is
|
||||
aligned with the MSB of MR1/SR1. MR1-0/SR1-0 hold a 32-bit frac-
|
||||
tion (1.31 format) in the range of −1 to +1−231, while MR2/SR2 con-
|
||||
tains the eight sign-extended bits. In total, the MR/SR registers
|
||||
contains a fraction in 9.31 format.
|
||||
In multiply and accumulate operations, the multiplier adjusts the
|
||||
format of the 32-bit product before adding or subtracting it from
|
||||
the result register. To do so, the multiplier sign-extends the product
|
||||
(7 bits), shifts it one bit to the left, and then adds or subtracts that
|
||||
value from the result register to form the new 40-bit result.
|
||||
The multiplier sets the MV/SV overflow bit when the result falls out-
|
||||
side the range of −1 to +1−231.
|
||||
|
||||
|
||||
|
||||
|
||||
4-6 ADSP-219x Instruction Set Reference
|
||||
Status Flags
|
||||
|
||||
|
||||
|
||||
|
||||
Status Flags
|
||||
Two status flags in the ASTAT register record the status of multiplier opera-
|
||||
tions. MV = 1 records an overflow or underflow state when MR is the
|
||||
specified result register, and SV = 1 records an overflow or underflow state
|
||||
when SR is the specified result register.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-7
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Multiply
|
||||
|
||||
MR = DREG1 * DREG2 ( RND ) ;
|
||||
SR SS
|
||||
SU
|
||||
US
|
||||
UU
|
||||
|
||||
|
||||
[IF COND] MR = XOP * YOP ( RND ) ;
|
||||
SR XOP SS
|
||||
SU
|
||||
US
|
||||
UU
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Multiplies the input operands and stores the result in the specified result
|
||||
register. Optionally, inputs may be signed or unsigned, and output may be
|
||||
rounded. For more information on input and output options, see “Data
|
||||
Format Options” on page 4-3.
|
||||
If execution is based on a condition, the multiplier performs the multipli-
|
||||
cation only if the condition evaluates true, and it performs a NOP operation
|
||||
if the condition evaluates false. Omitting the condition forces uncondi-
|
||||
tional execution of the instruction.
|
||||
|
||||
|
||||
|
||||
|
||||
4-8 ADSP-219x Instruction Set Reference
|
||||
Multiply
|
||||
|
||||
|
||||
|
||||
|
||||
INPUT
|
||||
|
||||
For the unconditional form of this instruction, you can use any of these
|
||||
data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
For the conditional form of this instruction, the input operands are
|
||||
restricted. Valid XOP and YOP registers are:
|
||||
|
||||
Xops Yops
|
||||
|
||||
AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1 MY0, MY1, SR1, 0
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
MR Multiplier result register. Results are directly available for x input
|
||||
only in the next conditional ALU, MAC, or shifter operation or as
|
||||
either x or y input in the next unconditional ALU, MAC, or shifter
|
||||
operation.
|
||||
SR Multiplier feedback register. Results are directly available for either
|
||||
x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU,
|
||||
MAC, or shifter operation or as either x or y input in the next
|
||||
unconditional ALU, MAC, or shifter operation.
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-9
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
This instruction provides a squaring operation (XOP*XOP and DREG1*DREG1)
|
||||
that performs single-cycle X2 and ΣX2 functions. In squaring operations,
|
||||
you must use the same register for both x-input operands.
|
||||
You cannot use DREG form of the multiply instruction in multifunction
|
||||
instructions.
|
||||
EXAMPLES
|
||||
|
||||
MR = AY0 * SI (RND); /* mult DREGs, round result */
|
||||
SR = AX0 * MX1 (SS); /* mult DREGs, signed inputs */
|
||||
|
||||
IF MV MR = MX0 * MY0 (SU); /* mult signed X, unsigned Y */
|
||||
CCODE = 0x09; NOP; /* set CCODE for SV condition */
|
||||
IF SWCOND SR = MR0 * SR1 (UU); /* mult unsigned X and Y */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
4-10 ADSP-219x Instruction Set Reference
|
||||
Multiply with Cumulative Add
|
||||
|
||||
|
||||
|
||||
|
||||
Multiply with Cumulative Add
|
||||
|
||||
MR = MR + DREG1 * DREG2 ( RND ) ;
|
||||
SR = SR SS
|
||||
SU
|
||||
US
|
||||
UU
|
||||
|
||||
|
||||
[IF COND] MR = MR + XOP * YOP ( RND ) ;
|
||||
SR = SR YOP XOP SS
|
||||
SU
|
||||
US
|
||||
UU
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Multiplies the input operands, adds the product to the current contents of
|
||||
the MR or SR register, and then stores the sum in the corresponding result
|
||||
register. Optionally, inputs may be signed or unsigned, and output may be
|
||||
rounded. For more information on input and output options, see “Data
|
||||
Format Options” on page 4-3.
|
||||
If execution is based on a condition, the multiplier performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-11
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
INPUT
|
||||
|
||||
For the unconditional form of this instruction, you can use any of these
|
||||
data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
For the conditional form of this instruction, the input operands are
|
||||
restricted. Valid XOP and YOP registers are:
|
||||
|
||||
Xops Yops
|
||||
|
||||
AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1 MY0, MY1, SR1, 0
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
MR Multiplier result register. Results are directly available for x input
|
||||
only in the next conditional ALU, MAC, or shifter operation or as
|
||||
either x or y input in the next unconditional ALU, MAC, or shifter
|
||||
operation.
|
||||
SR Multiplier feedback register. Results are directly available for either
|
||||
x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU,
|
||||
MAC, or shifter operation or as either x or y input in the next
|
||||
unconditional ALU, MAC, or shifter operation.
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
|
||||
|
||||
4-12 ADSP-219x Instruction Set Reference
|
||||
Multiply with Cumulative Add
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
This instruction provides a squaring operation (xop*xop and DREG*DREG)
|
||||
that performs single-cycle X2 and ΣX2 functions. In squaring operations,
|
||||
you must use the same register for both x-input operands.
|
||||
You cannot use unconditional (Dreg) form of the multiply instruction in
|
||||
multifunction instructions.
|
||||
EXAMPLES
|
||||
|
||||
MR = MR + AX0 * SI (RND); /* mult DREGs, rnd output, sum */
|
||||
SR = SR + AX1 * MX0 (SS); /* mult DREGs, sign input, sum */
|
||||
|
||||
IF MV MR = MR + MR0 * MY0 (SU);
|
||||
/* mult X/Yops, un/sign in, sum */
|
||||
IF MV MR = MR + MR2 * MX1 (UU);
|
||||
/* mult X/Yops, unsign in, sum */
|
||||
CCODE = 0x09; NOP; /* set CCODE for SV condition */
|
||||
IF SWCOND SR=SR+SR0*MY0 (US);
|
||||
/* mult X/Yops, un/sign in, sum */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-13
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Multiply with Cumulative Subtract
|
||||
|
||||
MR = MR − DREG1 * DREG2 ( RND ) ;
|
||||
SR = SR SS
|
||||
SU
|
||||
US
|
||||
UU
|
||||
|
||||
|
||||
[IF COND] MR = MR − XOP * YOP ( RND ) ;
|
||||
SR = SR YOP XOP SS
|
||||
SU
|
||||
US
|
||||
UU
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Multiplies the input operands, subtracts the product from the current
|
||||
contents of the MR or SR register, and then stores the result in the corre-
|
||||
sponding destination register. Optionally, inputs may be signed or
|
||||
unsigned, and output may be rounded. For more information on input
|
||||
and output options, see “Data Format Options” on page 4-3.
|
||||
If execution is based on a condition, the multiplier performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
|
||||
|
||||
|
||||
|
||||
4-14 ADSP-219x Instruction Set Reference
|
||||
Multiply with Cumulative Subtract
|
||||
|
||||
|
||||
|
||||
|
||||
INPUT
|
||||
|
||||
For the unconditional form of this instruction, you can use any of these
|
||||
data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
For the conditional form of this instruction, the input operands are
|
||||
restricted. Valid XOP and YOP registers are:
|
||||
|
||||
Xops Yops
|
||||
|
||||
AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1 MY0, MY1, SR1, 0
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
MR Multiplier result register. Results are directly available for x input
|
||||
only in the next conditional ALU, MAC, or shifter operation or as
|
||||
either x or y input in the next unconditional ALU, MAC, or shifter
|
||||
operation.
|
||||
SR Multiplier feedback register. Results are directly available for either
|
||||
x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU,
|
||||
MAC, or shifter operation or as either x or y input in the next
|
||||
unconditional ALU, MAC, or shifter operation.
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-15
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
This instruction provides a squaring operation (xop*xop and DREG*DREG)
|
||||
that performs single-cycle X2 and ΣX2 functions. In squaring operations,
|
||||
you must use the same register for both x input operands.
|
||||
You cannot use unconditional (Dreg) form of the multiply instruction in
|
||||
multifunction instructions.
|
||||
EXAMPLES
|
||||
|
||||
MR = MR - AX0 * SI (RND); /* mult DREGs, rnd output, sub */
|
||||
SR = SR - AX1 * MX0 (SS); /* mult DREGs, sign input, sub */
|
||||
|
||||
IF MV MR = MR - MR0 * MY0 (SU);
|
||||
/* mult X/Yops, un/sign in, sub */
|
||||
IF MV MR = MR - MR2 * MX1 (UU);
|
||||
/* mult X/Yops, unsign in, sub */
|
||||
CCODE = 0x09; NOP; /* set CCODE for SV condition */
|
||||
IF SWCOND SR=SR-SR0*MY0 (US);
|
||||
/* mult X/Yops, un/sign in, sub */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
4-16 ADSP-219x Instruction Set Reference
|
||||
MAC Clear
|
||||
|
||||
|
||||
|
||||
|
||||
MAC Clear
|
||||
|
||||
[IF COND] MR = 0 ;
|
||||
SR
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Sets the specified register to 0.
|
||||
If execution is based on a condition, the multiplier performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if
|
||||
the condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
INPUT
|
||||
|
||||
This instruction is a special case of xop * yop with the y-input operand set
|
||||
to 0.
|
||||
OUTPUT
|
||||
|
||||
MR Multiplier result register. Results are directly available for x input
|
||||
only in the next conditional ALU, MAC, or shifter operation or as
|
||||
either x or y input in the next unconditional ALU, MAC, or shifter
|
||||
operation.
|
||||
SR Multiplier feedback register. Results are directly available for either
|
||||
x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU,
|
||||
MAC, or shifter operation or as either x or y input in the next
|
||||
unconditional ALU, MAC, or shifter operation.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-17
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
MV (cleared if MR used), SV (cleared if SR used) AZ, AN, AV, AC, AS, AQ, SS
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
See description in “function” on page 4-17.
|
||||
EXAMPLES
|
||||
|
||||
MR = 0; /* clears MR */
|
||||
SR = 0; /* clears SR */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
4-18 ADSP-219x Instruction Set Reference
|
||||
MAC Round/Transfer
|
||||
|
||||
|
||||
|
||||
|
||||
MAC Round/Transfer
|
||||
|
||||
[IF COND] MR = MR (RND) ;
|
||||
|
||||
|
||||
[IF COND] SR = SR (RND) ;
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Performs a multiply with cumulative add operation in which the y-input
|
||||
operand is 0 and the zero-product is added to the specified result register.
|
||||
Rounding (RND) directs the multiplier to round the entire 40-bit value
|
||||
stored in the result register, MR or SR.
|
||||
If execution is based on a condition, the multiplier performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
INPUT
|
||||
|
||||
This instruction is a special case of MR|SR + xop * yop with the y-input
|
||||
operand set to 0.
|
||||
OUTPUT
|
||||
|
||||
MR Multiplier result register. Results are directly available for x input
|
||||
only in the next conditional ALU, MAC, or shifter operation or as
|
||||
either x or y input in the next unconditional ALU, MAC, or shifter
|
||||
operation.
|
||||
SR Multiplier feedback register. Results are directly available for either
|
||||
x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU,
|
||||
MAC, or shifter operation or as either x or y input in the next
|
||||
unconditional ALU, MAC, or shifter operation.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-19
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
MV (if MR used), SV (if SR used) AZ, AN, AV, AC, AS, AQ, SS
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The BIASRND bit in the ICNTL register determines the rounding mode.
|
||||
Refer to the section “Rounding Modes” on page 4-4 for more informa-
|
||||
tion. For a complete description of the MAC Round/ Transfer
|
||||
instruction, see the section “function” on page 4-19.
|
||||
EXAMPLES
|
||||
|
||||
MR = MR (RND); /* round MR */
|
||||
IF EQ SR = SR (RND); /* round SR */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
4-20 ADSP-219x Instruction Set Reference
|
||||
MAC Saturate
|
||||
|
||||
|
||||
|
||||
|
||||
MAC Saturate
|
||||
|
||||
SAT MR ;
|
||||
|
||||
|
||||
SAT SR ;
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Tests the MV (MAC overflow) or SV (shifter overflow) bit in the ASTAT reg-
|
||||
ister. If set ( 1), the multiplier saturates the low-order (31:0) bits of the
|
||||
40-bit MR or SR register; otherwise, the multiplier performs a NOP
|
||||
operation.
|
||||
INPUT
|
||||
|
||||
None.
|
||||
OUTPUT
|
||||
|
||||
MR Multiplier result register. Results are directly available for x input
|
||||
only in the next conditional ALU, MAC, or shifter operation or as
|
||||
either x or y input in the next unconditional ALU, MAC, or shifter
|
||||
operation.
|
||||
SR Multiplier feedback register. Results are directly available for either
|
||||
x ( SR0 and SR1) or y (SR1 only) input in the next conditional ALU,
|
||||
MAC, or shifter operation or as either x or y input in the next
|
||||
unconditional ALU, MAC, or shifter operation.
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
AZ, AN, AV, AC, AS, AQ, SS, MV, SV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-21
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The MAC saturation instruction provides control over a multiplication
|
||||
result that has overflowed or underflowed. It saturates the value in the
|
||||
specified register only for the cycle in which it executes. It does not enable
|
||||
a mode that continuously saturates results until disabled, like the ALU.
|
||||
Used at the end of a series of multiply and accumulate operations, the sat-
|
||||
uration instruction prevents the accumulator from overflowing.
|
||||
For every operation it performs, the multiplier generates an overflow sta-
|
||||
tus signal MV (SV when SR is the specified result register), which is recorded
|
||||
in the ASTAT status register. MV = 1 when the accumulator result, inter-
|
||||
preted as a signed (twos complement) number, crosses the 32-bit
|
||||
boundary, spilling over from MR1 into MR2. That is, the multiplier sets
|
||||
MV = 1 when the upper nine bits in MR are anything other than all 0s or all
|
||||
1s. Otherwise, it sets MV = 0.
|
||||
|
||||
The operation invoked by the saturation instruction depends on the over-
|
||||
flow status bit MV (or SV) and the MSB of MR2, which appear in Table 4-2.
|
||||
If MV/SV = 0, no saturation occurs. When MV/SV = 1, the multiplier exam-
|
||||
ines the MSB of MR2 to determine whether the result has overflowed or
|
||||
underflowed. If the MSB = 0, the result has overflowed, and the multiplier
|
||||
saturates the MR register, setting it to the maximum positive value. If the
|
||||
MSB = 1, the result has underflowed, and the multiplier saturates the MR
|
||||
register, setting it to the maximum negative value.
|
||||
|
||||
Table 4-2. Saturation Status Bits & Result Registers
|
||||
|
||||
MV/SV MSB of MR2/SR2 MR/SR Results
|
||||
|
||||
0 0 No change.
|
||||
|
||||
0 1 No change.
|
||||
|
||||
1 0 00000000 0111111111111111 1111111111111111
|
||||
|
||||
1 1 11111111 1000000000000000 0000000000000000
|
||||
|
||||
|
||||
|
||||
|
||||
4-22 ADSP-219x Instruction Set Reference
|
||||
MAC Saturate
|
||||
|
||||
|
||||
|
||||
|
||||
Do not permit the result to overflow beyond the MSB of MR2. Otherwise,
|
||||
the true sign bit of the result is irretrievably lost, and saturation may not
|
||||
produce a correct result. To reach this state, however, takes more than 255
|
||||
overflows (MV type).
|
||||
EXAMPLES
|
||||
|
||||
SAT MR; /* saturate MR */
|
||||
SAT SR; /* saturate SR */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-23
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Generate MAC Status Only: NONE
|
||||
|
||||
[NONE =] <MAC Operation> ;
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Performs the indicated unconditional MAC operation but does not load
|
||||
the results into the MR or SR result registers. Generates MAC status flags
|
||||
only. You can use this instruction to set MAC status without disturbing
|
||||
the contents of the MR and SR result registers.
|
||||
INPUT
|
||||
|
||||
XOP Limits the registers for the x input operand. Valid XOP registers are:
|
||||
|
||||
Xops
|
||||
|
||||
AR, MX0, MX1, MR0, MR1, MR2, SR0, SR1
|
||||
|
||||
|
||||
YOP Limits the registers for the x input operand. Valid YOP registers are:
|
||||
|
||||
Yops
|
||||
|
||||
MY0, MY1, SR1, 0
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
None. Generates MAC status flags only.
|
||||
|
||||
|
||||
|
||||
|
||||
4-24 ADSP-219x Instruction Set Reference
|
||||
Generate MAC Status Only: NONE
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
MV AZ, AN, AV, AC, AS, AQ, SS, SV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
You can use any unconditional MAC operation to generate MAC status
|
||||
flags.
|
||||
EXAMPLES
|
||||
|
||||
MX0 * MY0; /* generate status from mult */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 4-25
|
||||
MAC Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
4-26 ADSP-219x Instruction Set Reference
|
||||
|
||||
BIN
docs/9x_moveops.pdf
Normal file
BIN
docs/9x_moveops.pdf
Normal file
Binary file not shown.
2598
docs/9x_moveops.txt
Normal file
2598
docs/9x_moveops.txt
Normal file
File diff suppressed because it is too large
Load Diff
BIN
docs/9x_multiops.pdf
Normal file
BIN
docs/9x_multiops.pdf
Normal file
Binary file not shown.
791
docs/9x_multiops.txt
Normal file
791
docs/9x_multiops.txt
Normal file
@@ -0,0 +1,791 @@
|
||||
6 MULTIFUNCTION
|
||||
INSTRUCTIONS
|
||||
Figure 6-0.
|
||||
Table 6-0.
|
||||
Listing 6-0.
|
||||
|
||||
The instruction set provides multifunction instructions—multiple
|
||||
instructions within a single instruction cycle. Multifunction instructions
|
||||
can perform (in a single cycle) computations in parallel with data move
|
||||
operations. Multifunction instructions are combinations of single instruc-
|
||||
tions delimited with commas and ended with a semicolon, as in:
|
||||
AR = AX0 - AY0, AX0 = MR1; /* ALU sub and reg.-to-reg. move */
|
||||
|
||||
These operations are the basis for all high-performance DSP functions and
|
||||
take advantage of the DSP’s inherent parallelism. Multifunction opera-
|
||||
tions include:
|
||||
• “Compute with Dual Memory Read” on page 6-3
|
||||
• “Dual Memory Read” on page 6-7
|
||||
• “Compute with Memory Read” on page 6-10
|
||||
• “Compute with Memory Write” on page 6-14
|
||||
• “Compute with Register to Register Move” on page 6-18
|
||||
This chapter describes each of the multifunction instructions and the
|
||||
order of execution of multifunction operations.
|
||||
Multifunction instructions combine compute operations with data move
|
||||
operations. The multifunction combinations have no status flags specifi-
|
||||
cally associated with them, but the DSP does update the status flags for
|
||||
the computations that appear within multifunction instructions. For
|
||||
details, see “Arithmetic Status (ASTAT) Register” on page 2-5.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-1
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Order of Execution of Multifunction Operations
|
||||
The DSP reads registers and memory at the beginning of the processor
|
||||
pipeline and writes them at the end of it. Normal instruction syntax, read
|
||||
from left to right, implies this functional ordering. For example:
|
||||
a. MR = MR + MX0 * MY0(UU), MX0 = DM(I0 += M0), MY0 = PM(I4 += M4);
|
||||
b. DM(I0 += M0) = AR, AR = AX0 + AY0;
|
||||
c. AR = AX0 - AY0, AX0 = MR1;
|
||||
|
||||
This means that, for memory reads, the DSP executes the computation
|
||||
first, using the current value of the input data registers, and then transfers
|
||||
new data from memory or from another data register, overwriting the con-
|
||||
tents of the data registers (a and c). For memory writes, the DSP transfers
|
||||
the current value from the data register to memory first, and then over-
|
||||
writes the data register with the result of the computation (b).
|
||||
Even if you alter the order of the operations in your code, execution
|
||||
occurs in the correct order; the assembler issues a warning (if enabled), but
|
||||
results are correct at the opcode level. For example:
|
||||
MX0 = DM(I0 += M0), MY0 = PM(I4 += M4), MR = MR + MX0 * MY0(UU);
|
||||
|
||||
The altered order of operations appears to reverse the order in which the
|
||||
DSP executes the operations, but the DSP always executes instructions
|
||||
using read-first/write-last logic.
|
||||
The DSP’s read-first/write-last logic enables you to use the same data reg-
|
||||
ister in more than one multifunction operation. The same data register
|
||||
can serve as an input operand into the computation and as the destination
|
||||
or source register for a data move operation. However, except for the com-
|
||||
pute with memory write instruction, the same register cannot serve as
|
||||
destination for more than one multifunction operation. Doing so gener-
|
||||
ates unpredictable and erroneous results.
|
||||
|
||||
|
||||
|
||||
|
||||
6-2 ADSP-219x Instruction Set Reference
|
||||
Compute with Dual Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
Compute with Dual Memory Read
|
||||
|
||||
<ALU> , AX0 = DM( I0 += M0 ), AY0 = PM( I4 += M4 );
|
||||
<MAC> AX1 I1 M1 AY1 I5 M5
|
||||
MX0 I2 M2 MY0 I6 M6
|
||||
MX1 I3 M3 MY1 I7 M7
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Combines an ALU or MAC operation with a read from memory over the
|
||||
16-bit DM data bus and another read from memory over the 24-bit PM
|
||||
data bus. The restricted register forms—using XOP and YOP registers, not the
|
||||
DREG register file—of all ALU or MAC instructions are supported, except
|
||||
for the MAC saturate instruction and the divide primitives DIVS and DIVQ.
|
||||
Also, the multifunction ALU and MAC instructions may not use condi-
|
||||
tional (IF) options.
|
||||
The compute operation executes first, using the current contents of the
|
||||
data registers as input operands. Then the memory read operations exe-
|
||||
cute, overwriting the contents of the destination data registers with new
|
||||
data from memory.
|
||||
The destination of both memory read operations is an ALU or MAC data
|
||||
register. The DM bus read loads an ALU or MAC XOP register, and the
|
||||
PM bus read loads an ALU or MAC YOP register. The memory data is
|
||||
always right-justified in the destination data register.
|
||||
INPUT
|
||||
|
||||
The input operands for the compute operation are specific to the particu-
|
||||
lar operation. For details, see the compute instruction’s individual
|
||||
description.
|
||||
• For MAC operations, see “MAC Instructions” on page 4-1.
|
||||
• For ALU operations, see “ALU Instructions” on page 3-1.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-3
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Both data move operations use two DAG registers, index (Ireg) and mod-
|
||||
ify (Mreg), to generate memory addresses—DAG1 registers for the DM bus
|
||||
access, and DAG2 registers for the PM bus access. For details on DAG reg-
|
||||
isters and data addressing, see “Data Move Instructions” on page 7-1.
|
||||
• DM/DAG1 I0, I1, I2, or I3 (index registers)
|
||||
M0, M1, M2, or M3 (modify registers)
|
||||
|
||||
• PM/DAG2 I4, I5, I6, or I7 (index registers)
|
||||
M4, M5, M6, or M7 (modify registers)
|
||||
|
||||
|
||||
! You can use any index register with any modify register from the
|
||||
same DAG. You cannot pair a DAG1 register with a DAG2 register.
|
||||
OUTPUT
|
||||
|
||||
The result register for the compute operation is always the computation
|
||||
unit’s result registers.
|
||||
AR ALU operations
|
||||
MR MAC operations
|
||||
|
||||
! instruction.
|
||||
is not a MAC result register for this multifunction
|
||||
SR
|
||||
|
||||
|
||||
|
||||
The destination register for both data move operations is an ALU or MAC
|
||||
data register—an XOP register for the DM bus access and a YOP register for
|
||||
the PM bus access.
|
||||
XOP register: AX0, AX1, MX0, or MX1
|
||||
|
||||
YOP register: AY0, AY1, MY0, or MY1
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
The status flags generated as a result of the computation depends on the
|
||||
compute operation the instruction performs.For more information, see
|
||||
the status flags section of the computation’s reference page.
|
||||
|
||||
|
||||
|
||||
6-4 ADSP-219x Instruction Set Reference
|
||||
Compute with Dual Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The memory read operations use register indirect addressing with post-
|
||||
modify (Ireg += Mreg). For linear indirect addressing, you must initialize
|
||||
the Lx register of the corresponding Ireg register to 0. For circular indirect
|
||||
addressing, you must set the buffer’s length and base address with the cor-
|
||||
responding Lreg and Breg registers. For more information on addressing,
|
||||
see the ADSP-219x/2191 DSP Hardware Reference.
|
||||
The DM() reference uses the 16-bit DM data bus, and the PM() reference uses
|
||||
the 24-bit PM data bus. For PM data moves, the destination data register
|
||||
receives the sixteen MSBs from 24-bit memory, and the PX register catches
|
||||
the eight LSBs. To use all twenty-four bits of the memory data, you must
|
||||
transfer the eight LSBs from PX to another data register. Otherwise, the
|
||||
eight LSBs will be lost.
|
||||
The address of the access, not the PM() or DM() reference, selects the mem-
|
||||
ory bank. So, the DM reference could access 24-bit memory, and the PM
|
||||
reference could access 16-bit memory. DM reads of 24-bit memory result in
|
||||
the specified data register receiving bits 23:8 from memory. PM reads of
|
||||
16-bit memory result in the specified data register receiving bits 23:8 from
|
||||
memory. When the PX register is loaded using a 16-bit memory access (PM
|
||||
reference to 16-bit memory or DM reference to 24-bit memory), the DSP
|
||||
clears (=0)the 8-LSBs of PX.
|
||||
This multifunction instruction requires the DSP to fetch three items from
|
||||
memory: the instruction and two data words. The number of cycles
|
||||
required to execute it depends on whether the instruction generates bus
|
||||
conflicts:
|
||||
|
||||
Execution Conditions
|
||||
|
||||
1 cycle If the instruction is already cached and the data are from different memory banks
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-5
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Execution Conditions
|
||||
|
||||
2 cycles If only one bus conflict occurs—data vs. data or instruction vs. data
|
||||
|
||||
3 cycles If two bus conflicts occur—instruction vs. data vs. data
|
||||
|
||||
|
||||
EXAMPLES
|
||||
|
||||
AR = AX0 - AY0,
|
||||
MX1 = DM(I3 += M0),
|
||||
MY1 = PM(I5 += M4); /* sub and dual read */
|
||||
|
||||
AR = AX0 + AY0,
|
||||
MX0 = DM(I1 += M0),
|
||||
MY0 = PM(I4 += M4); /* add and dual read */
|
||||
|
||||
MR = MX0 * MY0 (SS),
|
||||
MX0 = DM(I2 += M2),
|
||||
MY0 = PM(I7 += M7); /* mult and dual read */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
|
||||
• “ALU Instructions” on page 3-1.
|
||||
• “MAC Instructions” on page 4-1.
|
||||
• “Arithmetic Status (ASTAT) Register” on page 2-5
|
||||
|
||||
|
||||
|
||||
|
||||
6-6 ADSP-219x Instruction Set Reference
|
||||
Dual Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
Dual Memory Read
|
||||
|
||||
AX0 = DM( I0 += M0 ) , AY0 = PM( I4 += M4 ) ;
|
||||
AX1 I1 M1 AY1 I5 M5
|
||||
MX0 I2 M2 MY0 I6 M6
|
||||
MX1 I3 M3 MY1 I7 M7
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Performs two memory read operations, one over the 16-bit DM data bus
|
||||
and the other over the 24-bit PM data bus.
|
||||
Each read operation moves the contents of the specified memory location
|
||||
to its respective destination register. The destination of both memory read
|
||||
operations is an ALU or MAC data register. The DM bus read loads an ALU
|
||||
or MAC DREGx register, and the PM bus read loads an ALU or MAC DREGy
|
||||
register. The memory data is always right-justified in the destination data
|
||||
register.
|
||||
INPUT
|
||||
|
||||
Both data move operations use two DAG registers, index (Ireg) and mod-
|
||||
ify (Mreg), to generate memory addresses—DAG1 registers for the DM bus
|
||||
access, and DAG2 registers for the PM bus access. For details on DAG reg-
|
||||
isters and data addressing, see “Data Move Instructions” on page 7-1.
|
||||
• DM/DAG1 I0, I1, I2, or I3 (index registers)
|
||||
M0, M1, M2, or M3 (modify registers)
|
||||
|
||||
• PM/DAG2 I4, I5, I6, or I7 (index registers)
|
||||
M4, M5, M6, or M7 (modify registers)
|
||||
|
||||
|
||||
! You can use any index register with any modify register from the
|
||||
same DAG. You cannot pair a DAG1 register with a DAG2 register.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-7
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
The destination register for both data move operations is an ALU or MAC
|
||||
data register—an XOP register for the DM bus access and a YOP register for
|
||||
the PM bus access.
|
||||
XOP AX0, AX1, MX0, or MX1
|
||||
|
||||
YOP AY0, AY1, MY0, or MY1
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
None affected.
|
||||
DETAILS
|
||||
|
||||
The memory read operations use register indirect addressing with post-
|
||||
modify (Ireg += Mreg). For linear indirect addressing, you must initialize
|
||||
the Lreg register of the corresponding Ireg register to 0. For circular indi-
|
||||
rect addressing, you must set the buffer’s length and base address with the
|
||||
corresponding Lreg and Breg registers. For more information on address-
|
||||
ing, see the ADSP-219x/2191 DSP Hardware Reference.
|
||||
The DM reference uses the 16-bit DM data bus, and the PM reference uses the
|
||||
24-bit PM data bus. For PM data moves, the destination data register
|
||||
receives the sixteen MSBs from 24-bit memory, and the PX register catches
|
||||
the eight LSBs. To use all twenty-four bits of the memory data, you must
|
||||
transfer the eight LSBs from PX to another data register. Otherwise, the
|
||||
eight LSBs will be lost.
|
||||
The address of the access, not the PM() or DM() reference, selects the mem-
|
||||
ory bank. So, the DM() reference could access 24-bit memory, and the PM()
|
||||
reference could access 16-bit memory. DM reads of 24-bit memory result in
|
||||
the specified data register receiving bits 23:8 from memory. PM reads of
|
||||
16-bit memory result in the specified data register receiving bits 23:8 from
|
||||
memory. When the PX register is loaded using a 16-bit memory access (PM
|
||||
reference to 16-bit memory or DM reference to 24-bit memory), the DSP
|
||||
clears (=0)the 8-LSBs of PX.
|
||||
|
||||
|
||||
|
||||
6-8 ADSP-219x Instruction Set Reference
|
||||
Dual Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
This multifunction instruction requires the DSP to fetch three items from
|
||||
memory: the instruction and two data words. The number of cycles
|
||||
required to execute it depends on whether the instruction generates bus
|
||||
conflicts:
|
||||
|
||||
Execution Conditions
|
||||
|
||||
1 cycle If the instruction is already cached and the data are from different memory banks
|
||||
|
||||
2 cycles If only one bus conflict occurs—data vs. data or instruction vs. data
|
||||
|
||||
3 cycles If two bus conflicts occur—instruction vs. data vs. data
|
||||
|
||||
|
||||
EXAMPLES
|
||||
|
||||
MX0 = DM(I0 += M0),
|
||||
MY0 = PM(I5 += M4); /* dual read */
|
||||
|
||||
AX1 = DM(I3 += M0),
|
||||
AY1 = PM(I6 += M4); /* dual read */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-9
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Compute with Memory Read
|
||||
|
||||
<ALU> , DREG = DM ( I0 += M0 ) ;
|
||||
I1 M1
|
||||
<MAC> PM
|
||||
I2 M2
|
||||
<SHIFT> I3 M3
|
||||
I4 M4
|
||||
I5 M5
|
||||
I6 M6
|
||||
I7 M7
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Combines an ALU, MAC, or shifter operation with a 16-bit read from
|
||||
memory over the DM (data memory) bus. The restricted register forms—
|
||||
using XOP and YOP registers, not the DREG register file—of all ALU, MAC, or
|
||||
Shifter instructions are supported, except for the MAC saturate instruc-
|
||||
tion, the divide primitives DIVS and DIVQ, and Shift immediate. Also, the
|
||||
multifunction ALU, MAC, and Shifter instructions may not use condi-
|
||||
tional (IF) options.
|
||||
The compute operation executes first, using the current contents of the
|
||||
data registers as input operands. Then the memory read operation exe-
|
||||
cutes, overwriting the contents of the destination data register with new
|
||||
data from memory.
|
||||
The read operation moves the contents of the memory location to the
|
||||
specified destination register. The destination of the memory read opera-
|
||||
tion is an ALU, MAC, or shifter data register. The memory data is always
|
||||
right-justified in the destination data register.
|
||||
INPUT
|
||||
|
||||
Valid input operands for the compute depend on the operation’s compu-
|
||||
tation unit. For more information, see the input descriptions in “ALU
|
||||
Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter
|
||||
Instructions” on page 5-1.
|
||||
|
||||
|
||||
|
||||
|
||||
6-10 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
The data move operation uses two DAG registers, index (Ireg) and mod-
|
||||
ify (Mreg), to generate memory addresses. Regardless of which DAG
|
||||
registers are used, all accesses occur over the DM bus. For details on DAG
|
||||
registers and data addressing, see “Data Move Instructions” on page 7-1.
|
||||
• DAG1 I0, I1, I2, or I3 (index registers)
|
||||
M0, M1, M2, or M3 (modify registers)
|
||||
|
||||
• DAG2 I4, I5, I6, or I7 (index registers)
|
||||
M4, M5, M6, or M7 (modify registers)
|
||||
|
||||
|
||||
! You can use any index register with any modify register from the
|
||||
same DAG. You cannot pair a DAG1 register with a DAG2 register.
|
||||
OUTPUT
|
||||
|
||||
The result register for the compute operation is always the computation
|
||||
unit’s result or feedback register.
|
||||
AR/AF ALU operations
|
||||
MR/SR MAC operations
|
||||
SR/SE Shifter operations
|
||||
The destination register for the data move operation is any register file
|
||||
data register. You can use any of these data registers for the DREG
|
||||
destination:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
The status flags generated as a result of the computation depends on the
|
||||
compute operation the instruction performs.For more information, see
|
||||
the status flags section of the computation’s reference page.
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-11
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The memory read operation uses indirect addressing with postmodify
|
||||
(Ireg += Mreg) and always accesses 16-bit data over the DM bus. For linear
|
||||
indirect addressing, you must initialize the Lx register of the correspond-
|
||||
ing Ireg register to 0. For circular indirect addressing, you must set the
|
||||
buffer’s length and base address with the corresponding Lreg and Breg
|
||||
registers. For more information on addressing, see the ADSP-219x/2191
|
||||
DSP Hardware Reference.
|
||||
Since the data accesses occur over the DM data bus only, the PM() and DM()
|
||||
references are semantically identical in this instruction. The address of the
|
||||
access selects the memory bank, so this instruction could access 24-bit
|
||||
memory. If so, the specified data register receives bits 23:8 from memory.
|
||||
Since the PM() reference does not activate the PM data bus, the PX register is
|
||||
not filled with any data.
|
||||
This multifunction instruction requires the DSP to fetch two items from
|
||||
memory: the instruction and one data word. The number of cycles
|
||||
required to execute this instruction depends on whether it generates a bus
|
||||
conflict:
|
||||
|
||||
Execution Conditions
|
||||
|
||||
1 cycle If no bus conflict occurs.
|
||||
|
||||
2 cycles If an instruction vs. data conflict occurs on the bus
|
||||
|
||||
|
||||
EXAMPLES
|
||||
|
||||
AR = AX0 - AY1 + C - 1,
|
||||
AX0 = DM(I1 += M0); /* ALU operation and mem read */
|
||||
|
||||
MR = MX1 * MY0 (SS),
|
||||
SR1 = PM(I4 += M4); /* MAC operation and mem read */
|
||||
|
||||
AR = 3; SE = AR; /* shift code, lshift 3 bits */
|
||||
|
||||
|
||||
|
||||
|
||||
6-12 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
SI = 0xB6A3; /* value of hi word of input */
|
||||
SR = ASHIFT SI (HI),
|
||||
SI = DM(I0 += M0); /* ashift hi word and mem read */
|
||||
|
||||
AR = 3; SE = AR; /* shift code lshift 3 bits */
|
||||
SI = 0x765D; /* value of lo word of input */
|
||||
SR = SR OR LSHIFT SI (LO),
|
||||
SI = DM(I0 += M0); /* lshift lo word and mem read */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “ALU Instructions” on page 3-1
|
||||
• “MAC Instructions” on page 4-1
|
||||
• “Shifter Instructions” on page 5-1
|
||||
• “Arithmetic Status (ASTAT) Register” on page 2-5
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-13
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Compute with Memory Write
|
||||
|
||||
DM ( I0 += M0 ) = DREG , <ALU> ;
|
||||
I1 M1
|
||||
PM <MAC>
|
||||
I2 M2
|
||||
I3 M3 <SHIFT>
|
||||
I4 M4
|
||||
I5 M5
|
||||
I6 M6
|
||||
I7 M7
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Combines an ALU, MAC, or shifter operation with a 16-bit write to
|
||||
memory over the DM (data memory) bus. The restricted register forms—
|
||||
using XOP and YOP registers, not the DREG register file—of all ALU, MAC,
|
||||
and Shifter instructions are supported, except for the MAC saturate
|
||||
instruction, the divide primitives DIVS and DIVQ, and Shift immediate.
|
||||
Also, the multifunction ALU, MAC, and Shifter instructions may not use
|
||||
conditional (IF) options.
|
||||
The write operation executes first, transferring the current contents of the
|
||||
data register to the specified memory location. Then the compute opera-
|
||||
tion executes, overwriting the contents of the destination data register
|
||||
with the result.
|
||||
The source of data for the memory write operation is an ALU, MAC, or
|
||||
shifter result or feedback register. The data is always right-justified in the
|
||||
destination memory location.
|
||||
INPUT
|
||||
|
||||
Valid input operands for the compute depend on the operation’s compu-
|
||||
tation unit. For more information, see the input descriptions in “ALU
|
||||
Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter
|
||||
Instructions” on page 5-1.
|
||||
|
||||
|
||||
|
||||
|
||||
6-14 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Write
|
||||
|
||||
|
||||
|
||||
|
||||
The data move operation uses two DAG registers, index (Ireg) and mod-
|
||||
ify (Mreg), to generate memory addresses. Regardless of which DAG
|
||||
registers are used, all accesses occur over the DM bus. For details on DAG
|
||||
registers and data addressing, see “Data Move Instructions” on page 7-1.
|
||||
• DAG1 I0, I1, I2, or I3 (index registers)
|
||||
M0, M1, M2, or M3 (modify registers)
|
||||
|
||||
• DAG2 I4, I5, I6, or I7 (index registers)
|
||||
M4, M5, M6, or M7 (modify registers)
|
||||
|
||||
|
||||
! You can use any index register with any modify register from the
|
||||
same DAG. You cannot pair a DAG1 register with a DAG2 register.
|
||||
OUTPUT
|
||||
|
||||
The destination register for the compute operation is always the computa-
|
||||
tion unit’s result or feedback register.
|
||||
AR/AF ALU operations
|
||||
MR/SR MAC operations
|
||||
SR/SE Shifter operations
|
||||
The source register for the data move operation is any register file data
|
||||
register. You can use any of these data registers for the DREG source:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
The status flags generated as a result of the computation depends on the
|
||||
compute operation the instruction performs.For more information, see
|
||||
the status flags section of the computation’s reference page.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-15
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The memory write operation uses indirect addressing with postmodify
|
||||
(Ireg += Mreg) and always transfers 16-bit data over the DM bus. For linear
|
||||
indirect addressing, you must initialize the Lreg register of the corre-
|
||||
sponding Ireg register to 0. For circular indirect addressing, you must set
|
||||
the buffer’s length and base address with the corresponding Lreg and Breg
|
||||
registers. For more information on addressing, see the ADSP-219x/2191
|
||||
DSP Hardware Reference.
|
||||
Since transfers occur over the DM data bus only, the PM() and DM() refer-
|
||||
ences are semantically identical in this instruction. The address of the
|
||||
access selects the memory bank, so this instruction could access 24-bit
|
||||
memory. If so, the operation writes bits 15:0 from the specified data regis-
|
||||
ter to bits 23:8 of the specified memory location. Since the PM() reference
|
||||
does not activate the PM data bus, the PX register does not supply any data.
|
||||
This multifunction instruction requires the DSP to fetch one item from
|
||||
memory and write one item to memory: the instruction and one data
|
||||
word. The number of cycles required to execute the instruction depends
|
||||
on whether it generates a bus conflict:
|
||||
|
||||
Execution Conditions
|
||||
|
||||
1 cycle If no bus conflict occurs.
|
||||
|
||||
2 cycles If an instruction vs. data conflict occurs on the bus
|
||||
|
||||
|
||||
Except for SR2, you can use the same data register in both the compute
|
||||
and memory write operations—as the result register for the computation
|
||||
and as the source register for the data move operation.
|
||||
EXAMPLES
|
||||
|
||||
DM(I1 += M0) = AX0,
|
||||
AR = AX0 - AY1 + C - 1; /* mem write and ALU operation */
|
||||
|
||||
|
||||
|
||||
|
||||
6-16 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Write
|
||||
|
||||
|
||||
|
||||
|
||||
PM(I4 += M4) = SR1,
|
||||
MR = MX1 * MY0 (SS); /* mem write and MAC operation */
|
||||
|
||||
AR = 3; SE = AR; /* shift code, lshift 3 bits */
|
||||
SI = 0xB6A3; /* value of hi word of input */
|
||||
DM(I0 += M0) = SI,
|
||||
SR = ASHIFT SI (HI); /* mem write and ashift hi word */
|
||||
|
||||
AR = 3; SE = AR; /* shift code lshift 3 bits */
|
||||
SI = 0x765D; /* value of lo word of input */
|
||||
DM(I0 += M0) = SI,
|
||||
SR = SR OR LSHIFT SI (LO); /* mem write and lshift lo word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “ALU Instructions” on page 3-1
|
||||
• “MAC Instructions” on page 4-1
|
||||
• “Shifter Instructions” on page 5-1
|
||||
• “Arithmetic Status (ASTAT) Register” on page 2-5
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-17
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Compute with Register to Register Move
|
||||
|
||||
<ALU> , DREG1 = DREG2 ;
|
||||
<MAC>
|
||||
<SHIFT>
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Combines an ALU, MAC, or shifter operation with a register to register
|
||||
move. The restricted register forms—using XOP and YOP registers, not the
|
||||
DREG register file—of all ALU, MAC, and Shifter instructions are sup-
|
||||
ported, except for the MAC saturate instruction, the divide primitives
|
||||
DIVS and DIVQ, and Shift immediate. Also, the multifunction ALU, MAC,
|
||||
and Shifter instructions may not use conditional (IF) options.
|
||||
The compute operation executes first, using the current contents of the
|
||||
data register. Then the data move executes, overwriting the contents of the
|
||||
destination data register with the contents of the source register.
|
||||
The source and destination of the data move operation is an ALU, MAC,
|
||||
or shifter data register. The transferred data is always right-justified in the
|
||||
destination data register.
|
||||
INPUT
|
||||
|
||||
Valid input operands for the compute depend on the operation’s compu-
|
||||
tation unit. For more information, see the input descriptions in “ALU
|
||||
Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter
|
||||
Instructions” on page 5-1.
|
||||
|
||||
|
||||
|
||||
|
||||
6-18 ADSP-219x Instruction Set Reference
|
||||
Compute with Register to Register Move
|
||||
|
||||
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
The result register for the compute operation is always the computation
|
||||
unit’s result or feedback register.
|
||||
AR/AF ALU operations
|
||||
MR/SR MAC operations
|
||||
SR/SE Shifter operations
|
||||
The source (DREG2) and destination (DREG1) registers for the data move
|
||||
operation are any register file data registers. You can use any of these data
|
||||
registers for the DREG source and destination:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
The status flags generated as a result of the computation depends on the
|
||||
compute operation the instruction performs. For more information, see
|
||||
the status flags section of the computation’s reference page.
|
||||
DETAILS
|
||||
|
||||
Except for SR2, you can use the same data register in both the compute
|
||||
and data move operations—as the result register for the computation and
|
||||
as the source register for the data move operation.
|
||||
If you use AR as the source and destination in the data move operation
|
||||
(AR = AR), the compute operation generates status only—no computation
|
||||
results. For more information, see “Generate ALU Status Only: NONE”
|
||||
on page 3-44.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-19
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
EXAMPLES
|
||||
|
||||
AR = AX1 + AY1, MX0 = AR; /* add and reg.-to-reg. move */
|
||||
|
||||
MR = MX1 * MY0 (US), MY0 = AR; /* mult and reg.-to-reg. move */
|
||||
|
||||
AR = 3; SE = AR; /* shift code, lshift 3 bits */
|
||||
SI = 0xB6A3; /* value of hi word of input */
|
||||
SR = ASHIFT SI (HI),
|
||||
SI = MR0; /* ashift hi word reg move */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
|
||||
• “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
|
||||
• “ALU Instructions” on page 3-1
|
||||
• “MAC Instructions” on page 4-1
|
||||
• “Shifter Instructions” on page 5-1
|
||||
• “Arithmetic Status (ASTAT) Register” on page 2-5
|
||||
|
||||
|
||||
|
||||
|
||||
6-20 ADSP-219x Instruction Set Reference
|
||||
|
||||
BIN
docs/9x_opcodes.pdf
Normal file
BIN
docs/9x_opcodes.pdf
Normal file
Binary file not shown.
2178
docs/9x_opcodes.txt
Normal file
2178
docs/9x_opcodes.txt
Normal file
File diff suppressed because it is too large
Load Diff
BIN
docs/9x_shftops.pdf
Normal file
BIN
docs/9x_shftops.pdf
Normal file
Binary file not shown.
985
docs/9x_shftops.txt
Normal file
985
docs/9x_shftops.txt
Normal file
@@ -0,0 +1,985 @@
|
||||
5 SHIFTER INSTRUCTIONS
|
||||
Figure 5-0.
|
||||
Table 5-0.
|
||||
Listing 5-0.
|
||||
|
||||
|
||||
|
||||
The instruction set provides shifter instructions for performing shift oper-
|
||||
ations on 16-bit input to yield 40-bit output. Combining these functions,
|
||||
programs can efficiently implement numeric format control, including
|
||||
full floating-point representation. Shifter operations include:
|
||||
• “Arithmetic Shift” on page 5-6
|
||||
• “Arithmetic Shift Immediate” on page 5-8
|
||||
• “Logical Shift” on page 5-10
|
||||
• “Logical Shift Immediate” on page 5-12
|
||||
• “Normalize” on page 5-14
|
||||
• “Normalize Immediate” on page 5-17
|
||||
• “Exponent Derive” on page 5-20
|
||||
• “Exponent (Block) Adjust” on page 5-23
|
||||
This chapter describes the individual shifter instructions and the following
|
||||
related topics:
|
||||
• “Shifter Registers” on page 5-2
|
||||
• “Shifter Instruction Options” on page 5-3
|
||||
• “Shifter Status Flags” on page 5-5
|
||||
• “Denormalization” on page 5-26
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-1
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
For details on condition codes, see “Condition Code (CCODE) Register”
|
||||
on page 2-6.
|
||||
|
||||
Shifter Registers
|
||||
As shown in Table 5-1, the shifter has five registers.
|
||||
|
||||
Table 5-1. Summary of shifter registers
|
||||
|
||||
Name Size Description
|
||||
|
||||
SR0 16 bits Shifter Result register (low word). SR denotes SR0, SR1, and SR2 combined,
|
||||
which hold the 40-bit shifter result.
|
||||
|
||||
SR1 16 bits Shifter Result register (middle word). This register also functions as the mul-
|
||||
tiplier’s y-input feedback register. SR denotes SR0, SR1, and SR2 combined,
|
||||
which hold the 40-bit shifter result.
|
||||
|
||||
SR2 16/8 bits Shifter Result register (high byte). SR denotes SR0, SR1, and SR2 combined,
|
||||
which hold the 40-bit shifter result. Although this register is 16 bits wide, for
|
||||
shifter operations, only the lower eight bits are used.
|
||||
|
||||
SB 16/5 bits Shifter Block exponent register. Although this register is 16 bits wide, for
|
||||
shifter operations, only the lower five bits are used.
|
||||
Contains the effective exponent derived from the number with greatest mag-
|
||||
nitude in a block of numbers. This value provides the shift code for all num-
|
||||
bers in the block in subsequent NORM or xSHIFT instructions.
|
||||
The value in this register is sign-extended to form a 16-bit value when trans-
|
||||
ferred to memory or to other data registers.
|
||||
Nonshifter instructions can use SB for a 16-bit scratch register.
|
||||
|
||||
|
||||
|
||||
|
||||
5-2 ADSP-219x Instruction Set Reference
|
||||
Shifter Instruction Options
|
||||
|
||||
|
||||
|
||||
|
||||
Table 5-1. Summary of shifter registers (Cont’d)
|
||||
|
||||
Name Size Description
|
||||
|
||||
SE 16/8 bits Shifter Exponent register. Although this register is 16 bits wide, for shifter
|
||||
operations, only the lower eight bits are used.
|
||||
Contains the effective exponent derived from the input data. This value pro-
|
||||
vides the shift code for a subsequent NORM or xSHIFT instruction.
|
||||
The value in this register is sign-extended to form a 16-bit value when trans-
|
||||
ferred to memory or to other data registers.
|
||||
Nonshifter instructions can use SE for a 16-bit scratch register.
|
||||
|
||||
SI 16 bits Shifter Input register. Provides single-precision twos-complement input to
|
||||
shifter instructions.
|
||||
|
||||
|
||||
When a shifter operation writes data to SR1, it sign extends the value into
|
||||
SR2, overwriting the previous contents of SR2.
|
||||
|
||||
The SB and SE registers are the result registers for the block exponent
|
||||
adjust (EXPADJ) operation and derive exponent (EXP) operation, respec-
|
||||
tively. The shifter input register SI supplies single-precision input data to
|
||||
any shifter operation, except EXPADJ. To input the result from an ALU or
|
||||
MAC operation directly, you use the appropriate result register—SR, AR,
|
||||
or MR.
|
||||
|
||||
Shifter Instruction Options
|
||||
Almost all shifter instructions have two to three options: (HI), (LO), and
|
||||
(HIX). Each option enables a different exponent detector mode that oper-
|
||||
ates only while the instruction executes. The shifter interprets and handles
|
||||
the input data according to the selected mode.
|
||||
For the derive exponent (EXP) and block exponent adjust ( EXPADJ) opera-
|
||||
tions, the shifter calculates the shift code—the direction and number of
|
||||
bits to shift—then stores that value in the SE register. For the ASHIFT,
|
||||
LSHIFT, and NORM operations, the user can supply the value of the shift
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-3
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
code directly to the SE or SB registers or use the result of a previous EXP or
|
||||
EXPADJ operation.
|
||||
|
||||
For the ASHIFT, LSHIFT, and NORM operations:
|
||||
(HI) Operation references the upper half of the output field.
|
||||
(LO) Operation references the lower half of the output field.
|
||||
For the exponent derive (EXP) operation:
|
||||
(HIX) Use this mode for shifts and normalization of results from ALU
|
||||
operations.
|
||||
Input data is the result of an add or subtract operation that may
|
||||
have overflowed. The shifter examines the ALU overflow bit AV. If
|
||||
AV=1, the effective exponent of the input is +1 (this value indicates
|
||||
that overflowed occurred before the EXP operation executed). If
|
||||
AV=0, no overflow occurred and the shifter performs the same oper-
|
||||
ations as the (HI) mode.
|
||||
(HI) Input data is a single-precision signed number or the upper half of
|
||||
a double-precision signed number. The number of leading sign bits
|
||||
in the input operand, which equals the number of sign bits minus
|
||||
one, determines the shift code.
|
||||
(By default, the EXPADJ operation always operates in this mode.)
|
||||
(LO) Input data is the lower half of a double-precision signed number.
|
||||
To derive the exponent on a double-precision number, you must
|
||||
perform the EXP operation twice, once on the upper half of the
|
||||
input, and once on the lower half. For details, “Exponent Derive”
|
||||
on page 5-20.
|
||||
|
||||
|
||||
|
||||
|
||||
5-4 ADSP-219x Instruction Set Reference
|
||||
Shifter Status Flags
|
||||
|
||||
|
||||
|
||||
|
||||
Shifter Status Flags
|
||||
Two status flags in the ASTAT register, SS and SV, record the status of
|
||||
shifter operations.
|
||||
SS Records the sign of the shifter input operand
|
||||
SS = 0 positive (+) input
|
||||
SS = 1 negative (−) input
|
||||
|
||||
SV Records overflow or underflow status
|
||||
SV = 0 no overflow or underflow occurred
|
||||
SV = 1 overflow or underflow occurred
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-5
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Arithmetic Shift
|
||||
|
||||
[IF COND] SR = [SR OR] ASHIFT DREG ( HI ) ;
|
||||
LO
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Arithmetically shifts the bits of the operand by the amount (number of
|
||||
bits) and direction specified by the shift code (value) in the SE register. A
|
||||
positive value produces a left (up) shift, and a negative value produces a
|
||||
right (down) shift. Optionally, the shift can be based on a half of the
|
||||
32-bit output field being shifted. For more information on output
|
||||
options, see “Shifter Instruction Options” on page 5-3.
|
||||
If execution is based on a condition, the shifter performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
With the SR OR option selected, the shifter ORs the shifted output with
|
||||
the current contents of the SR register and stores that value in SR. Other-
|
||||
wise, it overwrites the current contents of the SR register with the shifted
|
||||
output.
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SR Shifter result register contains 40-bit result.
|
||||
|
||||
|
||||
|
||||
5-6 ADSP-219x Instruction Set Reference
|
||||
Arithmetic Shift
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The shifter sign-extends the 40-bit result to the left, replicating the MSB
|
||||
of the input, and it zero-fills the 40-bit result from the right. Bits shifted
|
||||
out past either boundary (SR39 or SR0) are dropped.
|
||||
To shift a double-precision number, you shift both halves of the input
|
||||
data separately, using the same shift code value for both halves. You
|
||||
ASHIFT the upper half of the input data but LSHIFT the lower half. The
|
||||
first cycle, you ASHIFT the upper half of the input using the (HI) option.
|
||||
The second cycle, you LSHIFT the lower half using both the (LO) and SR OR
|
||||
options. Using these options prevents the shifter from sign-extending the
|
||||
MSB of the low word and from overwriting the output (upper word) from
|
||||
the previous ASHIFT operation.
|
||||
EXAMPLES
|
||||
|
||||
AR = 3; SE = AR; /* shift code, left shift 3 bits */
|
||||
SI = 0xB6A3; /* value of upper word of input data */
|
||||
SR = ASHIFT SI (HI); /* arithmetically shift high word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-7
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Arithmetic Shift Immediate
|
||||
|
||||
SR = [SR OR] ASHIFT DREG BY <imm8> ( HI ) ;
|
||||
LO
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Arithmetically shifts the bits of the operand by the amount (number of
|
||||
bits) and direction specified by the immediate value. Valid immediate val-
|
||||
ues range from −128 to 127. A positive value produces a left (up) shift, and
|
||||
a negative value produces a right (down) shift. Optionally, the shift can be
|
||||
based on a half of the 32-bit output field being shifted. For more informa-
|
||||
tion on output options, see “Shifter Instruction Options” on page 5-3.
|
||||
With the SR OR option selected, the shifter ORs the shifted output with
|
||||
the current contents of the SR register and stores that value in SR. Other-
|
||||
wise, it overwrites the current contents of the SR register with the shifted
|
||||
output.
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SR Shifter result register contains 40-bit result.
|
||||
|
||||
|
||||
|
||||
|
||||
5-8 ADSP-219x Instruction Set Reference
|
||||
Arithmetic Shift Immediate
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The shifter sign-extends the 40-bit result to the left, replicating the MSB
|
||||
of the input, and it zero-fills the 40-bit result from the right. Bits shifted
|
||||
out past either boundary (SR39 or SR0) are dropped.
|
||||
To shift a double-precision number, you shift both halves of the input
|
||||
data separately, using the same immediate value for both halves. You ASH-
|
||||
IFT the upper half of the input data but LSHIFT the lower half. The first
|
||||
cycle, you ASHIFT the upper half of the input using the (HI) option. The
|
||||
second cycle, you LSHIFT the lower half using both the (LO) and SR OR
|
||||
options. Using these options prevents the shifter from sign-extending the
|
||||
MSB of the low word and from overwriting the output (upper word) from
|
||||
the previous ASHIFT operation.
|
||||
EXAMPLES
|
||||
|
||||
SI = 0xB6A3; /* value of upper word of input data */
|
||||
SR = ASHIFT SI BY 3 (HI);/* arithmetically shift upper word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 15: Shift Data8” on page 9-37
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-9
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Logical Shift
|
||||
|
||||
[IF COND] SR = [SR OR] LSHIFT DREG ( HI ) ;
|
||||
LO
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Logically shifts the bits of the operand by the amount (number of bits)
|
||||
and direction specified by the shift code (value) in the SE register. A posi-
|
||||
tive value produces a left (up) shift, and a negative value produces a right
|
||||
(down) shift. Optionally, the shift can be based on a half of the 32-bit
|
||||
output field being shifted. For more information on output options, see
|
||||
“Shifter Instruction Options” on page 5-3.
|
||||
If execution is based on a condition, the shifter performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
With the SR OR option selected, the shifter ORs the shifted output with
|
||||
the current contents of the SR register and stores that value in SR. Other-
|
||||
wise, it overwrites the current contents of the SR register with the shifted
|
||||
output.
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SR Shifter result register contains 40-bit result.
|
||||
|
||||
|
||||
|
||||
5-10 ADSP-219x Instruction Set Reference
|
||||
Logical Shift
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
For left shifts (positive shift code), the shifter zero-fills the 40-bit result
|
||||
from the right. Bits shifted out past the high-order boundary (SR39) are
|
||||
dropped.
|
||||
For right shifts (negative shift code), the shifter zero-fills the 40-bit result
|
||||
from the left. Bits shifted out past the low-order boundary (SR0) are
|
||||
dropped.
|
||||
To shift a double-precision number, you shift both halves of the input
|
||||
data separately, using the same shift code value for both halves. The first
|
||||
cycle, you LSHIFT the upper half of the input using the (HI) option. The
|
||||
second cycle, you LSHIFT the lower half using both the (LO) and SR OR
|
||||
options. Using these options prevents the shifter from overwriting the
|
||||
result (upper word) from the previous LSHIFT operation.
|
||||
EXAMPLES
|
||||
|
||||
AR = 3; SE = AR; /* shift code left shift 3 bits */
|
||||
AX0 = 0x765D; /* value of lower word of input data */
|
||||
SR = SR OR LSHIFT AX0(LO);/* logically shift low word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-11
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Logical Shift Immediate
|
||||
|
||||
SR = [SR OR] LSHIFT BY <imm8> ( HI ) ;
|
||||
LO
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Logically shifts the bits of the operand by the amount (number of bits)
|
||||
and direction specified by the immediate value. Valid immediate values
|
||||
range from −128 to 127. A positive value produces a left (up) shift, and a
|
||||
negative value produces a right (down) shift. Optionally, the shift can be
|
||||
based on a half of the 32-bit output field being shifted. For more informa-
|
||||
tion on output options, see “Shifter Instruction Options” on page 5-3.
|
||||
With the SR OR option selected, the shifter ORs the shifted output with
|
||||
the current contents of the SR register and stores that value in SR. Other-
|
||||
wise, it overwrites the current contents of the SR register with the shifted
|
||||
output.
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SR Shifter result register contains 40-bit result.
|
||||
|
||||
|
||||
|
||||
|
||||
5-12 ADSP-219x Instruction Set Reference
|
||||
Logical Shift Immediate
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
For left shifts (positive shift code), the shifter zero-fills the 40-bit result
|
||||
from the right. Bits shifted out past the high-order boundary (SR39) are
|
||||
dropped.
|
||||
For right shifts (negative shift code), the shifter zero-fills the 40-bit result
|
||||
from the left. Bits shifted out past the low-order boundary (SR0) are
|
||||
dropped.
|
||||
To shift a double-precision number, you shift both halves of the input
|
||||
data separately, using the same shift code value for both halves. The first
|
||||
cycle, you LSHIFT the upper half of the input using the (HI) option. The
|
||||
second cycle, you LSHIFT the lower half using both the (LO) and SR OR
|
||||
options. Using these options prevents the shifter from overwriting the
|
||||
result (upper word) from the previous LSHIFT operation.
|
||||
EXAMPLES
|
||||
|
||||
SI = 0xFF6A; /* single-precision input */
|
||||
SR = SR OR LSHIFT SI BY 3 (LO); /* logically shift low word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 15: Shift Data8” on page 9-37
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-13
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Normalize
|
||||
|
||||
[IF COND] SR = [SR OR] NORM DREG ( HI ) ;
|
||||
LO
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Normalization, in essence, is a fixed- to floating-point conversion opera-
|
||||
tion that produces an exponent and a mantissa. Optionally, the operation
|
||||
can be based on a half of the 32-bit output field being shifted. For more
|
||||
information on output options, see “Shifter Instruction Options” on page
|
||||
5-3.
|
||||
Normalization using this instruction is a two step process that requires:
|
||||
• The EXP instruction to derive the exponent for the shift code.
|
||||
• The NORM instruction to shift the twos-complement input by the cal-
|
||||
culated shift code, removing its redundant sign bits and aligning its
|
||||
true sign bit to the high-order bit of the output field.
|
||||
The EXP operation calculates the number of redundant sign bits in the
|
||||
input and stores the negative of that value in SE. The NORM operation
|
||||
negates the value in SE again to generate a positive shift code, ensuring
|
||||
that the input is shifted left.
|
||||
If execution is based on a condition, the shifter performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
With the SR OR option selected, the shifter ORs the shifted output with
|
||||
the current contents of the SR register and stores that value in SR. Other-
|
||||
wise, it overwrites the current contents of the SR register with the shifted
|
||||
output.
|
||||
|
||||
|
||||
|
||||
|
||||
5-14 ADSP-219x Instruction Set Reference
|
||||
Normalize
|
||||
|
||||
|
||||
|
||||
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SR Shifter result register contains 40-bit result.
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The (HI) and (LO) options determine how unused bits in the 40-bit out-
|
||||
put are filled. When the (HI) option is selected, the shifter zero-fills the
|
||||
40-bit result from the right. When the (LO) option is selected, the shifter
|
||||
zero-fills the 40-bit result to the left. Bits shifted out past the high-order
|
||||
boundary (SR39) are dropped.
|
||||
To normalize a double-precision number, you normalize both halves of
|
||||
the input data separately, using the same shift code value for both halves.
|
||||
First, you use the EXP instruction to derive the exponent to use for the
|
||||
shift code. Then, in the first normalization cycle, you NORM the upper half
|
||||
of the input using the (HI) option. The next cycle, you NORM the lower half
|
||||
using both the (LO) and SR OR options. Using these options prevents the
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-15
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
shifter from overwriting the result (upper word) from the previous NORM
|
||||
operation.
|
||||
EXAMPLES
|
||||
|
||||
/* Normalize double-precision twos complement data: */
|
||||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||||
SE = EXP AX1 (HI); /* derive exponent on hi word */
|
||||
SE = EXP AX0 (LO); /* derive exponent on lo word */
|
||||
SR = NORM AX1 (HI); /* normalize hi word */
|
||||
SR = SR OR NORM AX0 (LO); /* normalize lo word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Denormalization” on page 5-26
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
5-16 ADSP-219x Instruction Set Reference
|
||||
Normalize Immediate
|
||||
|
||||
|
||||
|
||||
|
||||
Normalize Immediate
|
||||
|
||||
SR = [SR OR] NORM DREG BY <imm8> ( HI ) ;
|
||||
LO
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Normalization, in essence, is a fixed- to floating-point conversion opera-
|
||||
tion that produces an exponent and a mantissa. Using a positive constant
|
||||
for the shift code, it is a one step process that shifts the twos-complement
|
||||
input left by the specified amount, removing its redundant sign bits and
|
||||
aligning its true sign bit to the high-order bit of the output field. Option-
|
||||
ally, the operation can be based on a half of the 32-bit output field being
|
||||
shifted. For more information on output options, see “Shifter Instruction
|
||||
Options” on page 5-3.
|
||||
With the SR OR option selected, the shifter ORs the shifted output with
|
||||
the current contents of the SR register and stores that value in SR. Other-
|
||||
wise, it overwrites the current contents of the SR register with the shifted
|
||||
output.
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SR Shifter result register contains 40-bit result.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-17
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
SV AZ, AN, AV, AC, AS, AQ, SS, MV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The (HI) and (LO) options determine how unused bits in the 40-bit out-
|
||||
put are filled. When the (HI) option is selected, the shifter zero-fills the
|
||||
40-bit result from the right. When the (LO) option is selected, the shifter
|
||||
zero-fills the 40-bit result to the left. Bits shifted out past the high-order
|
||||
boundary (SR39) are dropped.
|
||||
To normalize a double-precision number, you normalize both halves of
|
||||
the input data separately, using the immediate value for both halves. In
|
||||
the first normalization cycle, you NORM the upper half of the input using
|
||||
the (HI) option. The next cycle, you NORM the lower half using both the
|
||||
(LO) and SR OR options. Using these options prevents the shifter from
|
||||
overwriting the result (upper word) from the previous NORM operation.
|
||||
EXAMPLES
|
||||
|
||||
/* Normalize a double-precision, twos-complement data: */
|
||||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||||
SR = NORM AX1 BY 2 (HI); /* normalize hi word */
|
||||
SR = SR OR NORM AX0 BY 2 (LO);/* normalize lo word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 15: Shift Data8” on page 9-37
|
||||
• “Denormalization” on page 5-26
|
||||
|
||||
|
||||
|
||||
|
||||
5-18 ADSP-219x Instruction Set Reference
|
||||
Normalize Immediate
|
||||
|
||||
|
||||
|
||||
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-19
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Exponent Derive
|
||||
|
||||
[IF COND] SE = EXP DREG ( HIX ) ;
|
||||
HI
|
||||
LO
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Derives the effective exponent of the input operand to generate the shift
|
||||
code value for use in a subsequent normalization operation. The instruc-
|
||||
tion option, (HIX), (HI), or (LO), determines the resulting shift code. For
|
||||
more information on output options, see “Shifter Instruction Options” on
|
||||
page 5-3.
|
||||
If execution is based on a condition, the shifter performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SE Shifter exponent register contains the 8-bit shift code.
|
||||
|
||||
|
||||
|
||||
|
||||
5-20 ADSP-219x Instruction Set Reference
|
||||
Exponent Derive
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
SS (Affected by operations using the (HI) and AZ, AN, AV, AC, AS, AQ, MV, SV
|
||||
(HIX) options only. Set by the MSB of the input
|
||||
data when AV = 0. In (HIX) mode only, set by the
|
||||
inverted MSB of the input data when AV = 1.)
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
You use the (LO) option only to derive the exponent for the low word in a
|
||||
double-precision twos-complement number. But before you do, you must
|
||||
derive the exponent on the high word using either the (HI) or the (HIX)
|
||||
option. The result of the EXP operation on the upper half determines the
|
||||
shift code of the lower half. Unless the upper half contains all sign bits,
|
||||
the SE register contains the correct shift code to use for both EXP (HI/HIX)
|
||||
and (LO) operations. If the upper half does contain all sign bits, EXP (LO)
|
||||
totals the number of sign bits in the double-precision word and stores that
|
||||
value in SE.
|
||||
EXAMPLES
|
||||
|
||||
/* Normalize double-precision twos complement data: */
|
||||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||||
SE = EXP AX1 (HI); /* derive exponent on hi word */
|
||||
SE = EXP AX0 (LO); /* derive exponent on lo word */
|
||||
SR = NORM AX1 (HI); /* normalize hi word */
|
||||
SR = SR OR NORM AX0 (LO); /* normalize lo word */
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-21
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
5-22 ADSP-219x Instruction Set Reference
|
||||
Exponent (Block) Adjust
|
||||
|
||||
|
||||
|
||||
|
||||
Exponent (Block) Adjust
|
||||
|
||||
[IF COND] SB = EXPADJ DREG ;
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Derives the effective exponent of the number of largest magnitude in a
|
||||
block of numbers. Using this value for the shift code in subsequent NORM
|
||||
instructions, you can normalize each number in the block.
|
||||
If execution is based on a condition, the shifter performs the operation
|
||||
only if the condition evaluates true, and it performs a NOP operation if the
|
||||
condition evaluates false. Omitting the condition forces unconditional
|
||||
execution of the instruction.
|
||||
INPUT
|
||||
|
||||
The input operand, the value to shift, is supplied in a data register. You
|
||||
can use any of these data registers for the DREG inputs:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
SB Shifter block exponent register contains the 5-bit exponent value.
|
||||
You must initialize SB to −16 before issuing the first EXPADJ instruc-
|
||||
tion in the series.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-23
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
|
||||
Affected Flags–set or cleared by the operation Unaffected Flags
|
||||
|
||||
AZ, AN, AV, AC, AS, AQ, SS, MV, SV
|
||||
|
||||
For information on these status bits in the ASTAT register, see Table 2-2 on page 2-5.
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
This instruction operates in (HI) mode to derive the exponent. It works
|
||||
on double-precision twos-complement input only. Possible values for the
|
||||
result of the EXPADJ operation range from −15 to 0.
|
||||
To derive the effective exponent for a block of numbers, you
|
||||
1. Initialize the SB register to −16.
|
||||
SB = −16;
|
||||
|
||||
This value falls below the range of possible exponent values.
|
||||
2. For each number in the block, derive the effective exponent.
|
||||
SB = EXPADJ DREGx;
|
||||
|
||||
For the first operation, the shifter derives the exponent and stores it
|
||||
in SB.
|
||||
For each subsequent operation, the shifter derives the exponent
|
||||
and compares the new value with the current value of SB. If the
|
||||
new value is greater than the current value, the shifter stores the
|
||||
new value in SB, overwriting the old value. Otherwise, the shifter
|
||||
discards the new value and the contents of SB remain unchanged.
|
||||
At the end of the last EXPADJ operation, SB contains the exponent
|
||||
of the number of largest magnitude in the block.
|
||||
|
||||
|
||||
|
||||
|
||||
5-24 ADSP-219x Instruction Set Reference
|
||||
Exponent (Block) Adjust
|
||||
|
||||
|
||||
|
||||
|
||||
3. Transfer the contents of SB to SE.
|
||||
SE = SB;
|
||||
|
||||
SE now contains the shift code to use in subsequent NORM opera-
|
||||
tions to normalize each of the numbers in the block. For details,
|
||||
see “Normalize” on page 5-14.
|
||||
Alternatively, you can save the exponent in a data register for use
|
||||
later in your program.
|
||||
EXAMPLES
|
||||
|
||||
/* Normalize double-precision twos complement data: */
|
||||
AX1 = 0xF6D4; /* load hi 2s comp data in dreg */
|
||||
AX0 = 0x04A2; /* load lo 2s comp data in dreg */
|
||||
SB = -16; /* initialize SB */
|
||||
SB = EXPADJ AX1;
|
||||
SB = EXPADJ AX0;
|
||||
SE = SB; /* load block adjusted exp */
|
||||
SR = NORM AX1 (HI); /* normalize hi word */
|
||||
SR = SR OR NORM AX0 (LO); /* normalize lo word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Condition Code (CCODE) Register” on page 2-6
|
||||
• “Mode Status (MSTAT) Register” on page 2-11
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 5-25
|
||||
Shifter Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Denormalization
|
||||
FUNCTION
|
||||
|
||||
Denormalization is a shift function in which a predefined exponent
|
||||
defines the amount and direction of the shift. In essence, denormalization
|
||||
is a floating- to fixed-point conversion operation. It requires a series of
|
||||
shifter operations:
|
||||
• The EXP instruction to derive the exponent used for the shift code,
|
||||
or SE explicitly loaded with the exponent value. SE must contain the
|
||||
shift value; for denormalization, you cannot use ASHIFT/LSHIFT
|
||||
with an immediate value.
|
||||
• The ASHIFT instruction to shift a single-precision number or the
|
||||
high word of a double-precision number.
|
||||
• When denormalizing a double-precision number, the LSHIFT
|
||||
instruction to shift the low word.
|
||||
Denormalize a double-precision, twos-complement number:
|
||||
MX1 = −3; /* generate shift code */
|
||||
SE = MX1; /* load value in SE register */
|
||||
AX1 = 0xB6A3; /* load high word of input */
|
||||
AX0 = 0x765D; /* load low word of input */
|
||||
SR = ASHIFT AX1(HI); /* arith shift high word */
|
||||
SR = SR OR LSHIFT AX0(LO); /* logically shift low word */
|
||||
|
||||
You can reverse shift order, but you must always arithmetically shift the
|
||||
high word of a double-precision number:
|
||||
MX1 = −3; /* generate shift code */
|
||||
SE = MX1; /* load value in SE register */
|
||||
AX1 = 0xB6A3; /* load high word of input */
|
||||
AX0 = 0x765D; /* load low word of input */
|
||||
SR = LSHIFT AX0(LO); /* logically shift low word */
|
||||
SR = SR OR ASHIFT AX1(HI); /* arith shift high word */
|
||||
|
||||
|
||||
|
||||
|
||||
5-26 ADSP-219x Instruction Set Reference
|
||||
|
||||
34
docs/ARCHITECTURE.md
Normal file
34
docs/ARCHITECTURE.md
Normal file
@@ -0,0 +1,34 @@
|
||||
# ADSP-219x Architecture Reference ⚙️
|
||||
|
||||
## Core Features
|
||||
The ADSP-219x family consists of a 16-bit fixed-point DSP core with a 24-bit instruction word.
|
||||
|
||||
- **Harvard Architecture**: Separate Program Memory (PM) and Data Memory (DM) buses.
|
||||
- **Instruction Width**: Exactly 24 bits. Padded often with a leading 0x00 or trailing zero byte if stored in 32-bit words, or packed as 3 bytes.
|
||||
- **Memory Model**:
|
||||
- PM Adressraum (24-bit Wörter): 16-bit to 24-bit depending on the model.
|
||||
- DM Adressraum (16-bit Wörter): Up to 64K words.
|
||||
|
||||
## Register Set 🗳️
|
||||
|
||||
| Group | Registry | Purpose |
|
||||
|-------|----------|---------|
|
||||
| **REG0** | AX0, AX1, MX0, MX1, AY0, AY1, MY0, MY1, MR2, SR2, AR, SI, MR1, SR1, MR0, SR0 | ALU, Multiplier, MAC, and Shifter registers. |
|
||||
| **REG1** | I0-I3, M0-M3, L0-L3, IMASK, IRPTL, ICNTL, STACKA | DAG1 (Data Address Generator) indices, modifies, lengths, and interrupt control. |
|
||||
| **REG2** | I4-I7, M4-M7, L4-L7, Reserved, CNTR, LPSTACKA | DAG2 indices, modifies, lengths, and hardware loop structures. |
|
||||
| **REG3** | ASTAT, MSTAT, SSTAT, LPSTACKP, CCODE, SE, SB, PX, DMPG1, DMPG2, IOPG, IJPG, Reserved, STACKP | Status registers, page registers, and control stacks. |
|
||||
|
||||
## Arithmetic Elements
|
||||
- **ALU**: 16-bit with overflow and saturation logic.
|
||||
- **Multiplier/MAC**: 16x16 → 40-bit accumulation (MR).
|
||||
- **Barrel Shifter**: 32-bit with 16-bit input and bit-manipulation capabilities.
|
||||
|
||||
## Instruction Types 🕹️
|
||||
There are ~37 distinct instruction types, distinguished by their MSB encoding.
|
||||
|
||||
- **Type 1**: Compute + Dual Memory Read (Multifunction).
|
||||
- **Type 3**: Direct Register Read/Write.
|
||||
- **Type 4**: Compute + Single Memory Read/Write.
|
||||
- **Type 6/7**: Load Immediate 16-bit to Register.
|
||||
- **Type 10/10a/19/36**: Jumps and Calls (Relative/Indirect/Long).
|
||||
- **Type 15/16**: Shifter operations.
|
||||
26
docs/GETTING_STARTED.md
Normal file
26
docs/GETTING_STARTED.md
Normal file
@@ -0,0 +1,26 @@
|
||||
# ADSP-219x Analysis Workflow (Air-Gapped 🛡️)
|
||||
|
||||
## Phase 1: Preparation (Online)
|
||||
1. **Download and Copy**: Ensure the entire `adsp219x-re/` folder is on the air-gapped machine.
|
||||
2. **Setup Dependencies**: Ensure Python 3.8+ is installed. Radare2 must be on $PATH.
|
||||
3. **Verify Python**: `python3 -m pip install r2pipe` (if not already part of your r2 install).
|
||||
|
||||
## Phase 2: Loading ROMs
|
||||
Use raw loading for ADSP-2191 ROMs:
|
||||
`r2 -a adsp2 -b 24 -m 0x0 my_rom.bin`
|
||||
(Note: `-a` and `-b` are placeholders until a native plugin exists. We use raw mode.)
|
||||
|
||||
## Phase 3: Automated Disassembly
|
||||
Run the standalone disassembler first to get a quick overview:
|
||||
`python3 disassembler/adsp219x_disasm.py my_rom.bin 3 > disassembly.txt`
|
||||
|
||||
## Phase 4: Radare2 + Iaito Integration
|
||||
To use our custom Python disassembly inside radare2:
|
||||
1. Open the ROM in radare2.
|
||||
2. Run the analysis script via r2pipe:
|
||||
`#!python analysis/analyze_rom.py` (Inside r2: `#!pipe python3 ...`)
|
||||
3. Use `iaito` to browse the memory with the comments generated by the script.
|
||||
|
||||
## Phase 5: Debugging/Validation
|
||||
Compare your proprietary ROM against our test ROMs in `testrom/test_roms/`.
|
||||
If you find a new instruction type, add it to `disassembler/adsp219x_disasm.py` and submit!
|
||||
1366
docs/opcode_definitions.txt
Normal file
1366
docs/opcode_definitions.txt
Normal file
File diff suppressed because it is too large
Load Diff
812
docs/opcode_mnemonics.txt
Normal file
812
docs/opcode_mnemonics.txt
Normal file
@@ -0,0 +1,812 @@
|
||||
9 INSTRUCTION OPCODES
|
||||
Figure 9-0.
|
||||
Table 9-0.
|
||||
Listing 9-0.
|
||||
|
||||
|
||||
|
||||
This chapter lists and describes the opcodes that defines each of the
|
||||
instructions in the ADSP-219x’s instruction set. This information is use-
|
||||
ful for debugging programs.
|
||||
This chapter covers the following topics:
|
||||
• “Opcode Mnemonics” on page 9-1
|
||||
• “Opcode Definitions” on page 9-20
|
||||
|
||||
|
||||
Opcode Mnemonics
|
||||
This section lists, describes, and gives the numeric value for each opcode
|
||||
mnemonic.
|
||||
|
||||
Table 9-1. Opcode mnemonics
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
AMF Specifies an ALU or multiplier operation. page 9-8
|
||||
|
||||
AS Specifies whether ALU saturation mode is page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
B Specifies whether branch is page 9-32
|
||||
page 9-41
|
||||
0 = immediate
|
||||
page 9-42
|
||||
1 = delayed
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-1
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-1. Opcode mnemonics (Cont’d)
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
BIT Specifies which interrupt to enable or disable (0–15). page 9-60
|
||||
|
||||
BO Specifies whether the supplied 4-bit constant in a type 9 instruction is page 9-12
|
||||
page 9-27
|
||||
01 = as is
|
||||
11 = negated
|
||||
|
||||
BR Specifies whether bit-reverse addressing on DAG1 is page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
BSR Specifies whether the secondary DAG address registers are page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
C Specifies whether a software interrupt is page 9-60
|
||||
0 = set
|
||||
1 = cleared
|
||||
|
||||
CC Specifies the two LSBs of a 4-bit constant value in a type 9 instruction. page 9-12
|
||||
page 9-27
|
||||
|
||||
CF Specifies whether to flush the instruction cache page 9-50
|
||||
0 = No flush
|
||||
1 = flush
|
||||
|
||||
COND Specifies one of the condition codes on which to base execution of the page 9-11
|
||||
instruction.
|
||||
|
||||
|
||||
|
||||
|
||||
9-2 ADSP-219x Instruction Set Reference
|
||||
Table 9-1. Opcode mnemonics (Cont’d)
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
D Specifies the direction of a data move. page 9-22
|
||||
page 9-35
|
||||
0 = read
|
||||
page 9-51
|
||||
1 = write page 9-54
|
||||
page 9-57
|
||||
page 9-58
|
||||
|
||||
DD Specifies a destination data register for a DM bus transfer. page 9-21
|
||||
00 = AX0
|
||||
01 = AX1
|
||||
10 = MX0
|
||||
11 = MX1
|
||||
|
||||
DDREG Specifies a destination register for a register-to-register move operation. page 9-13
|
||||
|
||||
DREG Specifies an unrestricted data register (REG0 only). page 9-13
|
||||
|
||||
DMI Specifies a DAG index address register (I0–I3) for a DM bus transfer. page 9-18
|
||||
page 9-21
|
||||
|
||||
DMM Specifies a DAG modify address register (M0–M3) for a DM bus trans- page 9-18
|
||||
fer. page 9-21
|
||||
|
||||
DRGP Specifies a destination register group. page 9-39
|
||||
00 = REG0
|
||||
01 = REG1
|
||||
10 = REG2
|
||||
11 = REG3
|
||||
|
||||
DRL Specifies two MSBs of DREG data register address. page 9-13
|
||||
|
||||
DRU Specifies two LSBs of DREG data register address. page 9-13
|
||||
|
||||
Exponent Specifies an 8-bit, two’s-complement shift value. page 9-37
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-3
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-1. Opcode mnemonics (Cont’d)
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
G Specifies a DAG register group. page 9-17
|
||||
0 = DAG1
|
||||
1 = DAG2
|
||||
|
||||
IREG/MREG Specifies DAG index and modify registers (I0–I7, M0–M7). page 9-18
|
||||
|
||||
I Specifies DAG index register (I0–I7). page 9-17
|
||||
|
||||
Idle Value Specifies a 4-bit value that defines an internal clock divisor. page 9-53
|
||||
|
||||
INT Specifies whether interrupts are globally page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
LPP Specifies push/pop of the loop stacks. page 9-50
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
M Specifies a DAG modify register. page 9-17
|
||||
|
||||
MM Specifies whether MAC integer mode is page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
MOD DATA Specifies an 8-bit, two’s-complement immediate data value. page 9-44
|
||||
page 9-51
|
||||
|
||||
MS Specifies memory bus for a memory data transfer page 9-54
|
||||
0 = 16-bit DM bus
|
||||
1 = 24-bit PM bus
|
||||
|
||||
|
||||
|
||||
|
||||
9-4 ADSP-219x Instruction Set Reference
|
||||
Table 9-1. Opcode mnemonics (Cont’d)
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
OL Specifies whether ALU overflow mode is page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
PD Specifies a destination data register for a PM bus transfer. page 9-21
|
||||
00 = AY0
|
||||
01 = AY1
|
||||
10 = MY0
|
||||
11 = MY1
|
||||
|
||||
PMI Specifies a DAG index address register (I4–I7) for a PM bus transfer. page 9-18
|
||||
|
||||
PMM Specifies a DAG modify address register (M4–M7) for a PM bus trans- page 9-18
|
||||
fer.
|
||||
|
||||
PPP Specifies push/pop of the PC stack. page 9-50
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
Q Specifies the RTI mode. page 9-42
|
||||
0 = normal
|
||||
1 = single-step
|
||||
|
||||
R Specifies a result register. page 9-49
|
||||
0 = MR register
|
||||
1 = SR register
|
||||
|
||||
REG Specifies a core register of RGPx. page 9-13
|
||||
|
||||
REG1 Specifies a register group 1 register page 9-13
|
||||
page 9-25
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-5
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-1. Opcode mnemonics (Cont’d)
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
REG2 Specifies a register group 2 register page 9-13
|
||||
page 9-25
|
||||
|
||||
REG3 Specifies a register group 3 register page 9-13
|
||||
page 9-56
|
||||
|
||||
RGP Specifies a register group. page 9-13
|
||||
00 = REG0
|
||||
01 = REG1
|
||||
10 = REG2
|
||||
11 = REG3.
|
||||
|
||||
S Specifies the branch type. page 9-32
|
||||
page 9-41
|
||||
0 = jump
|
||||
1 = call
|
||||
|
||||
SDREG Specifies the source data register for a data move operation. page 9-13
|
||||
|
||||
SF Specifies a shift function. page 9-15
|
||||
|
||||
SPP Specifies push/pop of the status stack. page 9-50
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
SR Specifies whether the secondary data registers are page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
|
||||
|
||||
|
||||
9-6 ADSP-219x Instruction Set Reference
|
||||
Table 9-1. Opcode mnemonics (Cont’d)
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
SRGP Specifies a source register group for a data move operation. page 9-39
|
||||
00 = REG0
|
||||
01 = REG1
|
||||
10 = REG2
|
||||
11 = REG3
|
||||
|
||||
SWCD Specifies a 4-bit nonfunctional value used by ADI tools only. page 9-52
|
||||
|
||||
T Specifies the return type. page 9-42
|
||||
0 = RTS
|
||||
1 = RTI
|
||||
|
||||
TERM Specifies the terminating condition for the type 11 instruction. page 9-34
|
||||
1110 = NOT CE
|
||||
1111 = TRUE
|
||||
|
||||
TI Specifies whether the timer is page 9-40
|
||||
0 = disabled
|
||||
1 = enabled
|
||||
|
||||
U Specifies whether the DAG index register is page 9-54
|
||||
0 = premodified with no update
|
||||
1 = postmodified with update
|
||||
|
||||
XOP Specifies a restricted data register used to supply the x operand value in page 9-19
|
||||
a multifunction or conditional instruction.
|
||||
|
||||
XREG Specifies the source register (REG0) in a shift function. page 9-13
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-7
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-1. Opcode mnemonics (Cont’d)
|
||||
|
||||
Mnemonic Description Details
|
||||
|
||||
Y0 Specifies whether the source of the x-operand is page 9-11
|
||||
0 = data register
|
||||
1 = 0 (explicit value)
|
||||
|
||||
YOP Specifies a restricted data register used to supply the y operand value in page 9-19
|
||||
a multifunction or conditional instruction.
|
||||
|
||||
YREG Specifies the destination register (REG0) in a shift function. page 9-13
|
||||
page 9-11
|
||||
|
||||
YY Specifies the two MSBs of a 4-bit constant value in a type 9 instruc- page 9-12
|
||||
tion. page 9-27
|
||||
|
||||
Z Specifies a result or feedback register page 9-23
|
||||
page 9-26
|
||||
0 = result register
|
||||
page 9-27
|
||||
1 = feedback register page 9-11
|
||||
|
||||
|
||||
ALU or Multiplier Function (AMF) Codes
|
||||
Table 9-2 on page 9-9 lists the AMF codes used by these instruction types:
|
||||
• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
|
||||
• “Type 9: Compute” on page 9-27
|
||||
|
||||
|
||||
|
||||
|
||||
9-8 ADSP-219x Instruction Set Reference
|
||||
Table 9-2. ALU/multiplier function (AMF) codes
|
||||
|
||||
Code Function Description
|
||||
|
||||
Multiplier functions
|
||||
|
||||
00000 NOP No operation
|
||||
|
||||
00001 X * Y (RND) Multiply
|
||||
|
||||
00010 MR + X * Y (RND) Multiply and accumulate
|
||||
|
||||
00011 MR – X * Y (RND) Multiply and subtract
|
||||
|
||||
00100 X * Y (SS) Multiply
|
||||
|
||||
00101 X * Y (SU) Multiply
|
||||
|
||||
00110 X * Y (US) Multiply
|
||||
|
||||
00111 X * Y (UU) Multiply
|
||||
|
||||
01000 MR + X * Y (SS) Multiply and accumulate
|
||||
|
||||
01001 MR + X * Y (SU) Multiply and accumulate
|
||||
|
||||
01010 MR + X * Y (US) Multiply and accumulate
|
||||
|
||||
01011 MR + X * Y (UU) Multiply and accumulate
|
||||
|
||||
01100 MR – X * Y (SS) Multiply and subtract
|
||||
|
||||
01101 MR – X * Y (SU) Multiply and subtract
|
||||
|
||||
01110 MR – X * Y (US) Multiply and subtract
|
||||
|
||||
01111 MR – X * Y (UU) Multiply and subtract
|
||||
|
||||
(RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned;
|
||||
(US) =x operand unsigned, y operand signed; (UU) = both operands unsigned
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-9
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-2. ALU/multiplier function (AMF) codes (Cont’d)
|
||||
|
||||
Code Function Description
|
||||
|
||||
ALU functions
|
||||
|
||||
10000 Y PASS/CLEAR
|
||||
|
||||
10001 Y+1 PASS
|
||||
|
||||
10010 X+Y+C Add with carry
|
||||
|
||||
10011 X+Y Add
|
||||
|
||||
10100 NOT Y Negate
|
||||
|
||||
10101 –Y PASS
|
||||
|
||||
10110 X–Y+C–1 Subtract (X–Y) with borrow
|
||||
|
||||
10111 X–Y Subtract
|
||||
|
||||
11000 Y–1 PASS
|
||||
|
||||
11001 Y–X Subtract
|
||||
|
||||
11010 Y–X+C–1 Subtract (Y–X) with borrow
|
||||
|
||||
11011 NOT X Negate
|
||||
|
||||
11100 X AND Y AND/test bit,clear bit
|
||||
|
||||
11101 X OR Y OR/set bit
|
||||
|
||||
11110 X XOR Y XOR/toggle bit
|
||||
|
||||
11111 ABS X Absolute value
|
||||
|
||||
(RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned;
|
||||
(US) =x operand unsigned, y operand signed; (UU) = both operands unsigned
|
||||
|
||||
|
||||
|
||||
|
||||
9-10 ADSP-219x Instruction Set Reference
|
||||
Condition Codes
|
||||
Table 9-3 on page 9-11 lists the condition codes used by these instruction
|
||||
types:
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Type 10: Direct Jump” on page 9-32
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Type 19: Indirect Jump/Call” on page 9-41
|
||||
• “Type 20: Return” on page 9-42
|
||||
• “Type 36: Long Jump/Call” on page 9-59
|
||||
• “Type 11: Do ··· Until” on page 9-34
|
||||
uses NOT CE and TRUE only for the terminating condition.
|
||||
|
||||
Table 9-3. Condition codes
|
||||
|
||||
Code Condition Description
|
||||
|
||||
0000 EQ Equal to 0 (= 0)
|
||||
|
||||
0001 NE Not equal to 0 (≠ 0)
|
||||
|
||||
0010 GT Greater than 0 (>0)
|
||||
|
||||
0011 LE Less than or equal to 0 (≤0)
|
||||
|
||||
0100 LT Less than 0 (<0)
|
||||
|
||||
0101 GE Greater than or equal to 0 (≥0)
|
||||
|
||||
0110 AV ALU overflow
|
||||
|
||||
0111 NOT AV Not ALU overflow
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-11
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-3. Condition codes (Cont’d)
|
||||
|
||||
Code Condition Description
|
||||
|
||||
1000 AC ALU carry
|
||||
|
||||
1001 NOT AC Not ALU carry
|
||||
|
||||
1010 SWCOND CCODE register condition
|
||||
|
||||
1011 NOT SWCOND Not CCODE register condition
|
||||
|
||||
1100 MV MAC overflow
|
||||
|
||||
1101 NOT MV Not MAC overflow
|
||||
|
||||
1110 NOT CE Counter not expired
|
||||
|
||||
1111 TRUE Always true
|
||||
|
||||
|
||||
Constant Codes
|
||||
Table 9-4 lists the valid constants used by “Type 9: Compute” on
|
||||
page 9-27. As shown, the YY/CC bits determine the constant value and the
|
||||
BO bits determine the sign of the value.
|
||||
|
||||
|
||||
Table 9-4. Constants
|
||||
|
||||
Code Decimal / Hex Decimal / Hex
|
||||
|
||||
YY CC BO = 01 BO = 11
|
||||
|
||||
00 00 1 / 0x0001 −2 / 0xFFFE
|
||||
|
||||
00 01 2 / 0x0002 −3 / 0xFFFD
|
||||
|
||||
00 10 4 / 0x0004 −5 / 0xFFFB
|
||||
|
||||
00 11 8 / 0x0008 −9 / 0xFFF7
|
||||
|
||||
|
||||
|
||||
|
||||
9-12 ADSP-219x Instruction Set Reference
|
||||
Table 9-4. Constants (Cont’d)
|
||||
|
||||
Code Decimal / Hex Decimal / Hex
|
||||
|
||||
YY CC BO = 01 BO = 11
|
||||
|
||||
01 00 16 / 0x0010 −17 / 0xFFEF
|
||||
|
||||
01 01 32 / 0x0020 −33 / 0xFFDF
|
||||
|
||||
01 10 64 / 0x0040 −65 / 0xFFBF
|
||||
|
||||
01 11 128 / 0x0080 −129 / 0xFF7F
|
||||
|
||||
10 00 256 / 0x0100 −257 / 0xFEFF
|
||||
|
||||
10 01 512 / 0x0200 −513 / 0xFDFF
|
||||
|
||||
10 10 1024 / 0x0400 −1025 / 0xFBFF
|
||||
|
||||
10 11 2048 / 0x0800 −2049 / 0xF7FF
|
||||
|
||||
11 00 4096 / 0x1000 −4097 / 0xEFFF
|
||||
|
||||
11 01 8192 / 0x2000 −8193 / 0xDFFF
|
||||
|
||||
11 10 16384 / 0x4000 −16385 / 0xBFFF
|
||||
|
||||
11 11 −32768 / 0x8000 +32767 / 0x7FFF
|
||||
|
||||
|
||||
Core Register Codes
|
||||
Table 9-5 on page 9-14 list the core registers and their addresses. The
|
||||
complete address of any individual register is formed by appending the
|
||||
register’s address bits to its RGP bits, so, for example, the address of the I2
|
||||
register is 010010. The opcode mnemonics DREG, DDREG, SDREG, XREG, and
|
||||
YREG and the following instruction types reference these registers by their
|
||||
address bits:
|
||||
• “Type 3: Dreg/Ireg/Mreg «···» DM/PM” on page 9-22
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-13
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 6: Dreg «··· Data16” on page 9-24
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
|
||||
• “Type 15: Shift Data8” on page 9-37
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Type 17: Any Reg «··· Any Reg” on page 9-39
|
||||
• “Type 34: Dreg «···» IOreg” on page 9-57
|
||||
• “Type 35: Dreg «···»Sreg” on page 9-58
|
||||
|
||||
Table 9-5. Core registers
|
||||
|
||||
RGP/Address Register Groups (RGP)
|
||||
|
||||
Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3)
|
||||
|
||||
0000 AX0 I0 I4 ASTAT
|
||||
|
||||
0001 AX1 I1 I5 MSTAT
|
||||
|
||||
0010 MX0 I2 I6 SSTAT
|
||||
|
||||
0011 MX1 I3 I7 LPSTACKP
|
||||
|
||||
0100 AY0 M0 M4 CCODE
|
||||
|
||||
0101 AY1 M1 M5 SE
|
||||
|
||||
0110 MY0 M2 M6 SB
|
||||
|
||||
|
||||
|
||||
|
||||
9-14 ADSP-219x Instruction Set Reference
|
||||
Table 9-5. Core registers (Cont’d)
|
||||
|
||||
RGP/Address Register Groups (RGP)
|
||||
|
||||
Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3)
|
||||
|
||||
0111 MY1 M3 M7 PX
|
||||
|
||||
1000 MR2 L0 L4 DMPG1
|
||||
|
||||
1001 SR2 L1 L5 DMPG2
|
||||
|
||||
1010 AR L2 L6 IOPG
|
||||
|
||||
1011 SI L3 L7 IJPG
|
||||
|
||||
1100 MR1 IMASK Reserved Reserved
|
||||
|
||||
1101 SR1 IRPTL Reserved Reserved
|
||||
|
||||
1110 MR0 ICNTL CNTR Reserved
|
||||
|
||||
1111 SR0 STACKA LPSTACKA STACKP
|
||||
|
||||
|
||||
SF Function Codes
|
||||
Table 9-6 list the shift function (SF) codes used by these instruction types:
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
|
||||
• “Type 15: Shift Data8” on page 9-37
|
||||
—shift functions (codes 0000–0111) only
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-15
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-6. SF codes
|
||||
|
||||
Code Function
|
||||
|
||||
0000 LSHIFT (HI)
|
||||
|
||||
0001 LSHIFT (HI, OR)
|
||||
|
||||
0010 LSHIFT (LO)
|
||||
|
||||
0011 LSHIFT (LO, OR)
|
||||
|
||||
0100 ASHIFT (HI)
|
||||
|
||||
0101 ASHIFT (HI, OR)
|
||||
|
||||
0110 ASHIFT (LO)
|
||||
|
||||
0111 ASHIFT (LO, OR)
|
||||
|
||||
1000 NORM (HI)
|
||||
|
||||
1001 NORM (HI, OR)
|
||||
|
||||
1010 NORM (LO)
|
||||
|
||||
1011 NORM (LO, OR)
|
||||
|
||||
1100 EXP (HI)
|
||||
|
||||
1101 EXP (HIX)
|
||||
|
||||
1110 EXP (LO)
|
||||
|
||||
1111 Derive Block Exponent
|
||||
|
||||
|
||||
|
||||
|
||||
9-16 ADSP-219x Instruction Set Reference
|
||||
I and M Codes
|
||||
Table 9-7 on page 9-17 lists the DAG index and modify register codes
|
||||
used by the following instruction types. The G bit (DAG1/DAG2) determines
|
||||
which group of I (index) and M (modify) registers.
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23.
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 19: Indirect Jump/Call” on page 9-41
|
||||
• “Type 21: Modify DagI” on page 9-43
|
||||
• “Type 21a: Modify DagI” on page 9-44
|
||||
• “Type 22: DM/PM «··· Data16” on page 9-45
|
||||
• “Type 29: Dreg «···» DM” on page 9-51
|
||||
• “Type 32: Any Reg «···» PM/DM” on page 9-54
|
||||
|
||||
Table 9-7. I and M codes
|
||||
|
||||
DAG1 (G=0) DAG2 (G=1)
|
||||
|
||||
Code I M I M
|
||||
|
||||
00 I0 M0 I4 M4
|
||||
|
||||
01 I1 M1 I5 M5
|
||||
|
||||
10 I2 M2 I6 M6
|
||||
|
||||
11 I3 M3 I7 M7
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-17
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
DMI, DMM, PMI, and PMM Codes
|
||||
Table 9-8 lists the DAG index and modify register codes used by “Type 1:
|
||||
Compute | DregX«···DM | DregY«···PM” on page 9-21.
|
||||
|
||||
Table 9-8. DMI, DMM, PMI, PMM codes
|
||||
|
||||
Code DMI DMM PMI PMM
|
||||
|
||||
00 I0 M0 I4 M4
|
||||
|
||||
01 I1 M1 I5 M5
|
||||
|
||||
10 I2 M2 I6 M6
|
||||
|
||||
11 I3 M3 I7 M7
|
||||
|
||||
|
||||
IREG/MREG Codes
|
||||
Table 9-9 lists the Ireg and Mreg codes used by “Type 3: Dreg/Ireg/Mreg
|
||||
«···» DM/PM” on page 9-22 to specify a DAG index or modify register.
|
||||
|
||||
Table 9-9. Ireg, Mreg codes
|
||||
|
||||
Code Register Code Register
|
||||
|
||||
0000 I0 1000 M0
|
||||
|
||||
0001 I1 1001 M1
|
||||
|
||||
0010 I2 1010 M2
|
||||
|
||||
0011 I3 1011 M3
|
||||
|
||||
0100 I4 1100 M4
|
||||
|
||||
0101 I5 1101 M5
|
||||
|
||||
|
||||
|
||||
|
||||
9-18 ADSP-219x Instruction Set Reference
|
||||
Table 9-9. Ireg, Mreg codes (Cont’d)
|
||||
|
||||
Code Register Code Register
|
||||
|
||||
0110 I6 1110 M6
|
||||
|
||||
0111 I7 1111 M7
|
||||
|
||||
|
||||
XOP and YOP Codes
|
||||
Table 9-10 on page 9-19 lists the XOP and YOP codes used by these
|
||||
instructions:
|
||||
• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 23: Divide primitive, DIVQ” on page 9-47
|
||||
• “Type 24: Divide primitive, DIVS” on page 9-48
|
||||
|
||||
Table 9-10. XOP/YOP codes
|
||||
|
||||
XOP YOP
|
||||
|
||||
Code ALU MAC Shift Code ALU MAC
|
||||
|
||||
000 AX0 MX0 SI 00 AY0 MY0
|
||||
|
||||
001 AX1 MX1 SR2 01 AY1 MY1
|
||||
|
||||
010 AR AR AR 10 AF SR1
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-19
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-10. XOP/YOP codes
|
||||
|
||||
XOP YOP
|
||||
|
||||
Code ALU MAC Shift Code ALU MAC
|
||||
|
||||
011 MR0 MR0 MR0 11 0 0
|
||||
|
||||
100 MR1 MR1 MR1
|
||||
|
||||
101 MR2 MR2 MR2
|
||||
|
||||
110 SR0 SR0 SR0
|
||||
|
||||
111 SR1 SR1 SR1
|
||||
|
||||
|
||||
|
||||
Opcode Definitions
|
||||
37
testrom/gen_testrom.py
Normal file
37
testrom/gen_testrom.py
Normal file
@@ -0,0 +1,37 @@
|
||||
import sys
|
||||
import struct
|
||||
import os
|
||||
|
||||
# Opcode constants
|
||||
TYPE1_NOP = 0xC00000
|
||||
TYPE6_AX0 = 0x400000
|
||||
TYPE10_JUMP_ALWAYS = 0x18000F
|
||||
TYPE30_NOP = 0x000000
|
||||
|
||||
def create_rom(filename, format=3):
|
||||
"""
|
||||
Creates a synthetic ADSP-219x ROM with known instruction patterns.
|
||||
"""
|
||||
os.makedirs(os.path.dirname(filename), exist_ok=True)
|
||||
instructions = [
|
||||
TYPE30_NOP, # 0x0000: NOP
|
||||
TYPE6_AX0 | (0x1234 << 4), # 0x0001: AX0 = 0x1234
|
||||
TYPE10_JUMP_ALWAYS | (0x0100 << 4), # 0x0002: JUMP 0x0100
|
||||
# ... add more test patterns ...
|
||||
]
|
||||
|
||||
with open(filename, "wb") as f:
|
||||
for ins in instructions:
|
||||
if format == 3:
|
||||
# Big-endian 3-byte pack
|
||||
f.write(struct.pack(">I", ins)[1:])
|
||||
else:
|
||||
# Big-endian 4-byte pad
|
||||
f.write(struct.pack(">I", ins))
|
||||
|
||||
if __name__ == "__main__":
|
||||
# Ensure full path to base_test.bin
|
||||
base_dir = os.path.dirname(os.path.abspath(__file__))
|
||||
create_rom(os.path.join(base_dir, "test_roms/base_test.bin"), 3)
|
||||
create_rom(os.path.join(base_dir, "test_roms/padded_test.bin"), 4)
|
||||
print("Test ROMs generated in test_roms/")
|
||||
BIN
testrom/test_roms/base_test.bin
Normal file
BIN
testrom/test_roms/base_test.bin
Normal file
Binary file not shown.
BIN
testrom/test_roms/padded_test.bin
Normal file
BIN
testrom/test_roms/padded_test.bin
Normal file
Binary file not shown.
Reference in New Issue
Block a user