Initial commit: ADSP-219x disassembler, docs, test ROMs, analysis tools
- Standalone Python disassembler for 24-bit ADSP-219x instructions - Complete instruction set reference (PDFs + extracted text) - Architecture documentation and getting-started guide - Test ROM generator with packed (3-byte) and padded (4-byte) formats - r2pipe-based analysis script for radare2 integration
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docs/9x_multiops.txt
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docs/9x_multiops.txt
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6 MULTIFUNCTION
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INSTRUCTIONS
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Figure 6-0.
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Table 6-0.
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Listing 6-0.
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The instruction set provides multifunction instructions—multiple
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instructions within a single instruction cycle. Multifunction instructions
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can perform (in a single cycle) computations in parallel with data move
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operations. Multifunction instructions are combinations of single instruc-
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tions delimited with commas and ended with a semicolon, as in:
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AR = AX0 - AY0, AX0 = MR1; /* ALU sub and reg.-to-reg. move */
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These operations are the basis for all high-performance DSP functions and
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take advantage of the DSP’s inherent parallelism. Multifunction opera-
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tions include:
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• “Compute with Dual Memory Read” on page 6-3
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• “Dual Memory Read” on page 6-7
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• “Compute with Memory Read” on page 6-10
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• “Compute with Memory Write” on page 6-14
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• “Compute with Register to Register Move” on page 6-18
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This chapter describes each of the multifunction instructions and the
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order of execution of multifunction operations.
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Multifunction instructions combine compute operations with data move
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operations. The multifunction combinations have no status flags specifi-
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cally associated with them, but the DSP does update the status flags for
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the computations that appear within multifunction instructions. For
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details, see “Arithmetic Status (ASTAT) Register” on page 2-5.
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ADSP-219x Instruction Set Reference 6-1
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Multifunction Instructions
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Order of Execution of Multifunction Operations
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The DSP reads registers and memory at the beginning of the processor
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pipeline and writes them at the end of it. Normal instruction syntax, read
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from left to right, implies this functional ordering. For example:
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a. MR = MR + MX0 * MY0(UU), MX0 = DM(I0 += M0), MY0 = PM(I4 += M4);
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b. DM(I0 += M0) = AR, AR = AX0 + AY0;
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c. AR = AX0 - AY0, AX0 = MR1;
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This means that, for memory reads, the DSP executes the computation
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first, using the current value of the input data registers, and then transfers
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new data from memory or from another data register, overwriting the con-
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tents of the data registers (a and c). For memory writes, the DSP transfers
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the current value from the data register to memory first, and then over-
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writes the data register with the result of the computation (b).
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Even if you alter the order of the operations in your code, execution
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occurs in the correct order; the assembler issues a warning (if enabled), but
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results are correct at the opcode level. For example:
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MX0 = DM(I0 += M0), MY0 = PM(I4 += M4), MR = MR + MX0 * MY0(UU);
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The altered order of operations appears to reverse the order in which the
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DSP executes the operations, but the DSP always executes instructions
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using read-first/write-last logic.
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The DSP’s read-first/write-last logic enables you to use the same data reg-
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ister in more than one multifunction operation. The same data register
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can serve as an input operand into the computation and as the destination
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or source register for a data move operation. However, except for the com-
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pute with memory write instruction, the same register cannot serve as
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destination for more than one multifunction operation. Doing so gener-
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ates unpredictable and erroneous results.
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6-2 ADSP-219x Instruction Set Reference
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Compute with Dual Memory Read
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Compute with Dual Memory Read
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<ALU> , AX0 = DM( I0 += M0 ), AY0 = PM( I4 += M4 );
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<MAC> AX1 I1 M1 AY1 I5 M5
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MX0 I2 M2 MY0 I6 M6
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MX1 I3 M3 MY1 I7 M7
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FUNCTION
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Combines an ALU or MAC operation with a read from memory over the
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16-bit DM data bus and another read from memory over the 24-bit PM
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data bus. The restricted register forms—using XOP and YOP registers, not the
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DREG register file—of all ALU or MAC instructions are supported, except
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for the MAC saturate instruction and the divide primitives DIVS and DIVQ.
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Also, the multifunction ALU and MAC instructions may not use condi-
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tional (IF) options.
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The compute operation executes first, using the current contents of the
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data registers as input operands. Then the memory read operations exe-
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cute, overwriting the contents of the destination data registers with new
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data from memory.
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The destination of both memory read operations is an ALU or MAC data
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register. The DM bus read loads an ALU or MAC XOP register, and the
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PM bus read loads an ALU or MAC YOP register. The memory data is
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always right-justified in the destination data register.
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INPUT
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The input operands for the compute operation are specific to the particu-
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lar operation. For details, see the compute instruction’s individual
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description.
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• For MAC operations, see “MAC Instructions” on page 4-1.
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• For ALU operations, see “ALU Instructions” on page 3-1.
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ADSP-219x Instruction Set Reference 6-3
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Multifunction Instructions
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Both data move operations use two DAG registers, index (Ireg) and mod-
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ify (Mreg), to generate memory addresses—DAG1 registers for the DM bus
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access, and DAG2 registers for the PM bus access. For details on DAG reg-
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isters and data addressing, see “Data Move Instructions” on page 7-1.
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• DM/DAG1 I0, I1, I2, or I3 (index registers)
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M0, M1, M2, or M3 (modify registers)
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• PM/DAG2 I4, I5, I6, or I7 (index registers)
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M4, M5, M6, or M7 (modify registers)
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! You can use any index register with any modify register from the
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same DAG. You cannot pair a DAG1 register with a DAG2 register.
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OUTPUT
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The result register for the compute operation is always the computation
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unit’s result registers.
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AR ALU operations
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MR MAC operations
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! instruction.
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is not a MAC result register for this multifunction
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SR
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The destination register for both data move operations is an ALU or MAC
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data register—an XOP register for the DM bus access and a YOP register for
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the PM bus access.
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XOP register: AX0, AX1, MX0, or MX1
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YOP register: AY0, AY1, MY0, or MY1
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STATUS FLAGS
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The status flags generated as a result of the computation depends on the
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compute operation the instruction performs.For more information, see
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the status flags section of the computation’s reference page.
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6-4 ADSP-219x Instruction Set Reference
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Compute with Dual Memory Read
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DETAILS
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The memory read operations use register indirect addressing with post-
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modify (Ireg += Mreg). For linear indirect addressing, you must initialize
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the Lx register of the corresponding Ireg register to 0. For circular indirect
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addressing, you must set the buffer’s length and base address with the cor-
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responding Lreg and Breg registers. For more information on addressing,
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see the ADSP-219x/2191 DSP Hardware Reference.
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The DM() reference uses the 16-bit DM data bus, and the PM() reference uses
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the 24-bit PM data bus. For PM data moves, the destination data register
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receives the sixteen MSBs from 24-bit memory, and the PX register catches
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the eight LSBs. To use all twenty-four bits of the memory data, you must
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transfer the eight LSBs from PX to another data register. Otherwise, the
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eight LSBs will be lost.
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The address of the access, not the PM() or DM() reference, selects the mem-
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ory bank. So, the DM reference could access 24-bit memory, and the PM
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reference could access 16-bit memory. DM reads of 24-bit memory result in
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the specified data register receiving bits 23:8 from memory. PM reads of
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16-bit memory result in the specified data register receiving bits 23:8 from
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memory. When the PX register is loaded using a 16-bit memory access (PM
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reference to 16-bit memory or DM reference to 24-bit memory), the DSP
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clears (=0)the 8-LSBs of PX.
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This multifunction instruction requires the DSP to fetch three items from
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memory: the instruction and two data words. The number of cycles
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required to execute it depends on whether the instruction generates bus
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conflicts:
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Execution Conditions
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1 cycle If the instruction is already cached and the data are from different memory banks
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ADSP-219x Instruction Set Reference 6-5
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Multifunction Instructions
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Execution Conditions
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2 cycles If only one bus conflict occurs—data vs. data or instruction vs. data
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3 cycles If two bus conflicts occur—instruction vs. data vs. data
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EXAMPLES
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AR = AX0 - AY0,
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MX1 = DM(I3 += M0),
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MY1 = PM(I5 += M4); /* sub and dual read */
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AR = AX0 + AY0,
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MX0 = DM(I1 += M0),
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MY0 = PM(I4 += M4); /* add and dual read */
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MR = MX0 * MY0 (SS),
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MX0 = DM(I2 += M2),
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MY0 = PM(I7 += M7); /* mult and dual read */
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SEE ALSO
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• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
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• “ALU Instructions” on page 3-1.
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• “MAC Instructions” on page 4-1.
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• “Arithmetic Status (ASTAT) Register” on page 2-5
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6-6 ADSP-219x Instruction Set Reference
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Dual Memory Read
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Dual Memory Read
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AX0 = DM( I0 += M0 ) , AY0 = PM( I4 += M4 ) ;
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AX1 I1 M1 AY1 I5 M5
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MX0 I2 M2 MY0 I6 M6
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MX1 I3 M3 MY1 I7 M7
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FUNCTION
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Performs two memory read operations, one over the 16-bit DM data bus
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and the other over the 24-bit PM data bus.
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Each read operation moves the contents of the specified memory location
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to its respective destination register. The destination of both memory read
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operations is an ALU or MAC data register. The DM bus read loads an ALU
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or MAC DREGx register, and the PM bus read loads an ALU or MAC DREGy
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register. The memory data is always right-justified in the destination data
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register.
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INPUT
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Both data move operations use two DAG registers, index (Ireg) and mod-
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ify (Mreg), to generate memory addresses—DAG1 registers for the DM bus
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access, and DAG2 registers for the PM bus access. For details on DAG reg-
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isters and data addressing, see “Data Move Instructions” on page 7-1.
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• DM/DAG1 I0, I1, I2, or I3 (index registers)
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M0, M1, M2, or M3 (modify registers)
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• PM/DAG2 I4, I5, I6, or I7 (index registers)
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M4, M5, M6, or M7 (modify registers)
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! You can use any index register with any modify register from the
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same DAG. You cannot pair a DAG1 register with a DAG2 register.
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ADSP-219x Instruction Set Reference 6-7
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Multifunction Instructions
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OUTPUT
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The destination register for both data move operations is an ALU or MAC
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data register—an XOP register for the DM bus access and a YOP register for
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the PM bus access.
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XOP AX0, AX1, MX0, or MX1
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YOP AY0, AY1, MY0, or MY1
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STATUS FLAGS
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None affected.
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DETAILS
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The memory read operations use register indirect addressing with post-
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modify (Ireg += Mreg). For linear indirect addressing, you must initialize
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the Lreg register of the corresponding Ireg register to 0. For circular indi-
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rect addressing, you must set the buffer’s length and base address with the
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corresponding Lreg and Breg registers. For more information on address-
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ing, see the ADSP-219x/2191 DSP Hardware Reference.
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The DM reference uses the 16-bit DM data bus, and the PM reference uses the
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24-bit PM data bus. For PM data moves, the destination data register
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receives the sixteen MSBs from 24-bit memory, and the PX register catches
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the eight LSBs. To use all twenty-four bits of the memory data, you must
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transfer the eight LSBs from PX to another data register. Otherwise, the
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eight LSBs will be lost.
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The address of the access, not the PM() or DM() reference, selects the mem-
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ory bank. So, the DM() reference could access 24-bit memory, and the PM()
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reference could access 16-bit memory. DM reads of 24-bit memory result in
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the specified data register receiving bits 23:8 from memory. PM reads of
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16-bit memory result in the specified data register receiving bits 23:8 from
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memory. When the PX register is loaded using a 16-bit memory access (PM
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reference to 16-bit memory or DM reference to 24-bit memory), the DSP
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clears (=0)the 8-LSBs of PX.
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6-8 ADSP-219x Instruction Set Reference
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Dual Memory Read
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This multifunction instruction requires the DSP to fetch three items from
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memory: the instruction and two data words. The number of cycles
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required to execute it depends on whether the instruction generates bus
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conflicts:
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Execution Conditions
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1 cycle If the instruction is already cached and the data are from different memory banks
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2 cycles If only one bus conflict occurs—data vs. data or instruction vs. data
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3 cycles If two bus conflicts occur—instruction vs. data vs. data
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EXAMPLES
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MX0 = DM(I0 += M0),
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MY0 = PM(I5 += M4); /* dual read */
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AX1 = DM(I3 += M0),
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AY1 = PM(I6 += M4); /* dual read */
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SEE ALSO
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• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
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ADSP-219x Instruction Set Reference 6-9
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Multifunction Instructions
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Compute with Memory Read
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<ALU> , DREG = DM ( I0 += M0 ) ;
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I1 M1
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<MAC> PM
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I2 M2
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<SHIFT> I3 M3
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I4 M4
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I5 M5
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I6 M6
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I7 M7
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FUNCTION
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Combines an ALU, MAC, or shifter operation with a 16-bit read from
|
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memory over the DM (data memory) bus. The restricted register forms—
|
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using XOP and YOP registers, not the DREG register file—of all ALU, MAC, or
|
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Shifter instructions are supported, except for the MAC saturate instruc-
|
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tion, the divide primitives DIVS and DIVQ, and Shift immediate. Also, the
|
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multifunction ALU, MAC, and Shifter instructions may not use condi-
|
||||
tional (IF) options.
|
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The compute operation executes first, using the current contents of the
|
||||
data registers as input operands. Then the memory read operation exe-
|
||||
cutes, overwriting the contents of the destination data register with new
|
||||
data from memory.
|
||||
The read operation moves the contents of the memory location to the
|
||||
specified destination register. The destination of the memory read opera-
|
||||
tion is an ALU, MAC, or shifter data register. The memory data is always
|
||||
right-justified in the destination data register.
|
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INPUT
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||||
|
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Valid input operands for the compute depend on the operation’s compu-
|
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tation unit. For more information, see the input descriptions in “ALU
|
||||
Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter
|
||||
Instructions” on page 5-1.
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6-10 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
The data move operation uses two DAG registers, index (Ireg) and mod-
|
||||
ify (Mreg), to generate memory addresses. Regardless of which DAG
|
||||
registers are used, all accesses occur over the DM bus. For details on DAG
|
||||
registers and data addressing, see “Data Move Instructions” on page 7-1.
|
||||
• DAG1 I0, I1, I2, or I3 (index registers)
|
||||
M0, M1, M2, or M3 (modify registers)
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||||
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• DAG2 I4, I5, I6, or I7 (index registers)
|
||||
M4, M5, M6, or M7 (modify registers)
|
||||
|
||||
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||||
! You can use any index register with any modify register from the
|
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same DAG. You cannot pair a DAG1 register with a DAG2 register.
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OUTPUT
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||||
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||||
The result register for the compute operation is always the computation
|
||||
unit’s result or feedback register.
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AR/AF ALU operations
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MR/SR MAC operations
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SR/SE Shifter operations
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The destination register for the data move operation is any register file
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data register. You can use any of these data registers for the DREG
|
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destination:
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Register File
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AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
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||||
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STATUS FLAGS
|
||||
|
||||
The status flags generated as a result of the computation depends on the
|
||||
compute operation the instruction performs.For more information, see
|
||||
the status flags section of the computation’s reference page.
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-11
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The memory read operation uses indirect addressing with postmodify
|
||||
(Ireg += Mreg) and always accesses 16-bit data over the DM bus. For linear
|
||||
indirect addressing, you must initialize the Lx register of the correspond-
|
||||
ing Ireg register to 0. For circular indirect addressing, you must set the
|
||||
buffer’s length and base address with the corresponding Lreg and Breg
|
||||
registers. For more information on addressing, see the ADSP-219x/2191
|
||||
DSP Hardware Reference.
|
||||
Since the data accesses occur over the DM data bus only, the PM() and DM()
|
||||
references are semantically identical in this instruction. The address of the
|
||||
access selects the memory bank, so this instruction could access 24-bit
|
||||
memory. If so, the specified data register receives bits 23:8 from memory.
|
||||
Since the PM() reference does not activate the PM data bus, the PX register is
|
||||
not filled with any data.
|
||||
This multifunction instruction requires the DSP to fetch two items from
|
||||
memory: the instruction and one data word. The number of cycles
|
||||
required to execute this instruction depends on whether it generates a bus
|
||||
conflict:
|
||||
|
||||
Execution Conditions
|
||||
|
||||
1 cycle If no bus conflict occurs.
|
||||
|
||||
2 cycles If an instruction vs. data conflict occurs on the bus
|
||||
|
||||
|
||||
EXAMPLES
|
||||
|
||||
AR = AX0 - AY1 + C - 1,
|
||||
AX0 = DM(I1 += M0); /* ALU operation and mem read */
|
||||
|
||||
MR = MX1 * MY0 (SS),
|
||||
SR1 = PM(I4 += M4); /* MAC operation and mem read */
|
||||
|
||||
AR = 3; SE = AR; /* shift code, lshift 3 bits */
|
||||
|
||||
|
||||
|
||||
|
||||
6-12 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Read
|
||||
|
||||
|
||||
|
||||
|
||||
SI = 0xB6A3; /* value of hi word of input */
|
||||
SR = ASHIFT SI (HI),
|
||||
SI = DM(I0 += M0); /* ashift hi word and mem read */
|
||||
|
||||
AR = 3; SE = AR; /* shift code lshift 3 bits */
|
||||
SI = 0x765D; /* value of lo word of input */
|
||||
SR = SR OR LSHIFT SI (LO),
|
||||
SI = DM(I0 += M0); /* lshift lo word and mem read */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “ALU Instructions” on page 3-1
|
||||
• “MAC Instructions” on page 4-1
|
||||
• “Shifter Instructions” on page 5-1
|
||||
• “Arithmetic Status (ASTAT) Register” on page 2-5
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-13
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Compute with Memory Write
|
||||
|
||||
DM ( I0 += M0 ) = DREG , <ALU> ;
|
||||
I1 M1
|
||||
PM <MAC>
|
||||
I2 M2
|
||||
I3 M3 <SHIFT>
|
||||
I4 M4
|
||||
I5 M5
|
||||
I6 M6
|
||||
I7 M7
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Combines an ALU, MAC, or shifter operation with a 16-bit write to
|
||||
memory over the DM (data memory) bus. The restricted register forms—
|
||||
using XOP and YOP registers, not the DREG register file—of all ALU, MAC,
|
||||
and Shifter instructions are supported, except for the MAC saturate
|
||||
instruction, the divide primitives DIVS and DIVQ, and Shift immediate.
|
||||
Also, the multifunction ALU, MAC, and Shifter instructions may not use
|
||||
conditional (IF) options.
|
||||
The write operation executes first, transferring the current contents of the
|
||||
data register to the specified memory location. Then the compute opera-
|
||||
tion executes, overwriting the contents of the destination data register
|
||||
with the result.
|
||||
The source of data for the memory write operation is an ALU, MAC, or
|
||||
shifter result or feedback register. The data is always right-justified in the
|
||||
destination memory location.
|
||||
INPUT
|
||||
|
||||
Valid input operands for the compute depend on the operation’s compu-
|
||||
tation unit. For more information, see the input descriptions in “ALU
|
||||
Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter
|
||||
Instructions” on page 5-1.
|
||||
|
||||
|
||||
|
||||
|
||||
6-14 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Write
|
||||
|
||||
|
||||
|
||||
|
||||
The data move operation uses two DAG registers, index (Ireg) and mod-
|
||||
ify (Mreg), to generate memory addresses. Regardless of which DAG
|
||||
registers are used, all accesses occur over the DM bus. For details on DAG
|
||||
registers and data addressing, see “Data Move Instructions” on page 7-1.
|
||||
• DAG1 I0, I1, I2, or I3 (index registers)
|
||||
M0, M1, M2, or M3 (modify registers)
|
||||
|
||||
• DAG2 I4, I5, I6, or I7 (index registers)
|
||||
M4, M5, M6, or M7 (modify registers)
|
||||
|
||||
|
||||
! You can use any index register with any modify register from the
|
||||
same DAG. You cannot pair a DAG1 register with a DAG2 register.
|
||||
OUTPUT
|
||||
|
||||
The destination register for the compute operation is always the computa-
|
||||
tion unit’s result or feedback register.
|
||||
AR/AF ALU operations
|
||||
MR/SR MAC operations
|
||||
SR/SE Shifter operations
|
||||
The source register for the data move operation is any register file data
|
||||
register. You can use any of these data registers for the DREG source:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
The status flags generated as a result of the computation depends on the
|
||||
compute operation the instruction performs.For more information, see
|
||||
the status flags section of the computation’s reference page.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-15
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
DETAILS
|
||||
|
||||
The memory write operation uses indirect addressing with postmodify
|
||||
(Ireg += Mreg) and always transfers 16-bit data over the DM bus. For linear
|
||||
indirect addressing, you must initialize the Lreg register of the corre-
|
||||
sponding Ireg register to 0. For circular indirect addressing, you must set
|
||||
the buffer’s length and base address with the corresponding Lreg and Breg
|
||||
registers. For more information on addressing, see the ADSP-219x/2191
|
||||
DSP Hardware Reference.
|
||||
Since transfers occur over the DM data bus only, the PM() and DM() refer-
|
||||
ences are semantically identical in this instruction. The address of the
|
||||
access selects the memory bank, so this instruction could access 24-bit
|
||||
memory. If so, the operation writes bits 15:0 from the specified data regis-
|
||||
ter to bits 23:8 of the specified memory location. Since the PM() reference
|
||||
does not activate the PM data bus, the PX register does not supply any data.
|
||||
This multifunction instruction requires the DSP to fetch one item from
|
||||
memory and write one item to memory: the instruction and one data
|
||||
word. The number of cycles required to execute the instruction depends
|
||||
on whether it generates a bus conflict:
|
||||
|
||||
Execution Conditions
|
||||
|
||||
1 cycle If no bus conflict occurs.
|
||||
|
||||
2 cycles If an instruction vs. data conflict occurs on the bus
|
||||
|
||||
|
||||
Except for SR2, you can use the same data register in both the compute
|
||||
and memory write operations—as the result register for the computation
|
||||
and as the source register for the data move operation.
|
||||
EXAMPLES
|
||||
|
||||
DM(I1 += M0) = AX0,
|
||||
AR = AX0 - AY1 + C - 1; /* mem write and ALU operation */
|
||||
|
||||
|
||||
|
||||
|
||||
6-16 ADSP-219x Instruction Set Reference
|
||||
Compute with Memory Write
|
||||
|
||||
|
||||
|
||||
|
||||
PM(I4 += M4) = SR1,
|
||||
MR = MX1 * MY0 (SS); /* mem write and MAC operation */
|
||||
|
||||
AR = 3; SE = AR; /* shift code, lshift 3 bits */
|
||||
SI = 0xB6A3; /* value of hi word of input */
|
||||
DM(I0 += M0) = SI,
|
||||
SR = ASHIFT SI (HI); /* mem write and ashift hi word */
|
||||
|
||||
AR = 3; SE = AR; /* shift code lshift 3 bits */
|
||||
SI = 0x765D; /* value of lo word of input */
|
||||
DM(I0 += M0) = SI,
|
||||
SR = SR OR LSHIFT SI (LO); /* mem write and lshift lo word */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “ALU Instructions” on page 3-1
|
||||
• “MAC Instructions” on page 4-1
|
||||
• “Shifter Instructions” on page 5-1
|
||||
• “Arithmetic Status (ASTAT) Register” on page 2-5
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-17
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
Compute with Register to Register Move
|
||||
|
||||
<ALU> , DREG1 = DREG2 ;
|
||||
<MAC>
|
||||
<SHIFT>
|
||||
|
||||
|
||||
FUNCTION
|
||||
|
||||
Combines an ALU, MAC, or shifter operation with a register to register
|
||||
move. The restricted register forms—using XOP and YOP registers, not the
|
||||
DREG register file—of all ALU, MAC, and Shifter instructions are sup-
|
||||
ported, except for the MAC saturate instruction, the divide primitives
|
||||
DIVS and DIVQ, and Shift immediate. Also, the multifunction ALU, MAC,
|
||||
and Shifter instructions may not use conditional (IF) options.
|
||||
The compute operation executes first, using the current contents of the
|
||||
data register. Then the data move executes, overwriting the contents of the
|
||||
destination data register with the contents of the source register.
|
||||
The source and destination of the data move operation is an ALU, MAC,
|
||||
or shifter data register. The transferred data is always right-justified in the
|
||||
destination data register.
|
||||
INPUT
|
||||
|
||||
Valid input operands for the compute depend on the operation’s compu-
|
||||
tation unit. For more information, see the input descriptions in “ALU
|
||||
Instructions” on page 3-1, “MAC Instructions” on page 4-1, and “Shifter
|
||||
Instructions” on page 5-1.
|
||||
|
||||
|
||||
|
||||
|
||||
6-18 ADSP-219x Instruction Set Reference
|
||||
Compute with Register to Register Move
|
||||
|
||||
|
||||
|
||||
|
||||
OUTPUT
|
||||
|
||||
The result register for the compute operation is always the computation
|
||||
unit’s result or feedback register.
|
||||
AR/AF ALU operations
|
||||
MR/SR MAC operations
|
||||
SR/SE Shifter operations
|
||||
The source (DREG2) and destination (DREG1) registers for the data move
|
||||
operation are any register file data registers. You can use any of these data
|
||||
registers for the DREG source and destination:
|
||||
|
||||
Register File
|
||||
|
||||
AX0, AX1, AY0, AY1, AR, MX0, MX1, MY0, MY1, MR0, MR1, MR2, SR0, SR1, SR2, SI
|
||||
|
||||
|
||||
STATUS FLAGS
|
||||
|
||||
The status flags generated as a result of the computation depends on the
|
||||
compute operation the instruction performs. For more information, see
|
||||
the status flags section of the computation’s reference page.
|
||||
DETAILS
|
||||
|
||||
Except for SR2, you can use the same data register in both the compute
|
||||
and data move operations—as the result register for the computation and
|
||||
as the source register for the data move operation.
|
||||
If you use AR as the source and destination in the data move operation
|
||||
(AR = AR), the compute operation generates status only—no computation
|
||||
results. For more information, see “Generate ALU Status Only: NONE”
|
||||
on page 3-44.
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 6-19
|
||||
Multifunction Instructions
|
||||
|
||||
|
||||
|
||||
|
||||
EXAMPLES
|
||||
|
||||
AR = AX1 + AY1, MX0 = AR; /* add and reg.-to-reg. move */
|
||||
|
||||
MR = MX1 * MY0 (US), MY0 = AR; /* mult and reg.-to-reg. move */
|
||||
|
||||
AR = 3; SE = AR; /* shift code, lshift 3 bits */
|
||||
SI = 0xB6A3; /* value of hi word of input */
|
||||
SR = ASHIFT SI (HI),
|
||||
SI = MR0; /* ashift hi word reg move */
|
||||
|
||||
SEE ALSO
|
||||
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
|
||||
• “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
|
||||
• “ALU Instructions” on page 3-1
|
||||
• “MAC Instructions” on page 4-1
|
||||
• “Shifter Instructions” on page 5-1
|
||||
• “Arithmetic Status (ASTAT) Register” on page 2-5
|
||||
|
||||
|
||||
|
||||
|
||||
6-20 ADSP-219x Instruction Set Reference
|
||||
|
||||
Reference in New Issue
Block a user