Initial commit: ADSP-219x disassembler, docs, test ROMs, analysis tools

- Standalone Python disassembler for 24-bit ADSP-219x instructions
- Complete instruction set reference (PDFs + extracted text)
- Architecture documentation and getting-started guide
- Test ROM generator with packed (3-byte) and padded (4-byte) formats
- r2pipe-based analysis script for radare2 integration

docs/ARCHITECTURE.md

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+# ADSP-219x Architecture Reference ⚙️
+
+## Core Features
+The ADSP-219x family consists of a 16-bit fixed-point DSP core with a 24-bit instruction word.
+
+- **Harvard Architecture**: Separate Program Memory (PM) and Data Memory (DM) buses.
+- **Instruction Width**: Exactly 24 bits. Padded often with a leading 0x00 or trailing zero byte if stored in 32-bit words, or packed as 3 bytes.
+- **Memory Model**: 
+  - PM Adressraum (24-bit Wörter): 16-bit to 24-bit depending on the model.
+  - DM Adressraum (16-bit Wörter): Up to 64K words.
+
+## Register Set 🗳️
+
+| Group | Registry | Purpose |
+|-------|----------|---------|
+| **REG0** | AX0, AX1, MX0, MX1, AY0, AY1, MY0, MY1, MR2, SR2, AR, SI, MR1, SR1, MR0, SR0 | ALU, Multiplier, MAC, and Shifter registers. |
+| **REG1** | I0-I3, M0-M3, L0-L3, IMASK, IRPTL, ICNTL, STACKA | DAG1 (Data Address Generator) indices, modifies, lengths, and interrupt control. |
+| **REG2** | I4-I7, M4-M7, L4-L7, Reserved, CNTR, LPSTACKA | DAG2 indices, modifies, lengths, and hardware loop structures. |
+| **REG3** | ASTAT, MSTAT, SSTAT, LPSTACKP, CCODE, SE, SB, PX, DMPG1, DMPG2, IOPG, IJPG, Reserved, STACKP | Status registers, page registers, and control stacks. |
+
+## Arithmetic Elements
+- **ALU**: 16-bit with overflow and saturation logic.
+- **Multiplier/MAC**: 16x16 → 40-bit accumulation (MR).
+- **Barrel Shifter**: 32-bit with 16-bit input and bit-manipulation capabilities.
+
+## Instruction Types 🕹️
+There are ~37 distinct instruction types, distinguished by their MSB encoding. 
+
+- **Type 1**: Compute + Dual Memory Read (Multifunction).
+- **Type 3**: Direct Register Read/Write.
+- **Type 4**: Compute + Single Memory Read/Write.
+- **Type 6/7**: Load Immediate 16-bit to Register.
+- **Type 10/10a/19/36**: Jumps and Calls (Relative/Indirect/Long).
+- **Type 15/16**: Shifter operations.