Initial commit: ADSP-219x disassembler, docs, test ROMs, analysis tools
- Standalone Python disassembler for 24-bit ADSP-219x instructions - Complete instruction set reference (PDFs + extracted text) - Architecture documentation and getting-started guide - Test ROM generator with packed (3-byte) and padded (4-byte) formats - r2pipe-based analysis script for radare2 integration
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docs/opcode_mnemonics.txt
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9 INSTRUCTION OPCODES
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Figure 9-0.
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Table 9-0.
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Listing 9-0.
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This chapter lists and describes the opcodes that defines each of the
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instructions in the ADSP-219x’s instruction set. This information is use-
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ful for debugging programs.
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This chapter covers the following topics:
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• “Opcode Mnemonics” on page 9-1
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• “Opcode Definitions” on page 9-20
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Opcode Mnemonics
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This section lists, describes, and gives the numeric value for each opcode
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mnemonic.
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Table 9-1. Opcode mnemonics
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Mnemonic Description Details
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AMF Specifies an ALU or multiplier operation. page 9-8
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AS Specifies whether ALU saturation mode is page 9-40
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0 = disabled
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1 = enabled
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B Specifies whether branch is page 9-32
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page 9-41
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0 = immediate
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page 9-42
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1 = delayed
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ADSP-219x Instruction Set Reference 9-1
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Instruction Opcodes
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Table 9-1. Opcode mnemonics (Cont’d)
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Mnemonic Description Details
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BIT Specifies which interrupt to enable or disable (0–15). page 9-60
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BO Specifies whether the supplied 4-bit constant in a type 9 instruction is page 9-12
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page 9-27
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01 = as is
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11 = negated
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BR Specifies whether bit-reverse addressing on DAG1 is page 9-40
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0 = disabled
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1 = enabled
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BSR Specifies whether the secondary DAG address registers are page 9-40
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0 = disabled
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1 = enabled
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C Specifies whether a software interrupt is page 9-60
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0 = set
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1 = cleared
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CC Specifies the two LSBs of a 4-bit constant value in a type 9 instruction. page 9-12
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page 9-27
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CF Specifies whether to flush the instruction cache page 9-50
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0 = No flush
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1 = flush
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COND Specifies one of the condition codes on which to base execution of the page 9-11
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instruction.
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9-2 ADSP-219x Instruction Set Reference
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Table 9-1. Opcode mnemonics (Cont’d)
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Mnemonic Description Details
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D Specifies the direction of a data move. page 9-22
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page 9-35
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0 = read
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page 9-51
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1 = write page 9-54
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page 9-57
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page 9-58
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DD Specifies a destination data register for a DM bus transfer. page 9-21
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00 = AX0
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01 = AX1
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10 = MX0
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11 = MX1
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DDREG Specifies a destination register for a register-to-register move operation. page 9-13
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DREG Specifies an unrestricted data register (REG0 only). page 9-13
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DMI Specifies a DAG index address register (I0–I3) for a DM bus transfer. page 9-18
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page 9-21
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DMM Specifies a DAG modify address register (M0–M3) for a DM bus trans- page 9-18
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fer. page 9-21
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DRGP Specifies a destination register group. page 9-39
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00 = REG0
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01 = REG1
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10 = REG2
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11 = REG3
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DRL Specifies two MSBs of DREG data register address. page 9-13
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DRU Specifies two LSBs of DREG data register address. page 9-13
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Exponent Specifies an 8-bit, two’s-complement shift value. page 9-37
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ADSP-219x Instruction Set Reference 9-3
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Instruction Opcodes
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Table 9-1. Opcode mnemonics (Cont’d)
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Mnemonic Description Details
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G Specifies a DAG register group. page 9-17
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0 = DAG1
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1 = DAG2
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IREG/MREG Specifies DAG index and modify registers (I0–I7, M0–M7). page 9-18
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I Specifies DAG index register (I0–I7). page 9-17
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Idle Value Specifies a 4-bit value that defines an internal clock divisor. page 9-53
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INT Specifies whether interrupts are globally page 9-40
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0 = disabled
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1 = enabled
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LPP Specifies push/pop of the loop stacks. page 9-50
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0 = disabled
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1 = enabled
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M Specifies a DAG modify register. page 9-17
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MM Specifies whether MAC integer mode is page 9-40
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0 = disabled
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1 = enabled
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MOD DATA Specifies an 8-bit, two’s-complement immediate data value. page 9-44
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page 9-51
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MS Specifies memory bus for a memory data transfer page 9-54
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0 = 16-bit DM bus
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1 = 24-bit PM bus
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9-4 ADSP-219x Instruction Set Reference
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Table 9-1. Opcode mnemonics (Cont’d)
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Mnemonic Description Details
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OL Specifies whether ALU overflow mode is page 9-40
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0 = disabled
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1 = enabled
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PD Specifies a destination data register for a PM bus transfer. page 9-21
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00 = AY0
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01 = AY1
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10 = MY0
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11 = MY1
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PMI Specifies a DAG index address register (I4–I7) for a PM bus transfer. page 9-18
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PMM Specifies a DAG modify address register (M4–M7) for a PM bus trans- page 9-18
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fer.
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PPP Specifies push/pop of the PC stack. page 9-50
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0 = disabled
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1 = enabled
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Q Specifies the RTI mode. page 9-42
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0 = normal
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1 = single-step
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R Specifies a result register. page 9-49
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0 = MR register
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1 = SR register
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REG Specifies a core register of RGPx. page 9-13
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REG1 Specifies a register group 1 register page 9-13
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page 9-25
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ADSP-219x Instruction Set Reference 9-5
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Instruction Opcodes
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Table 9-1. Opcode mnemonics (Cont’d)
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Mnemonic Description Details
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REG2 Specifies a register group 2 register page 9-13
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page 9-25
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REG3 Specifies a register group 3 register page 9-13
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page 9-56
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RGP Specifies a register group. page 9-13
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00 = REG0
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01 = REG1
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10 = REG2
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11 = REG3.
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S Specifies the branch type. page 9-32
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page 9-41
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0 = jump
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1 = call
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SDREG Specifies the source data register for a data move operation. page 9-13
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SF Specifies a shift function. page 9-15
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SPP Specifies push/pop of the status stack. page 9-50
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0 = disabled
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1 = enabled
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SR Specifies whether the secondary data registers are page 9-40
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0 = disabled
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1 = enabled
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9-6 ADSP-219x Instruction Set Reference
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Table 9-1. Opcode mnemonics (Cont’d)
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Mnemonic Description Details
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SRGP Specifies a source register group for a data move operation. page 9-39
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00 = REG0
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01 = REG1
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10 = REG2
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11 = REG3
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SWCD Specifies a 4-bit nonfunctional value used by ADI tools only. page 9-52
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T Specifies the return type. page 9-42
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0 = RTS
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1 = RTI
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TERM Specifies the terminating condition for the type 11 instruction. page 9-34
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1110 = NOT CE
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1111 = TRUE
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TI Specifies whether the timer is page 9-40
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0 = disabled
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1 = enabled
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U Specifies whether the DAG index register is page 9-54
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0 = premodified with no update
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1 = postmodified with update
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XOP Specifies a restricted data register used to supply the x operand value in page 9-19
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a multifunction or conditional instruction.
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XREG Specifies the source register (REG0) in a shift function. page 9-13
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ADSP-219x Instruction Set Reference 9-7
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Instruction Opcodes
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Table 9-1. Opcode mnemonics (Cont’d)
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Mnemonic Description Details
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Y0 Specifies whether the source of the x-operand is page 9-11
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0 = data register
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1 = 0 (explicit value)
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YOP Specifies a restricted data register used to supply the y operand value in page 9-19
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a multifunction or conditional instruction.
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YREG Specifies the destination register (REG0) in a shift function. page 9-13
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page 9-11
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YY Specifies the two MSBs of a 4-bit constant value in a type 9 instruc- page 9-12
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tion. page 9-27
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Z Specifies a result or feedback register page 9-23
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page 9-26
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0 = result register
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page 9-27
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1 = feedback register page 9-11
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ALU or Multiplier Function (AMF) Codes
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Table 9-2 on page 9-9 lists the AMF codes used by these instruction types:
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• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
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• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
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• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
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• “Type 9: Compute” on page 9-27
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9-8 ADSP-219x Instruction Set Reference
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Table 9-2. ALU/multiplier function (AMF) codes
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Code Function Description
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Multiplier functions
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00000 NOP No operation
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00001 X * Y (RND) Multiply
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00010 MR + X * Y (RND) Multiply and accumulate
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00011 MR – X * Y (RND) Multiply and subtract
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00100 X * Y (SS) Multiply
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00101 X * Y (SU) Multiply
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00110 X * Y (US) Multiply
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00111 X * Y (UU) Multiply
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01000 MR + X * Y (SS) Multiply and accumulate
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01001 MR + X * Y (SU) Multiply and accumulate
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01010 MR + X * Y (US) Multiply and accumulate
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01011 MR + X * Y (UU) Multiply and accumulate
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01100 MR – X * Y (SS) Multiply and subtract
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01101 MR – X * Y (SU) Multiply and subtract
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01110 MR – X * Y (US) Multiply and subtract
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01111 MR – X * Y (UU) Multiply and subtract
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(RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned;
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(US) =x operand unsigned, y operand signed; (UU) = both operands unsigned
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ADSP-219x Instruction Set Reference 9-9
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Instruction Opcodes
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Table 9-2. ALU/multiplier function (AMF) codes (Cont’d)
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Code Function Description
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ALU functions
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10000 Y PASS/CLEAR
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10001 Y+1 PASS
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10010 X+Y+C Add with carry
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10011 X+Y Add
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10100 NOT Y Negate
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10101 –Y PASS
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10110 X–Y+C–1 Subtract (X–Y) with borrow
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10111 X–Y Subtract
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11000 Y–1 PASS
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11001 Y–X Subtract
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11010 Y–X+C–1 Subtract (Y–X) with borrow
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11011 NOT X Negate
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11100 X AND Y AND/test bit,clear bit
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11101 X OR Y OR/set bit
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11110 X XOR Y XOR/toggle bit
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11111 ABS X Absolute value
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(RND) = round results; (SS) = both operands signed; (SU) = x operand signed, y operand unsigned;
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(US) =x operand unsigned, y operand signed; (UU) = both operands unsigned
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9-10 ADSP-219x Instruction Set Reference
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Condition Codes
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Table 9-3 on page 9-11 lists the condition codes used by these instruction
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types:
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• “Type 9: Compute” on page 9-27
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• “Type 10: Direct Jump” on page 9-32
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• “Type 16: Shift Reg0” on page 9-38
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• “Type 19: Indirect Jump/Call” on page 9-41
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• “Type 20: Return” on page 9-42
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• “Type 36: Long Jump/Call” on page 9-59
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• “Type 11: Do ··· Until” on page 9-34
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uses NOT CE and TRUE only for the terminating condition.
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Table 9-3. Condition codes
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Code Condition Description
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0000 EQ Equal to 0 (= 0)
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0001 NE Not equal to 0 (≠ 0)
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0010 GT Greater than 0 (>0)
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0011 LE Less than or equal to 0 (≤0)
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0100 LT Less than 0 (<0)
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0101 GE Greater than or equal to 0 (≥0)
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0110 AV ALU overflow
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0111 NOT AV Not ALU overflow
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ADSP-219x Instruction Set Reference 9-11
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Instruction Opcodes
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Table 9-3. Condition codes (Cont’d)
|
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Code Condition Description
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1000 AC ALU carry
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1001 NOT AC Not ALU carry
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1010 SWCOND CCODE register condition
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1011 NOT SWCOND Not CCODE register condition
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1100 MV MAC overflow
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1101 NOT MV Not MAC overflow
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1110 NOT CE Counter not expired
|
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|
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1111 TRUE Always true
|
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Constant Codes
|
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Table 9-4 lists the valid constants used by “Type 9: Compute” on
|
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page 9-27. As shown, the YY/CC bits determine the constant value and the
|
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BO bits determine the sign of the value.
|
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Table 9-4. Constants
|
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Code Decimal / Hex Decimal / Hex
|
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|
||||
YY CC BO = 01 BO = 11
|
||||
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||||
00 00 1 / 0x0001 −2 / 0xFFFE
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||||
00 01 2 / 0x0002 −3 / 0xFFFD
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||||
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||||
00 10 4 / 0x0004 −5 / 0xFFFB
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||||
|
||||
00 11 8 / 0x0008 −9 / 0xFFF7
|
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|
||||
|
||||
|
||||
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9-12 ADSP-219x Instruction Set Reference
|
||||
Table 9-4. Constants (Cont’d)
|
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|
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Code Decimal / Hex Decimal / Hex
|
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|
||||
YY CC BO = 01 BO = 11
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||||
|
||||
01 00 16 / 0x0010 −17 / 0xFFEF
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||||
01 01 32 / 0x0020 −33 / 0xFFDF
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||||
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||||
01 10 64 / 0x0040 −65 / 0xFFBF
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||||
|
||||
01 11 128 / 0x0080 −129 / 0xFF7F
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||||
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||||
10 00 256 / 0x0100 −257 / 0xFEFF
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||||
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||||
10 01 512 / 0x0200 −513 / 0xFDFF
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||||
|
||||
10 10 1024 / 0x0400 −1025 / 0xFBFF
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||||
10 11 2048 / 0x0800 −2049 / 0xF7FF
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||||
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||||
11 00 4096 / 0x1000 −4097 / 0xEFFF
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||||
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||||
11 01 8192 / 0x2000 −8193 / 0xDFFF
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||||
11 10 16384 / 0x4000 −16385 / 0xBFFF
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||||
|
||||
11 11 −32768 / 0x8000 +32767 / 0x7FFF
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||||
|
||||
|
||||
Core Register Codes
|
||||
Table 9-5 on page 9-14 list the core registers and their addresses. The
|
||||
complete address of any individual register is formed by appending the
|
||||
register’s address bits to its RGP bits, so, for example, the address of the I2
|
||||
register is 010010. The opcode mnemonics DREG, DDREG, SDREG, XREG, and
|
||||
YREG and the following instruction types reference these registers by their
|
||||
address bits:
|
||||
• “Type 3: Dreg/Ireg/Mreg «···» DM/PM” on page 9-22
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-13
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 6: Dreg «··· Data16” on page 9-24
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
|
||||
• “Type 15: Shift Data8” on page 9-37
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
• “Type 17: Any Reg «··· Any Reg” on page 9-39
|
||||
• “Type 34: Dreg «···» IOreg” on page 9-57
|
||||
• “Type 35: Dreg «···»Sreg” on page 9-58
|
||||
|
||||
Table 9-5. Core registers
|
||||
|
||||
RGP/Address Register Groups (RGP)
|
||||
|
||||
Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3)
|
||||
|
||||
0000 AX0 I0 I4 ASTAT
|
||||
|
||||
0001 AX1 I1 I5 MSTAT
|
||||
|
||||
0010 MX0 I2 I6 SSTAT
|
||||
|
||||
0011 MX1 I3 I7 LPSTACKP
|
||||
|
||||
0100 AY0 M0 M4 CCODE
|
||||
|
||||
0101 AY1 M1 M5 SE
|
||||
|
||||
0110 MY0 M2 M6 SB
|
||||
|
||||
|
||||
|
||||
|
||||
9-14 ADSP-219x Instruction Set Reference
|
||||
Table 9-5. Core registers (Cont’d)
|
||||
|
||||
RGP/Address Register Groups (RGP)
|
||||
|
||||
Address 00 (REG0) 01 (REG1) 10 (REG2) 11 (REG3)
|
||||
|
||||
0111 MY1 M3 M7 PX
|
||||
|
||||
1000 MR2 L0 L4 DMPG1
|
||||
|
||||
1001 SR2 L1 L5 DMPG2
|
||||
|
||||
1010 AR L2 L6 IOPG
|
||||
|
||||
1011 SI L3 L7 IJPG
|
||||
|
||||
1100 MR1 IMASK Reserved Reserved
|
||||
|
||||
1101 SR1 IRPTL Reserved Reserved
|
||||
|
||||
1110 MR0 ICNTL CNTR Reserved
|
||||
|
||||
1111 SR0 STACKA LPSTACKA STACKP
|
||||
|
||||
|
||||
SF Function Codes
|
||||
Table 9-6 list the shift function (SF) codes used by these instruction types:
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 14: Shift | Dreg1 «··· Dreg2” on page 9-36
|
||||
• “Type 15: Shift Data8” on page 9-37
|
||||
—shift functions (codes 0000–0111) only
|
||||
• “Type 16: Shift Reg0” on page 9-38
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-15
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-6. SF codes
|
||||
|
||||
Code Function
|
||||
|
||||
0000 LSHIFT (HI)
|
||||
|
||||
0001 LSHIFT (HI, OR)
|
||||
|
||||
0010 LSHIFT (LO)
|
||||
|
||||
0011 LSHIFT (LO, OR)
|
||||
|
||||
0100 ASHIFT (HI)
|
||||
|
||||
0101 ASHIFT (HI, OR)
|
||||
|
||||
0110 ASHIFT (LO)
|
||||
|
||||
0111 ASHIFT (LO, OR)
|
||||
|
||||
1000 NORM (HI)
|
||||
|
||||
1001 NORM (HI, OR)
|
||||
|
||||
1010 NORM (LO)
|
||||
|
||||
1011 NORM (LO, OR)
|
||||
|
||||
1100 EXP (HI)
|
||||
|
||||
1101 EXP (HIX)
|
||||
|
||||
1110 EXP (LO)
|
||||
|
||||
1111 Derive Block Exponent
|
||||
|
||||
|
||||
|
||||
|
||||
9-16 ADSP-219x Instruction Set Reference
|
||||
I and M Codes
|
||||
Table 9-7 on page 9-17 lists the DAG index and modify register codes
|
||||
used by the following instruction types. The G bit (DAG1/DAG2) determines
|
||||
which group of I (index) and M (modify) registers.
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23.
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 19: Indirect Jump/Call” on page 9-41
|
||||
• “Type 21: Modify DagI” on page 9-43
|
||||
• “Type 21a: Modify DagI” on page 9-44
|
||||
• “Type 22: DM/PM «··· Data16” on page 9-45
|
||||
• “Type 29: Dreg «···» DM” on page 9-51
|
||||
• “Type 32: Any Reg «···» PM/DM” on page 9-54
|
||||
|
||||
Table 9-7. I and M codes
|
||||
|
||||
DAG1 (G=0) DAG2 (G=1)
|
||||
|
||||
Code I M I M
|
||||
|
||||
00 I0 M0 I4 M4
|
||||
|
||||
01 I1 M1 I5 M5
|
||||
|
||||
10 I2 M2 I6 M6
|
||||
|
||||
11 I3 M3 I7 M7
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-17
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
DMI, DMM, PMI, and PMM Codes
|
||||
Table 9-8 lists the DAG index and modify register codes used by “Type 1:
|
||||
Compute | DregX«···DM | DregY«···PM” on page 9-21.
|
||||
|
||||
Table 9-8. DMI, DMM, PMI, PMM codes
|
||||
|
||||
Code DMI DMM PMI PMM
|
||||
|
||||
00 I0 M0 I4 M4
|
||||
|
||||
01 I1 M1 I5 M5
|
||||
|
||||
10 I2 M2 I6 M6
|
||||
|
||||
11 I3 M3 I7 M7
|
||||
|
||||
|
||||
IREG/MREG Codes
|
||||
Table 9-9 lists the Ireg and Mreg codes used by “Type 3: Dreg/Ireg/Mreg
|
||||
«···» DM/PM” on page 9-22 to specify a DAG index or modify register.
|
||||
|
||||
Table 9-9. Ireg, Mreg codes
|
||||
|
||||
Code Register Code Register
|
||||
|
||||
0000 I0 1000 M0
|
||||
|
||||
0001 I1 1001 M1
|
||||
|
||||
0010 I2 1010 M2
|
||||
|
||||
0011 I3 1011 M3
|
||||
|
||||
0100 I4 1100 M4
|
||||
|
||||
0101 I5 1101 M5
|
||||
|
||||
|
||||
|
||||
|
||||
9-18 ADSP-219x Instruction Set Reference
|
||||
Table 9-9. Ireg, Mreg codes (Cont’d)
|
||||
|
||||
Code Register Code Register
|
||||
|
||||
0110 I6 1110 M6
|
||||
|
||||
0111 I7 1111 M7
|
||||
|
||||
|
||||
XOP and YOP Codes
|
||||
Table 9-10 on page 9-19 lists the XOP and YOP codes used by these
|
||||
instructions:
|
||||
• “Type 1: Compute | DregX«···DM | DregY«···PM” on page 9-21
|
||||
• “Type 4: Compute | Dreg «···» DM/PM” on page 9-23
|
||||
• “Type 8: Compute | Dreg1 «··· Dreg2” on page 9-26
|
||||
• “Type 9: Compute” on page 9-27
|
||||
• “Type 12: Shift | Dreg «···» DM/PM” on page 9-35
|
||||
• “Type 23: Divide primitive, DIVQ” on page 9-47
|
||||
• “Type 24: Divide primitive, DIVS” on page 9-48
|
||||
|
||||
Table 9-10. XOP/YOP codes
|
||||
|
||||
XOP YOP
|
||||
|
||||
Code ALU MAC Shift Code ALU MAC
|
||||
|
||||
000 AX0 MX0 SI 00 AY0 MY0
|
||||
|
||||
001 AX1 MX1 SR2 01 AY1 MY1
|
||||
|
||||
010 AR AR AR 10 AF SR1
|
||||
|
||||
|
||||
|
||||
|
||||
ADSP-219x Instruction Set Reference 9-19
|
||||
Instruction Opcodes
|
||||
|
||||
|
||||
|
||||
|
||||
Table 9-10. XOP/YOP codes
|
||||
|
||||
XOP YOP
|
||||
|
||||
Code ALU MAC Shift Code ALU MAC
|
||||
|
||||
011 MR0 MR0 MR0 11 0 0
|
||||
|
||||
100 MR1 MR1 MR1
|
||||
|
||||
101 MR2 MR2 MR2
|
||||
|
||||
110 SR0 SR0 SR0
|
||||
|
||||
111 SR1 SR1 SR1
|
||||
|
||||
|
||||
|
||||
Opcode Definitions
|
||||
Reference in New Issue
Block a user