Type 12: SF is 4 bits (15-12), D is bit11 (not SF=3bits, D=bit12).
Verified all 8 SF variants against assembler: LSHIFT/ASHIFT,
HI/LO, plain/OR. FIR output scaling chain now correct.
TESTING.md: Synced with actual verification status.
34 of 37 types now assembler-verified.
Only Type 22/22a (2-word data write), Type 31 (IDLE), and
Type 32a (DAG store+transfer) remain structural-only.
Removed build artifacts (.o, .elf) from examples/build/.
Assembler-verified and fixed:
- Type 12: XOP field corrected to bits10-8 (was bits11-9)
- Type 14: SF=4bits, XREG uses reg0[] not xop_shift[] (was 3-bit OOB)
- Type 16: XREG uses reg0[] (was xop_shift[], 4-bit index OOB)
- Type 19: I-reg field at bits3-2 (was bits1-0), now correct for jump(i2)
- Type 26: Push/Pop encoding is 10/11 not 01/10;
PPP=bits6-5, LPP=bits4-3 (was bits6-4, bits3-2)
All 6 variants verified: push/pop sts, loop, pc
Assembler-verified unchanged:
- Type 21/21a: MODIFY correct
- Type 23/24: DIVQ/DIVS correct
- Type 29: DM immediate modify read/write correct
- Type 32: Any Reg <-> DM read/write correct
- Type 34/35: IO/System register read/write correct
- Type 36: LJUMP 2-word correct
- Type 37: SETINT/CLRINT correct
Remaining note: Type 12 SF field may use a different mapping
than sf_names[] for combined shift+memory ops (ASHIFT encodes
as SF=2 not SF=4). Needs further investigation.
Type 9 Constant-YOP: Implement exact constant table from docs.
Index = (YY<<2)|CC, value = 1<<idx for BO=01, -(1<<idx)-1
for BO=11. Special case idx=15: -32768 / +32767.
(was: simple cc with optional negate, completely wrong values)
Type 18: Fix DIS encoding to check for bit pattern 10 (was 01).
Verified all 8 modes against assembler: ENA/DIS for
AS, MM, BR, TI all correct.
Truncation guards: Use saved 'avail' from original op->size
instead of checking op->size after it was set to 3.
(was: always true, guards never triggered)
- DDREG: fixed to bits 7-4 (was bits 8-6, mixed XOP bit into dest)
- SDREG: fixed to bits 3-0 (was bits 5-0, included foreign bits)
- Dest/src registers now correctly use reg0[] table (was xop_alu[])
- NONE pattern: check full bits 7-0 == 0xAA (was only bits 5-0)
- XOP/YOP tables now follow AMF type (MAC vs ALU), not Z bit
- Output format: f(xop, yop), ddreg = sdreg (matches ADI syntax)
- Verified against assembler output for all three Type 8 variants:
ALU+move, MAC+move, and NONE=ALU status-only
- Full regression: isa_test.bin, fir.bin, iir.bin all unchanged
- Fix Type 1 multifunction: AMF=bits17-13, DD=bits19-18, PD=bits21-20
(was off by one bit, causing wrong MAC decode on real firmware)
- Add FIR filter ROM (fir.bin): 52 instructions, assembled from AD example
- Add IIR biquad ROM (iir.bin): 28 instructions, assembled from AD example
- Add open21xx-compatible source files (build/fir.dsp, build/iir.dsp)
- Both ROMs disassemble correctly showing expected DSP patterns:
MAC+dual-read kernels, DO UNTIL loops, ASHIFT scaling, RTS(DB)
- Full regression: isa_test.bin unchanged
